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/************************
*       GCD
*************************/
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
 
module gcd #(
parameter GCDw=32
 
)( clk, reset, enable, in1, in2, done, gcd);
        input clk, reset;
        input [GCDw-1 : 0] in1, in2;
        output [GCDw-1 : 0] gcd;
        input enable;
        output done;
        wire ldG, ldP, ldQ, selP0, selQ0, selP, selQ;
        wire AeqB, AltB;
 
        gcd_cu CU(
                .clk (clk),
                .reset (reset),
                .AeqB (AeqB),
                .AltB (AltB),
                .enable (enable),
                .ldG (ldG),
                .ldP (ldP),
                .ldQ (ldQ),
                .selP0 (selP0),
                .selQ0 (selQ0),
                .selP (selP),
                .selQ (selQ),
                .done (done)
        );
 
 
        gcd_dpu #(
                .GCDw(GCDw)
        )DPU(
                .clk (clk),
                .reset (reset),
                .in1 (in1),
                .in2 (in2),
                .gcd (gcd),
                .AeqB (AeqB),
                .AltB (AltB),
                .ldG  (ldG),
                .ldP (ldP),
                .ldQ (ldQ),
                .selP0 (selP0),
                .selQ0 (selQ0),
                .selP (selP),
                .selQ (selQ)
                );
 
 
endmodule
 
 
 
 
/************************
*       gcd_cu
*************************/
 
module gcd_cu (clk, reset, ldG, ldP, ldQ, selP0, selQ0, selP, selQ, AeqB, AltB, done, enable);
        input clk, reset;
        input AeqB, AltB, enable;
        output ldG, ldP, ldQ, selP0, selQ0, selP, selQ, done;
        reg ldG, ldP, ldQ, selP0, selQ0, selP, selQ, done;
 
 
        //State encoding 
        parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
        reg [1:0] y;
        always @ (posedge reset or posedge clk) begin
                if (reset == 1) y <= S0;
                else begin
                        case (y)
                                S0: begin if (enable == 1) y <= S1;
                                        else y <= S0;
                                end
                                S1: begin if (AeqB == 1) y <= S2;
                                        else y <= S1;
                                end
                                S2: begin if (enable == 0) y <= S0;
                                        else y <= S2;
                                end
                                default: y <= S0;
                        endcase
                end
        end
 
 
        always @ (y or enable or AeqB or AltB) begin
                ldG = 1'b0; ldP = 1'b0; ldQ = 1'b0;
                selP0 = 1'b0;
                selQ0 = 1'b0;
                selP = 1'b0;
                selQ = 1'b0;
                done = 1'b0;
                case (y)
                S0:     begin
                        done = 1'b1;
                        if (enable == 1)begin
                                selP0 = 1; ldP = 1; selQ0 = 1; ldQ = 1; done = 0;
                        end
                end
 
                S1: begin
                        if (AeqB == 1) begin
                                ldG = 1;
                                done = 1;
                        end
                        else if (AltB == 1) begin
                                ldQ = 1;
                        end
                        else begin
                                ldP = 1; selP = 1; selQ = 1;
                        end
                end
                S2: begin
                        ldG = 1;
                        done = 1;
                end
                default: ;
                endcase
                end
        endmodule
 
 
 
/************************
*       gcd_dpu
*************************/
 
module gcd_dpu #(
        parameter GCDw=32
 
)( clk, reset, in1, in2, gcd, ldG, ldP, ldQ, selP0, selQ0, selP, selQ, AeqB, AltB);
        input clk, reset;
        input [GCDw-1:0] in1, in2;
        output [GCDw-1:0]  gcd;
        input ldG, ldP, ldQ, selP0, selQ0, selP, selQ;
        output AeqB, AltB;
        reg [GCDw-1:0]  reg_P, reg_Q;
        wire [GCDw-1:0]  wire_ALU;
        reg [GCDw-1:0]  gcd;
        wire AeqB, AltB;
        //RegP with Multiplex 2:1
        always @ (posedge clk or posedge reset)begin
                if (reset == 1) reg_P <= 0;
                else begin
                        if (ldP == 1)begin
                                if (selP0==1) reg_P <= in1;
                                else reg_P <= wire_ALU;
                        end
                end
        end
 
                //RegQ with Multiplex 2:1
        always @ (posedge clk or posedge reset) begin
                if (reset == 1) reg_Q <= 0;
                else begin
                        if (ldQ == 1)begin
                                if (selQ0==1) reg_Q <= in2;
                                else reg_Q <= wire_ALU;
                        end
                end
        end
 
        //RegG with enable signal
        always @ (posedge clk or posedge reset)begin
                if (reset == 1) gcd <= {GCDw{1'b0}};
                else begin
                        if (ldG == 1) gcd <= reg_P;
                end
        end
 
        //Comparator
        assign AeqB = (reg_P == reg_Q)? 1'b1 : 1'b0;
        assign AltB = (reg_P < reg_Q) ? 1'b1 : 1'b0;
 
        //Subtractor
        assign wire_ALU = ((selP == 1) & (selQ == 1)) ? (reg_P - reg_Q) : (reg_Q - reg_P);
endmodule
 

Line No.	Rev	Author	Line
1	48	alirezamon	`/************************`
2			`* GCD`
3			`*************************/`
4
5			`// synthesis translate_off`
6			`timescale 1ns / 1ps
7			`// synthesis translate_on`
8
9
10			`module gcd #(`
11			`parameter GCDw=32`
12
13			`)( clk, reset, enable, in1, in2, done, gcd);`
14			`input clk, reset;`
15			`input [GCDw-1 : 0] in1, in2;`
16			`output [GCDw-1 : 0] gcd;`
17			`input enable;`
18			`output done;`
19			`wire ldG, ldP, ldQ, selP0, selQ0, selP, selQ;`
20			`wire AeqB, AltB;`
21
22			`gcd_cu CU(`
23			`.clk (clk),`
24			`.reset (reset),`
25			`.AeqB (AeqB),`
26			`.AltB (AltB),`
27			`.enable (enable),`
28			`.ldG (ldG),`
29			`.ldP (ldP),`
30			`.ldQ (ldQ),`
31			`.selP0 (selP0),`
32			`.selQ0 (selQ0),`
33			`.selP (selP),`
34			`.selQ (selQ),`
35			`.done (done)`
36			`);`
37
38
39			`gcd_dpu #(`
40			`.GCDw(GCDw)`
41			`)DPU(`
42			`.clk (clk),`
43			`.reset (reset),`
44			`.in1 (in1),`
45			`.in2 (in2),`
46			`.gcd (gcd),`
47			`.AeqB (AeqB),`
48			`.AltB (AltB),`
49			`.ldG (ldG),`
50			`.ldP (ldP),`
51			`.ldQ (ldQ),`
52			`.selP0 (selP0),`
53			`.selQ0 (selQ0),`
54			`.selP (selP),`
55			`.selQ (selQ)`
56			`);`
57
58
59			`endmodule`
60
61
62
63
64			`/************************`
65			`* gcd_cu`
66			`*************************/`
67
68			`module gcd_cu (clk, reset, ldG, ldP, ldQ, selP0, selQ0, selP, selQ, AeqB, AltB, done, enable);`
69			`input clk, reset;`
70			`input AeqB, AltB, enable;`
71			`output ldG, ldP, ldQ, selP0, selQ0, selP, selQ, done;`
72			`reg ldG, ldP, ldQ, selP0, selQ0, selP, selQ, done;`
73
74
75			`//State encoding`
76			`parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;`
77			`reg [1:0] y;`
78			`always @ (posedge reset or posedge clk) begin`
79			`if (reset == 1) y <= S0;`
80			`else begin`
81			`case (y)`
82			`S0: begin if (enable == 1) y <= S1;`
83			`else y <= S0;`
84			`end`
85			`S1: begin if (AeqB == 1) y <= S2;`
86			`else y <= S1;`
87			`end`
88			`S2: begin if (enable == 0) y <= S0;`
89			`else y <= S2;`
90			`end`
91			`default: y <= S0;`
92			`endcase`
93			`end`
94			`end`
95
96
97			`always @ (y or enable or AeqB or AltB) begin`
98			`ldG = 1'b0; ldP = 1'b0; ldQ = 1'b0;`
99			`selP0 = 1'b0;`
100			`selQ0 = 1'b0;`
101			`selP = 1'b0;`
102			`selQ = 1'b0;`
103			`done = 1'b0;`
104			`case (y)`
105			`S0: begin`
106			`done = 1'b1;`
107			`if (enable == 1)begin`
108			`selP0 = 1; ldP = 1; selQ0 = 1; ldQ = 1; done = 0;`
109			`end`
110			`end`
111
112			`S1: begin`
113			`if (AeqB == 1) begin`
114			`ldG = 1;`
115			`done = 1;`
116			`end`
117			`else if (AltB == 1) begin`
118			`ldQ = 1;`
119			`end`
120			`else begin`
121			`ldP = 1; selP = 1; selQ = 1;`
122			`end`
123			`end`
124			`S2: begin`
125			`ldG = 1;`
126			`done = 1;`
127			`end`
128			`default: ;`
129			`endcase`
130			`end`
131			`endmodule`
132
133
134
135			`/************************`
136			`* gcd_dpu`
137			`*************************/`
138
139			`module gcd_dpu #(`
140			`parameter GCDw=32`
141
142			`)( clk, reset, in1, in2, gcd, ldG, ldP, ldQ, selP0, selQ0, selP, selQ, AeqB, AltB);`
143			`input clk, reset;`
144			`input [GCDw-1:0] in1, in2;`
145			`output [GCDw-1:0] gcd;`
146			`input ldG, ldP, ldQ, selP0, selQ0, selP, selQ;`
147			`output AeqB, AltB;`
148			`reg [GCDw-1:0] reg_P, reg_Q;`
149			`wire [GCDw-1:0] wire_ALU;`
150			`reg [GCDw-1:0] gcd;`
151			`wire AeqB, AltB;`
152			`//RegP with Multiplex 2:1`
153			`always @ (posedge clk or posedge reset)begin`
154			`if (reset == 1) reg_P <= 0;`
155			`else begin`
156			`if (ldP == 1)begin`
157			`if (selP0==1) reg_P <= in1;`
158			`else reg_P <= wire_ALU;`
159			`end`
160			`end`
161			`end`
162
163			`//RegQ with Multiplex 2:1`
164			`always @ (posedge clk or posedge reset) begin`
165			`if (reset == 1) reg_Q <= 0;`
166			`else begin`
167			`if (ldQ == 1)begin`
168			`if (selQ0==1) reg_Q <= in2;`
169			`else reg_Q <= wire_ALU;`
170			`end`
171			`end`
172			`end`
173
174			`//RegG with enable signal`
175			`always @ (posedge clk or posedge reset)begin`
176			`if (reset == 1) gcd <= {GCDw{1'b0}};`
177			`else begin`
178			`if (ldG == 1) gcd <= reg_P;`
179			`end`
180			`end`
181
182			`//Comparator`
183			`assign AeqB = (reg_P == reg_Q)? 1'b1 : 1'b0;`
184			`assign AltB = (reg_P < reg_Q) ? 1'b1 : 1'b0;`
185
186			`//Subtractor`
187			`assign wire_ALU = ((selP == 1) & (selQ == 1)) ? (reg_P - reg_Q) : (reg_Q - reg_P);`
188			`endmodule`
189

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [Other/] [gcd.v] - Blame information for rev 48