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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [clk_source/] [xilinx_pll/] [xilinx_pll_sim/] [period_count.v] - Blame information for rev 48

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/*
 * period_count.v: Measures the length of the period of the input signal.
 * author: Till Mahlburg
 * year: 2019-2020
 * organization: Universität Leipzig
 * license: ISC
 *
 */
 
// synthesis translate_off
 
`timescale 1 ns / 1 ps
 
module period_count #(
        /* set the precision of the period count */
        parameter RESOLUTION = 0.01) (
        input RST,
        input PWRDWN,
        input clk,
        output reg [31:0] period_length_1000);
 
        integer period_counter;
 
        /* count up continuously with the given resolution */
        always begin
                #0.001
                if (RST) begin
                        period_counter <= 0;
                end else begin
                        period_counter <= period_counter + 1;
                end
                #(RESOLUTION - 0.001);
        end
 
        /* output counted value and reset counter on every rising clk edge */
        always @(posedge clk or posedge RST or posedge PWRDWN) begin
                if (PWRDWN || RST) begin
                        period_length_1000 <= 0;
                end else begin
                        period_length_1000 <= (period_counter * RESOLUTION * 1000);
                        period_counter <= 0;
                end
        end
 
endmodule
 
// synthesis translate_on

Line No.	Rev	Author	Line
1	48	alirezamon	`/*`
2			`* period_count.v: Measures the length of the period of the input signal.`
3			`* author: Till Mahlburg`
4			`* year: 2019-2020`
5			`* organization: Universität Leipzig`
6			`* license: ISC`
7			`*`
8			`*/`
9
10			`// synthesis translate_off`
11
12			`timescale 1 ns / 1 ps
13
14			`module period_count #(`
15			`/* set the precision of the period count */`
16			`parameter RESOLUTION = 0.01) (`
17			`input RST,`
18			`input PWRDWN,`
19			`input clk,`
20			`output reg [31:0] period_length_1000);`
21
22			`integer period_counter;`
23
24			`/* count up continuously with the given resolution */`
25			`always begin`
26			`#0.001`
27			`if (RST) begin`
28			`period_counter <= 0;`
29			`end else begin`
30			`period_counter <= period_counter + 1;`
31			`end`
32			`#(RESOLUTION - 0.001);`
33			`end`
34
35			`/* output counted value and reset counter on every rising clk edge */`
36			`always @(posedge clk or posedge RST or posedge PWRDWN) begin`
37			`if (PWRDWN \|\| RST) begin`
38			`period_length_1000 <= 0;`
39			`end else begin`
40			`period_length_1000 <= (period_counter * RESOLUTION * 1000);`
41			`period_counter <= 0;`
42			`end`
43			`end`
44
45			`endmodule`
46
47			`// synthesis translate_on`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [clk_source/] [xilinx_pll/] [xilinx_pll_sim/] [period_count.v] - Blame information for rev 48