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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [clk_source/] [xilinx_pll/] [xilinx_pll_sim/] [plle2_base.v] - Blame information for rev 48

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1 48 alirezamon 
/*
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 * plle2_base.v: Simulates the PLLE2_BASE pll of the xilinx 7 series. This
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 * is just a wrapper around the actual logic found in pll.v
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 * author: Till Mahlburg
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 * year: 2019-2020
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 * organization: Universität Leipzig
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 * license: ISC
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 *
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 */
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// synthesis translate_off
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`timescale 1 ns / 1 ps
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/* A reference for the interface can be found in Xilinx UG953 page 509ff */
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module PLLE2_BASE #(
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        /* not implemented */
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        parameter BANDWIDTH                     = "OPTIMIZED",
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        parameter CLKFBOUT_MULT                 = 5,
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        parameter CLKFBOUT_PHASE                = 0.0,
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        /* is ignored, but should be set */
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        parameter CLKIN1_PERIOD                 = 0.0,
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        parameter CLKOUT0_DIVIDE                = 1,
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        parameter CLKOUT1_DIVIDE                = 1,
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        parameter CLKOUT2_DIVIDE                = 1,
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        parameter CLKOUT3_DIVIDE                = 1,
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        parameter CLKOUT4_DIVIDE                = 1,
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        parameter CLKOUT5_DIVIDE                = 1,
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        parameter CLKOUT0_DUTY_CYCLE    = 0.5,
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        parameter CLKOUT1_DUTY_CYCLE    = 0.5,
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        parameter CLKOUT2_DUTY_CYCLE    = 0.5,
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        parameter CLKOUT3_DUTY_CYCLE    = 0.5,
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        parameter CLKOUT4_DUTY_CYCLE    = 0.5,
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        parameter CLKOUT5_DUTY_CYCLE    = 0.5,
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        parameter CLKOUT0_PHASE                 = 0.0,
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        parameter CLKOUT1_PHASE                 = 0.0,
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        parameter CLKOUT2_PHASE                 = 0.0,
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        parameter CLKOUT3_PHASE                 = 0.0,
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        parameter CLKOUT4_PHASE                 = 0.0,
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        parameter CLKOUT5_PHASE                 = 0.0,
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        parameter DIVCLK_DIVIDE                 = 1,
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        /* both not implemented */
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        parameter REF_JITTER1                   = 0.0,
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        parameter STARTUP_WAIT                  = "FALSE",
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        /* Setting the FPGA model and speed grade allows a more realistic
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         * simulation. Default values are the most restrictive */
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        parameter FPGA_TYPE                             = "ARTIX",
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        parameter SPEED_GRADE                   = "-1")(
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        output  CLKOUT0,
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        output  CLKOUT1,
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        output  CLKOUT2,
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        output  CLKOUT3,
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        output  CLKOUT4,
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        output  CLKOUT5,
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        /* PLL feedback output. */
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        output  CLKFBOUT,
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        output  LOCKED,
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        input   CLKIN1,
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        /* PLL feedback input. Is ignored in this implementation, but should be connected to CLKFBOUT for internal feedback. */
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        input   CLKFBIN,
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        /* Used to power down instatiated but unused PLLs */
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        input   PWRDWN,
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        input   RST);
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        wire    [15:0] DO;
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        wire    DRDY;
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        plle2_base_sim #(
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                .BANDWIDTH(BANDWIDTH),
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                .CLKFBOUT_MULT_F(CLKFBOUT_MULT),
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                .CLKFBOUT_PHASE(CLKFBOUT_PHASE),
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                .CLKIN1_PERIOD(CLKIN1_PERIOD),
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                .CLKIN2_PERIOD(0.000),
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                .CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE),
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                .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
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                .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
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                .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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                .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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                .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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                .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
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                .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
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                .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
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                .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
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                .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
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                .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
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                .CLKOUT0_PHASE(CLKOUT0_PHASE),
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                .CLKOUT1_PHASE(CLKOUT1_PHASE),
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                .CLKOUT2_PHASE(CLKOUT2_PHASE),
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                .CLKOUT3_PHASE(CLKOUT3_PHASE),
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                .CLKOUT4_PHASE(CLKOUT4_PHASE),
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                .CLKOUT5_PHASE(CLKOUT5_PHASE),
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                .DIVCLK_DIVIDE(DIVCLK_DIVIDE),
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                .REF_JITTER1(REF_JITTER1),
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                .REF_JITTER2(0.010),
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                .STARTUP_WAIT(STARTUP_WAIT),
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                .COMPENSATION("ZHOLD"),
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                .MODULE_TYPE("PLLE2_BASE"),
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                .FPGA_TYPE(FPGA_TYPE),
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                .SPEED_GRADE(SPEED_GRADE))
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        plle2_base (
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                .CLKOUT0(CLKOUT0),
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                .CLKOUT1(CLKOUT1),
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                .CLKOUT2(CLKOUT2),
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                .CLKOUT3(CLKOUT3),
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                .CLKOUT4(CLKOUT4),
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                .CLKOUT5(CLKOUT5),
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                .CLKOUT6(),
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                .CLKOUT0B(),
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                .CLKOUT1B(),
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                .CLKOUT2B(),
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                .CLKOUT3B(),
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                .CLKFBOUTB(),
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                .CLKFBOUT(CLKFBOUT),
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                .LOCKED(LOCKED),
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                .CLKIN1(CLKIN1),
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                .CLKIN2(1'b0),
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                .CLKINSEL(1'b1),
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                .PWRDWN(PWRDWN),
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                .RST(RST),
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                .CLKFBIN(CLKFBIN),
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                .DADDR(7'h00),
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                .DCLK(1'b0),
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                .DEN(1'b0),
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                .DWE(1'b0),
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                .DI(16'h0),
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                .DO(DO),
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                .DRDY(DRDY)
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        );
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endmodule
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// synthesis translate_on
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