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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ethmac/] [rtl/] [eth_fifo.v] - Blame information for rev 48

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_fifo.v                                                  ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/04/22 13:45:52  mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2  2002/03/25 13:33:04  mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1  2002/02/05 16:44:39  mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still  need
// to be fixed.
//
//
 
`include "ethmac_defines.v"
`include "timescale.v"
 
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
                 almost_full, full, almost_empty, empty, cnt);
 
parameter DATA_WIDTH    = 32;
parameter DEPTH         = 8;
parameter CNT_WIDTH     = 4;
 
input                     clk;
input                     reset;
input                     write;
input                     read;
input                     clear;
input   [DATA_WIDTH-1:0]  data_in;
 
output  [DATA_WIDTH-1:0]  data_out;
output                    almost_full;
output                    full;
output                    almost_empty;
output                    empty;
output  [CNT_WIDTH-1:0]   cnt;
 
`ifdef ETH_FIFO_XILINX
`else
  `ifdef ETH_ALTERA_ALTSYNCRAM
  `else
    reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1];
    reg     [DATA_WIDTH-1:0]  data_out;
  `endif
`endif
 
reg     [CNT_WIDTH-1:0]   cnt;
reg     [CNT_WIDTH-2:0]   read_pointer;
reg     [CNT_WIDTH-2:0]   write_pointer;
 
 
always @ (posedge clk or posedge reset)
begin
  if(reset)
    cnt <= 0;
  else
  if(clear)
    cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
  else
  if(read ^ write)
    if(read)
      cnt <= cnt - 1;
    else
      cnt <= cnt + 1;
end
 
 
always @ (posedge clk or posedge reset)
begin
  if(reset)
    read_pointer <= 0;
  else
  if(clear)
    read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
  else
  if(read & ~empty)
    read_pointer <= read_pointer + 1'b1;
end
 
always @ (posedge clk or posedge reset)
begin
  if(reset)
    write_pointer <= 0;
  else
  if(clear)
    write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
  else
  if(write & ~full)
    write_pointer <= write_pointer + 1'b1;
end
 
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full  = cnt == DEPTH;
assign almost_full  = &cnt[CNT_WIDTH-2:0];
 
 
 
`ifdef ETH_FIFO_XILINX
  xilinx_dist_ram_16x32 fifo
  ( .data_out(data_out),
    .we(write & ~full),
    .data_in(data_in),
    .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
    .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
    .wclk(clk)
  );
`else   // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
 
 
 
/*
  altera_dpram_16x32  altera_dpram_16x32_inst
  (
    .data             (data_in),
    .wren             (write & ~full),
    .wraddress        (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
    .rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
    .clock            (clk),
    .q                (data_out)
  );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
 
  alt_dpram     alt_dpram_inst (
        .clock ( clk ),
        .data ( data_in ),
        .rdaddress ( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
        .wraddress ( clear ? {CNT_WIDTH-1{1'b0}} : write_pointer ),
        .wren ( write & ~full ),
        .q ( data_out )
        );
*/
 
        eth_simple_dual_port_ram
        #(
                .Dw(DATA_WIDTH),
                .Aw(CNT_WIDTH-1)
        )
        dpram
        (
                .data(data_in),
                .read_addr (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
                .write_addr(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
                .we( write & ~full),
                .clk(clk),
                .q(data_out)
        );
 
 
 
`else   // !ETH_ALTERA_ALTSYNCRAM
  always @ (posedge clk)
  begin
    if(write & clear)
      fifo[0] <= data_in;
    else
   if(write & ~full)
      fifo[write_pointer] <= data_in;
  end
 
 
  always @ (posedge clk)
  begin
    if(clear)
      data_out <= fifo[0];
    else
      data_out <= fifo[read_pointer];
  end
`endif  // !ETH_ALTERA_ALTSYNCRAM
`endif  // !ETH_FIFO_XILINX
 
 
endmodule

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ethmac/] [rtl/] [eth_fifo.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_fifo.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/project,ethmac ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.3 2002/04/22 13:45:52 mohor`
45			`// Generic ram or Xilinx ram can be used in fifo (selectable by setting`
46			`// ETH_FIFO_XILINX in eth_defines.v).`
47			`//`
48			`// Revision 1.2 2002/03/25 13:33:04 mohor`
49			`// When clear and read/write are active at the same time, cnt and pointers are`
50			`// set to 1.`
51			`//`
52			`// Revision 1.1 2002/02/05 16:44:39 mohor`
53			`// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200`
54			`// MHz. Statuses, overrun, control frame transmission and reception still need`
55			`// to be fixed.`
56			`//`
57			`//`
58
59			`include "ethmac_defines.v"
60			`include "timescale.v"
61
62			`module eth_fifo (data_in, data_out, clk, reset, write, read, clear,`
63			`almost_full, full, almost_empty, empty, cnt);`
64
65			`parameter DATA_WIDTH = 32;`
66			`parameter DEPTH = 8;`
67			`parameter CNT_WIDTH = 4;`
68
69			`input clk;`
70			`input reset;`
71			`input write;`
72			`input read;`
73			`input clear;`
74			`input [DATA_WIDTH-1:0] data_in;`
75
76			`output [DATA_WIDTH-1:0] data_out;`
77			`output almost_full;`
78			`output full;`
79			`output almost_empty;`
80			`output empty;`
81			`output [CNT_WIDTH-1:0] cnt;`
82
83			`ifdef ETH_FIFO_XILINX
84			`else
85			`ifdef ETH_ALTERA_ALTSYNCRAM
86			`else
87			`reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];`
88			`reg [DATA_WIDTH-1:0] data_out;`
89			`endif
90			`endif
91
92			`reg [CNT_WIDTH-1:0] cnt;`
93			`reg [CNT_WIDTH-2:0] read_pointer;`
94			`reg [CNT_WIDTH-2:0] write_pointer;`
95
96
97			`always @ (posedge clk or posedge reset)`
98			`begin`
99			`if(reset)`
100			`cnt <= 0;`
101			`else`
102			`if(clear)`
103			`cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};`
104			`else`
105			`if(read ^ write)`
106			`if(read)`
107			`cnt <= cnt - 1;`
108			`else`
109			`cnt <= cnt + 1;`
110			`end`
111
112
113			`always @ (posedge clk or posedge reset)`
114			`begin`
115			`if(reset)`
116			`read_pointer <= 0;`
117			`else`
118			`if(clear)`
119			`read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};`
120			`else`
121			`if(read & ~empty)`
122			`read_pointer <= read_pointer + 1'b1;`
123			`end`
124
125			`always @ (posedge clk or posedge reset)`
126			`begin`
127			`if(reset)`
128			`write_pointer <= 0;`
129			`else`
130			`if(clear)`
131			`write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};`
132			`else`
133			`if(write & ~full)`
134			`write_pointer <= write_pointer + 1'b1;`
135			`end`
136
137			`assign empty = ~(\|cnt);`
138			`assign almost_empty = cnt == 1;`
139			`assign full = cnt == DEPTH;`
140			`assign almost_full = &cnt[CNT_WIDTH-2:0];`
141
142
143
144			`ifdef ETH_FIFO_XILINX
145			`xilinx_dist_ram_16x32 fifo`
146			`( .data_out(data_out),`
147			`.we(write & ~full),`
148			`.data_in(data_in),`
149			`.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),`
150			`.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),`
151			`.wclk(clk)`
152			`);`
153			`else // !ETH_FIFO_XILINX
154			`ifdef ETH_ALTERA_ALTSYNCRAM
155
156
157
158			`/*`
159			`altera_dpram_16x32 altera_dpram_16x32_inst`
160			`(`
161			`.data (data_in),`
162			`.wren (write & ~full),`
163			`.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),`
164			`.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),`
165			`.clock (clk),`
166			`.q (data_out)`
167			`); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE`
168
169			`alt_dpram alt_dpram_inst (`
170			`.clock ( clk ),`
171			`.data ( data_in ),`
172			`.rdaddress ( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),`
173			`.wraddress ( clear ? {CNT_WIDTH-1{1'b0}} : write_pointer ),`
174			`.wren ( write & ~full ),`
175			`.q ( data_out )`
176			`);`
177			`*/`
178
179			`eth_simple_dual_port_ram`
180			`#(`
181			`.Dw(DATA_WIDTH),`
182			`.Aw(CNT_WIDTH-1)`
183			`)`
184			`dpram`
185			`(`
186			`.data(data_in),`
187			`.read_addr (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),`
188			`.write_addr(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),`
189			`.we( write & ~full),`
190			`.clk(clk),`
191			`.q(data_out)`
192			`);`
193
194
195
196			`else // !ETH_ALTERA_ALTSYNCRAM
197			`always @ (posedge clk)`
198			`begin`
199			`if(write & clear)`
200			`fifo[0] <= data_in;`
201			`else`
202			`if(write & ~full)`
203			`fifo[write_pointer] <= data_in;`
204			`end`
205
206
207			`always @ (posedge clk)`
208			`begin`
209			`if(clear)`
210			`data_out <= fifo[0];`
211			`else`
212			`data_out <= fifo[read_pointer];`
213			`end`
214			`endif // !ETH_ALTERA_ALTSYNCRAM
215			`endif // !ETH_FIFO_XILINX
216
217
218			`endmodule`