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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ethmac/] [rtl/] [eth_receivecontrol.v] - Blame information for rev 48

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_receivecontrol.v                                        ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/11/22 01:57:06  mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.3  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
//
//
//
//
//
 
 
`include "timescale.v"
 
 
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
                           RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
                          );
 
 
input       MTxClk;
input       MRxClk;
input       TxReset;
input       RxReset;
input [7:0] RxData;
input       RxValid;
input       RxStartFrm;
input       RxEndFrm;
input       RxFlow;
input       ReceiveEnd;
input [47:0]MAC;
input       DlyCrcEn;
input       TxDoneIn;
input       TxAbortIn;
input       TxStartFrmOut;
input       ReceivedLengthOK;
input       ReceivedPacketGood;
input       TxUsedDataOutDetected;
input       RxStatusWriteLatched_sync2;
input       r_PassAll;
 
output      Pause;
output      ReceivedPauseFrm;
output      AddressOK;
output      SetPauseTimer;
 
 
reg         Pause;
reg         AddressOK;                // Multicast or unicast address detected
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
reg  [2:0]  DlyCrcCnt;
reg  [4:0]  ByteCnt;
reg [15:0]  AssembledTimerValue;
reg [15:0]  LatchedTimerValue;
reg         ReceivedPauseFrm;
reg         ReceivedPauseFrmWAddr;
reg         PauseTimerEq0_sync1;
reg         PauseTimerEq0_sync2;
reg [15:0]  PauseTimer;
reg         Divider2;
reg  [5:0]  SlotTimer;
 
wire [47:0] ReservedMulticast;        // 0x0180C2000001
wire [15:0] TypeLength;               // 0x8808
wire        ResetByteCnt;             // 
wire        IncrementByteCnt;         // 
wire        ByteCntEq0;               // ByteCnt = 0
wire        ByteCntEq1;               // ByteCnt = 1
wire        ByteCntEq2;               // ByteCnt = 2
wire        ByteCntEq3;               // ByteCnt = 3
wire        ByteCntEq4;               // ByteCnt = 4
wire        ByteCntEq5;               // ByteCnt = 5
wire        ByteCntEq12;              // ByteCnt = 12
wire        ByteCntEq13;              // ByteCnt = 13
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq18;              // ByteCnt = 18
wire        DecrementPauseTimer;      // 
wire        PauseTimerEq0;            // 
wire        ResetSlotTimer;           // 
wire        IncrementSlotTimer;       // 
wire        SlotFinished;             // 
 
 
 
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
 
 
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    AddressOK <=  1'b0;
  else
  if(DetectionWindow & ByteCntEq0)
    AddressOK <=   RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
  else
  if(DetectionWindow & ByteCntEq1)
    AddressOK <=  (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq2)
    AddressOK <=  (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq3)
    AddressOK <=  (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq4)
    AddressOK <=  (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
  else
  if(DetectionWindow & ByteCntEq5)
    AddressOK <=  (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
  else
  if(ReceiveEnd)
    AddressOK <=  1'b0;
end
 
 
 
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    TypeLengthOK <=  1'b0;
  else
  if(DetectionWindow & ByteCntEq12)
    TypeLengthOK <=  ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
  else
  if(DetectionWindow & ByteCntEq13)
    TypeLengthOK <=  ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
  else
  if(ReceiveEnd)
    TypeLengthOK <=  1'b0;
end
 
 
 
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    OpCodeOK <=  1'b0;
  else
  if(ByteCntEq16)
    OpCodeOK <=  1'b0;
  else
    begin
      if(DetectionWindow & ByteCntEq14)
        OpCodeOK <=  ByteCntEq14 & RxData[7:0] == 8'h00;
 
      if(DetectionWindow & ByteCntEq15)
        OpCodeOK <=  ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
    end
end
 
 
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    ReceivedPauseFrmWAddr <=  1'b0;
  else
  if(ReceiveEnd)
    ReceivedPauseFrmWAddr <=  1'b0;
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
    ReceivedPauseFrmWAddr <=  1'b1;
end
 
 
 
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    AssembledTimerValue[15:0] <=  16'h0;
  else
  if(RxStartFrm)
    AssembledTimerValue[15:0] <=  16'h0;
  else
    begin
      if(DetectionWindow & ByteCntEq16)
        AssembledTimerValue[15:8] <=  RxData[7:0];
      if(DetectionWindow & ByteCntEq17)
        AssembledTimerValue[7:0] <=  RxData[7:0];
    end
end
 
 
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    DetectionWindow <=  1'b1;
  else
  if(ByteCntEq18)
    DetectionWindow <=  1'b0;
  else
  if(ReceiveEnd)
    DetectionWindow <=  1'b1;
end
 
 
 
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    LatchedTimerValue[15:0] <=  16'h0;
  else
  if(DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
    LatchedTimerValue[15:0] <=  AssembledTimerValue[15:0];
  else
  if(ReceiveEnd)
    LatchedTimerValue[15:0] <=  16'h0;
end
 
 
 
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    DlyCrcCnt <=  3'h0;
  else
  if(RxValid & RxEndFrm)
    DlyCrcCnt <=  3'h0;
  else
  if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
    DlyCrcCnt <=  DlyCrcCnt + 3'd1;
end
 
 
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 &
                          (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 
 
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    ByteCnt[4:0] <=  5'h0;
  else
  if(ResetByteCnt)
    ByteCnt[4:0] <=  5'h0;
  else
  if(IncrementByteCnt)
    ByteCnt[4:0] <=  ByteCnt[4:0] + 5'd1;
end
 
 
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
 
 
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
 
 
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    PauseTimer[15:0] <=  16'h0;
  else
  if(SetPauseTimer)
    PauseTimer[15:0] <=  LatchedTimerValue[15:0];
  else
  if(DecrementPauseTimer)
    PauseTimer[15:0] <=  PauseTimer[15:0] - 16'd1;
end
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
 
 
 
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    begin
      PauseTimerEq0_sync1 <=  1'b1;
      PauseTimerEq0_sync2 <=  1'b1;
    end
  else
    begin
      PauseTimerEq0_sync1 <=  PauseTimerEq0;
      PauseTimerEq0_sync2 <=  PauseTimerEq0_sync1;
    end
end
 
 
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    Pause <=  1'b0;
  else
  if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
    Pause <=  RxFlow & ~PauseTimerEq0_sync2;
end
 
 
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    Divider2 <=  1'b0;
  else
  if(|PauseTimer[15:0] & RxFlow)
    Divider2 <=  ~Divider2;
  else
    Divider2 <=  1'b0;
end
 
 
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
 
 
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    SlotTimer[5:0] <=  6'h0;
  else
  if(ResetSlotTimer)
    SlotTimer[5:0] <=  6'h0;
  else
  if(IncrementSlotTimer)
    SlotTimer[5:0] <=  SlotTimer[5:0] + 6'd1;
end
 
 
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
 
 
 
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    ReceivedPauseFrm <= 1'b0;
  else
  if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
    ReceivedPauseFrm <= 1'b0;
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
    ReceivedPauseFrm <= 1'b1;
end
 
 
endmodule

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ethmac/] [rtl/] [eth_receivecontrol.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_receivecontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/project,ethmac ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.4 2002/11/22 01:57:06 mohor`
45			`// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort`
46			`// synchronized.`
47			`//`
48			`// Revision 1.3 2002/01/23 10:28:16 mohor`
49			`// Link in the header changed.`
50			`//`
51			`// Revision 1.2 2001/10/19 08:43:51 mohor`
52			`// eth_timescale.v changed to timescale.v This is done because of the`
53			`// simulation of the few cores in a one joined project.`
54			`//`
55			`// Revision 1.1 2001/08/06 14:44:29 mohor`
56			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
57			`// Include files fixed to contain no path.`
58			`// File names and module names changed ta have a eth_ prologue in the name.`
59			`// File eth_timescale.v is used to define timescale`
60			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
61			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
62			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
63			`// is done due to the ASIC tools.`
64			`//`
65			`// Revision 1.1 2001/07/30 21:23:42 mohor`
66			`// Directory structure changed. Files checked and joind together.`
67			`//`
68			`// Revision 1.1 2001/07/03 12:51:54 mohor`
69			`// Initial release of the MAC Control module.`
70			`//`
71			`//`
72			`//`
73			`//`
74			`//`
75
76
77			`include "timescale.v"
78
79
80			`module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,`
81			`RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,`
82			`TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,`
83			`TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,`
84			`RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer`
85			`);`
86
87
88			`input MTxClk;`
89			`input MRxClk;`
90			`input TxReset;`
91			`input RxReset;`
92			`input [7:0] RxData;`
93			`input RxValid;`
94			`input RxStartFrm;`
95			`input RxEndFrm;`
96			`input RxFlow;`
97			`input ReceiveEnd;`
98			`input [47:0]MAC;`
99			`input DlyCrcEn;`
100			`input TxDoneIn;`
101			`input TxAbortIn;`
102			`input TxStartFrmOut;`
103			`input ReceivedLengthOK;`
104			`input ReceivedPacketGood;`
105			`input TxUsedDataOutDetected;`
106			`input RxStatusWriteLatched_sync2;`
107			`input r_PassAll;`
108
109			`output Pause;`
110			`output ReceivedPauseFrm;`
111			`output AddressOK;`
112			`output SetPauseTimer;`
113
114
115			`reg Pause;`
116			`reg AddressOK; // Multicast or unicast address detected`
117			`reg TypeLengthOK; // Type/Length field contains 0x8808`
118			`reg DetectionWindow; // Detection of the PAUSE frame is possible within this window`
119			`reg OpCodeOK; // PAUSE opcode detected (0x0001)`
120			`reg [2:0] DlyCrcCnt;`
121			`reg [4:0] ByteCnt;`
122			`reg [15:0] AssembledTimerValue;`
123			`reg [15:0] LatchedTimerValue;`
124			`reg ReceivedPauseFrm;`
125			`reg ReceivedPauseFrmWAddr;`
126			`reg PauseTimerEq0_sync1;`
127			`reg PauseTimerEq0_sync2;`
128			`reg [15:0] PauseTimer;`
129			`reg Divider2;`
130			`reg [5:0] SlotTimer;`
131
132			`wire [47:0] ReservedMulticast; // 0x0180C2000001`
133			`wire [15:0] TypeLength; // 0x8808`
134			`wire ResetByteCnt; //`
135			`wire IncrementByteCnt; //`
136			`wire ByteCntEq0; // ByteCnt = 0`
137			`wire ByteCntEq1; // ByteCnt = 1`
138			`wire ByteCntEq2; // ByteCnt = 2`
139			`wire ByteCntEq3; // ByteCnt = 3`
140			`wire ByteCntEq4; // ByteCnt = 4`
141			`wire ByteCntEq5; // ByteCnt = 5`
142			`wire ByteCntEq12; // ByteCnt = 12`
143			`wire ByteCntEq13; // ByteCnt = 13`
144			`wire ByteCntEq14; // ByteCnt = 14`
145			`wire ByteCntEq15; // ByteCnt = 15`
146			`wire ByteCntEq16; // ByteCnt = 16`
147			`wire ByteCntEq17; // ByteCnt = 17`
148			`wire ByteCntEq18; // ByteCnt = 18`
149			`wire DecrementPauseTimer; //`
150			`wire PauseTimerEq0; //`
151			`wire ResetSlotTimer; //`
152			`wire IncrementSlotTimer; //`
153			`wire SlotFinished; //`
154
155
156
157			`// Reserved multicast address and Type/Length for PAUSE control`
158			`assign ReservedMulticast = 48'h0180C2000001;`
159			`assign TypeLength = 16'h8808;`
160
161
162			`// Address Detection (Multicast or unicast)`
163			`always @ (posedge MRxClk or posedge RxReset)`
164			`begin`
165			`if(RxReset)`
166			`AddressOK <= 1'b0;`
167			`else`
168			`if(DetectionWindow & ByteCntEq0)`
169			`AddressOK <= RxData[7:0] == ReservedMulticast[47:40] \| RxData[7:0] == MAC[47:40];`
170			`else`
171			`if(DetectionWindow & ByteCntEq1)`
172			`AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] \| RxData[7:0] == MAC[39:32]) & AddressOK;`
173			`else`
174			`if(DetectionWindow & ByteCntEq2)`
175			`AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] \| RxData[7:0] == MAC[31:24]) & AddressOK;`
176			`else`
177			`if(DetectionWindow & ByteCntEq3)`
178			`AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] \| RxData[7:0] == MAC[23:16]) & AddressOK;`
179			`else`
180			`if(DetectionWindow & ByteCntEq4)`
181			`AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] \| RxData[7:0] == MAC[15:8]) & AddressOK;`
182			`else`
183			`if(DetectionWindow & ByteCntEq5)`
184			`AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] \| RxData[7:0] == MAC[7:0]) & AddressOK;`
185			`else`
186			`if(ReceiveEnd)`
187			`AddressOK <= 1'b0;`
188			`end`
189
190
191
192			`// TypeLengthOK (Type/Length Control frame detected)`
193			`always @ (posedge MRxClk or posedge RxReset )`
194			`begin`
195			`if(RxReset)`
196			`TypeLengthOK <= 1'b0;`
197			`else`
198			`if(DetectionWindow & ByteCntEq12)`
199			`TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);`
200			`else`
201			`if(DetectionWindow & ByteCntEq13)`
202			`TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;`
203			`else`
204			`if(ReceiveEnd)`
205			`TypeLengthOK <= 1'b0;`
206			`end`
207
208
209
210			`// Latch Control Frame Opcode`
211			`always @ (posedge MRxClk or posedge RxReset )`
212			`begin`
213			`if(RxReset)`
214			`OpCodeOK <= 1'b0;`
215			`else`
216			`if(ByteCntEq16)`
217			`OpCodeOK <= 1'b0;`
218			`else`
219			`begin`
220			`if(DetectionWindow & ByteCntEq14)`
221			`OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00;`
222
223			`if(DetectionWindow & ByteCntEq15)`
224			`OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;`
225			`end`
226			`end`
227
228
229			`// ReceivedPauseFrmWAddr (+Address Check)`
230			`always @ (posedge MRxClk or posedge RxReset )`
231			`begin`
232			`if(RxReset)`
233			`ReceivedPauseFrmWAddr <= 1'b0;`
234			`else`
235			`if(ReceiveEnd)`
236			`ReceivedPauseFrmWAddr <= 1'b0;`
237			`else`
238			`if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)`
239			`ReceivedPauseFrmWAddr <= 1'b1;`
240			`end`
241
242
243
244			`// Assembling 16-bit timer value from two 8-bit data`
245			`always @ (posedge MRxClk or posedge RxReset )`
246			`begin`
247			`if(RxReset)`
248			`AssembledTimerValue[15:0] <= 16'h0;`
249			`else`
250			`if(RxStartFrm)`
251			`AssembledTimerValue[15:0] <= 16'h0;`
252			`else`
253			`begin`
254			`if(DetectionWindow & ByteCntEq16)`
255			`AssembledTimerValue[15:8] <= RxData[7:0];`
256			`if(DetectionWindow & ByteCntEq17)`
257			`AssembledTimerValue[7:0] <= RxData[7:0];`
258			`end`
259			`end`
260
261
262			`// Detection window (while PAUSE detection is possible)`
263			`always @ (posedge MRxClk or posedge RxReset )`
264			`begin`
265			`if(RxReset)`
266			`DetectionWindow <= 1'b1;`
267			`else`
268			`if(ByteCntEq18)`
269			`DetectionWindow <= 1'b0;`
270			`else`
271			`if(ReceiveEnd)`
272			`DetectionWindow <= 1'b1;`
273			`end`
274
275
276
277			`// Latching Timer Value`
278			`always @ (posedge MRxClk or posedge RxReset )`
279			`begin`
280			`if(RxReset)`
281			`LatchedTimerValue[15:0] <= 16'h0;`
282			`else`
283			`if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)`
284			`LatchedTimerValue[15:0] <= AssembledTimerValue[15:0];`
285			`else`
286			`if(ReceiveEnd)`
287			`LatchedTimerValue[15:0] <= 16'h0;`
288			`end`
289
290
291
292			`// Delayed CEC counter`
293			`always @ (posedge MRxClk or posedge RxReset)`
294			`begin`
295			`if(RxReset)`
296			`DlyCrcCnt <= 3'h0;`
297			`else`
298			`if(RxValid & RxEndFrm)`
299			`DlyCrcCnt <= 3'h0;`
300			`else`
301			`if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])`
302			`DlyCrcCnt <= DlyCrcCnt + 3'd1;`
303			`end`
304
305
306			`assign ResetByteCnt = RxEndFrm;`
307			`assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 &`
308			`(~DlyCrcEn \| DlyCrcEn & DlyCrcCnt[2]);`
309
310
311			`// Byte counter`
312			`always @ (posedge MRxClk or posedge RxReset)`
313			`begin`
314			`if(RxReset)`
315			`ByteCnt[4:0] <= 5'h0;`
316			`else`
317			`if(ResetByteCnt)`
318			`ByteCnt[4:0] <= 5'h0;`
319			`else`
320			`if(IncrementByteCnt)`
321			`ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;`
322			`end`
323
324
325			`assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;`
326			`assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;`
327			`assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;`
328			`assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;`
329			`assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;`
330			`assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;`
331			`assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;`
332			`assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;`
333			`assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;`
334			`assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;`
335			`assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;`
336			`assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;`
337			`assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;`
338
339
340			`assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;`
341			`assign DecrementPauseTimer = SlotFinished & \|PauseTimer;`
342
343
344			`// PauseTimer[15:0]`
345			`always @ (posedge MRxClk or posedge RxReset)`
346			`begin`
347			`if(RxReset)`
348			`PauseTimer[15:0] <= 16'h0;`
349			`else`
350			`if(SetPauseTimer)`
351			`PauseTimer[15:0] <= LatchedTimerValue[15:0];`
352			`else`
353			`if(DecrementPauseTimer)`
354			`PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;`
355			`end`
356
357			`assign PauseTimerEq0 = ~(\|PauseTimer[15:0]);`
358
359
360
361			`// Synchronization of the pause timer`
362			`always @ (posedge MTxClk or posedge TxReset)`
363			`begin`
364			`if(TxReset)`
365			`begin`
366			`PauseTimerEq0_sync1 <= 1'b1;`
367			`PauseTimerEq0_sync2 <= 1'b1;`
368			`end`
369			`else`
370			`begin`
371			`PauseTimerEq0_sync1 <= PauseTimerEq0;`
372			`PauseTimerEq0_sync2 <= PauseTimerEq0_sync1;`
373			`end`
374			`end`
375
376
377			`// Pause signal generation`
378			`always @ (posedge MTxClk or posedge TxReset)`
379			`begin`
380			`if(TxReset)`
381			`Pause <= 1'b0;`
382			`else`
383			`if((TxDoneIn \| TxAbortIn \| ~TxUsedDataOutDetected) & ~TxStartFrmOut)`
384			`Pause <= RxFlow & ~PauseTimerEq0_sync2;`
385			`end`
386
387
388			`// Divider2 is used for incrementing the Slot timer every other clock`
389			`always @ (posedge MRxClk or posedge RxReset)`
390			`begin`
391			`if(RxReset)`
392			`Divider2 <= 1'b0;`
393			`else`
394			`if(\|PauseTimer[15:0] & RxFlow)`
395			`Divider2 <= ~Divider2;`
396			`else`
397			`Divider2 <= 1'b0;`
398			`end`
399
400
401			`assign ResetSlotTimer = RxReset;`
402			`assign IncrementSlotTimer = Pause & RxFlow & Divider2;`
403
404
405			`// SlotTimer`
406			`always @ (posedge MRxClk or posedge RxReset)`
407			`begin`
408			`if(RxReset)`
409			`SlotTimer[5:0] <= 6'h0;`
410			`else`
411			`if(ResetSlotTimer)`
412			`SlotTimer[5:0] <= 6'h0;`
413			`else`
414			`if(IncrementSlotTimer)`
415			`SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;`
416			`end`
417
418
419			`assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)`
420
421
422
423			`// Pause Frame received`
424			`always @ (posedge MRxClk or posedge RxReset)`
425			`begin`
426			`if(RxReset)`
427			`ReceivedPauseFrm <= 1'b0;`
428			`else`
429			`if(RxStatusWriteLatched_sync2 & r_PassAll \| ReceivedPauseFrm & (~r_PassAll))`
430			`ReceivedPauseFrm <= 1'b0;`
431			`else`
432			`if(ByteCntEq16 & TypeLengthOK & OpCodeOK)`
433			`ReceivedPauseFrm <= 1'b1;`
434			`end`
435
436
437			`endmodule`