OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ethmac/] [rtl/] [eth_txstatem.v] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 alirezamon
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txstatem.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/project,ethmac                     ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46
// Revision 1.5  2002/10/30 12:54:50  mohor
47
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
48
//
49
// Revision 1.4  2002/01/23 10:28:16  mohor
50
// Link in the header changed.
51
//
52
// Revision 1.3  2001/10/19 08:43:51  mohor
53
// eth_timescale.v changed to timescale.v This is done because of the
54
// simulation of the few cores in a one joined project.
55
//
56
// Revision 1.2  2001/09/11 14:17:00  mohor
57
// Few little NCSIM warnings fixed.
58
//
59
// Revision 1.1  2001/08/06 14:44:29  mohor
60
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
61
// Include files fixed to contain no path.
62
// File names and module names changed ta have a eth_ prologue in the name.
63
// File eth_timescale.v is used to define timescale
64
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
65
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
66
// and Mdo_OE. The bidirectional signal must be created on the top level. This
67
// is done due to the ASIC tools.
68
//
69
// Revision 1.1  2001/07/30 21:23:42  mohor
70
// Directory structure changed. Files checked and joind together.
71
//
72
// Revision 1.3  2001/06/19 18:16:40  mohor
73
// TxClk changed to MTxClk (as discribed in the documentation).
74
// Crc changed so only one file can be used instead of two.
75
//
76
// Revision 1.2  2001/06/19 10:38:07  mohor
77
// Minor changes in header.
78
//
79
// Revision 1.1  2001/06/19 10:27:57  mohor
80
// TxEthMAC initial release.
81
//
82
//
83
//
84
//
85
 
86
 
87
`include "timescale.v"
88
 
89
 
90
module eth_txstatem  (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
91
                      IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
92
                      StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
93
                      NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
94
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
95
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
96
                      StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
97
                     );
98
 
99
input MTxClk;
100
input Reset;
101
input ExcessiveDefer;
102
input CarrierSense;
103
input [6:0] NibCnt;
104
input [6:0] IPGT;
105
input [6:0] IPGR1;
106
input [6:0] IPGR2;
107
input FullD;
108
input TxStartFrm;
109
input TxEndFrm;
110
input TxUnderRun;
111
input Collision;
112
input UnderRun;
113
input StartTxDone;
114
input TooBig;
115
input NibCntEq7;
116
input NibCntEq15;
117
input MaxFrame;
118
input Pad;
119
input CrcEn;
120
input NibbleMinFl;
121
input RandomEq0;
122
input ColWindow;
123
input RetryMax;
124
input NoBckof;
125
input RandomEqByteCnt;
126
 
127
 
128
output StateIdle;         // Idle state
129
output StateIPG;          // IPG state
130
output StatePreamble;     // Preamble state
131
output [1:0] StateData;   // Data state
132
output StatePAD;          // PAD state
133
output StateFCS;          // FCS state
134
output StateJam;          // Jam state
135
output StateJam_q;        // Delayed Jam state
136
output StateBackOff;      // Backoff state
137
output StateDefer;        // Defer state
138
 
139
output StartFCS;          // FCS state will be activated in next clock
140
output StartJam;          // Jam state will be activated in next clock
141
output StartBackoff;      // Backoff state will be activated in next clock
142
output StartDefer;        // Defer state will be activated in next clock
143
output DeferIndication;
144
output StartPreamble;     // Preamble state will be activated in next clock
145
output [1:0] StartData;   // Data state will be activated in next clock
146
output StartIPG;          // IPG state will be activated in next clock
147
 
148
wire StartIdle;           // Idle state will be activated in next clock
149
wire StartPAD;            // PAD state will be activated in next clock
150
 
151
 
152
reg StateIdle;
153
reg StateIPG;
154
reg StatePreamble;
155
reg [1:0] StateData;
156
reg StatePAD;
157
reg StateFCS;
158
reg StateJam;
159
reg StateJam_q;
160
reg StateBackOff;
161
reg StateDefer;
162
reg Rule1;
163
 
164
 
165
// Defining the next state
166
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
167
 
168
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
169
 
170
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
171
 
172
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
173
 
174
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
175
 
176
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
177
 
178
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
179
                | ~Collision & StatePAD & NibbleMinFl & CrcEn;
180
 
181
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
182
 
183
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
184
 
185
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
186
                  | StateIdle & CarrierSense
187
                  | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
188
                  | StateBackOff & (TxUnderRun | RandomEqByteCnt)
189
                  | StartTxDone | TooBig;
190
 
191
assign DeferIndication = StateIdle & CarrierSense;
192
 
193
// Tx State Machine
194
always @ (posedge MTxClk or posedge Reset)
195
begin
196
  if(Reset)
197
    begin
198
      StateIPG        <=  1'b0;
199
      StateIdle       <=  1'b0;
200
      StatePreamble   <=  1'b0;
201
      StateData[1:0]  <=  2'b0;
202
      StatePAD        <=  1'b0;
203
      StateFCS        <=  1'b0;
204
      StateJam        <=  1'b0;
205
      StateJam_q      <=  1'b0;
206
      StateBackOff    <=  1'b0;
207
      StateDefer      <=  1'b1;
208
    end
209
  else
210
    begin
211
      StateData[1:0] <=  StartData[1:0];
212
      StateJam_q <=  StateJam;
213
 
214
      if(StartDefer | StartIdle)
215
        StateIPG <=  1'b0;
216
      else
217
      if(StartIPG)
218
        StateIPG <=  1'b1;
219
 
220
      if(StartDefer | StartPreamble)
221
        StateIdle <=  1'b0;
222
      else
223
      if(StartIdle)
224
        StateIdle <=  1'b1;
225
 
226
      if(StartData[0] | StartJam)
227
        StatePreamble <=  1'b0;
228
      else
229
      if(StartPreamble)
230
        StatePreamble <=  1'b1;
231
 
232
      if(StartFCS | StartJam)
233
        StatePAD <=  1'b0;
234
      else
235
      if(StartPAD)
236
        StatePAD <=  1'b1;
237
 
238
      if(StartJam | StartDefer)
239
        StateFCS <=  1'b0;
240
      else
241
      if(StartFCS)
242
        StateFCS <=  1'b1;
243
 
244
      if(StartBackoff | StartDefer)
245
        StateJam <=  1'b0;
246
      else
247
      if(StartJam)
248
        StateJam <=  1'b1;
249
 
250
      if(StartDefer)
251
        StateBackOff <=  1'b0;
252
      else
253
      if(StartBackoff)
254
        StateBackOff <=  1'b1;
255
 
256
      if(StartIPG)
257
        StateDefer <=  1'b0;
258
      else
259
      if(StartDefer)
260
        StateDefer <=  1'b1;
261
    end
262
end
263
 
264
 
265
// This sections defines which interpack gap rule to use
266
always @ (posedge MTxClk or posedge Reset)
267
begin
268
  if(Reset)
269
    Rule1 <=  1'b0;
270
  else
271
    begin
272
      if(StateIdle | StateBackOff)
273
        Rule1 <=  1'b0;
274
      else
275
      if(StatePreamble | FullD)
276
        Rule1 <=  1'b1;
277
    end
278
end
279
 
280
 
281
 
282
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.