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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [gpio/] [gpio.v] - Blame information for rev 48

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1 48 alirezamon 
/**********************************************************************
2 
**      File:  gpio.v
3 
**
4 
**
5 
**      Copyright (C) 2014-2017  Alireza Monemi
6 
**
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**      This file is part of ProNoC
8 
**
9 
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
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**      you can redistribute it and/or modify it under the terms of the GNU
11 
**      Lesser General Public License as published by the Free Software Foundation,
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**      either version 2 of the License, or (at your option) any later version.
13 
**
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**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
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**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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**      Public License for more details.
18 
**
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**      You should have received a copy of the GNU Lesser General Public
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**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
21 
**
22 
**
23 
**      Description:
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**      a simple wishbone compatible output/input port
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**      each port has three registers.
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**
27 
**        addr
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**              0        DIR_REG
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**              1       WRITE_REG       port 0
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**              2       READ_REG
31 
**
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**              32      DIR_REG
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**              33      WRITE_REG       port 1
34 
**              34      READ_REG
35 
**              .
36 
**              .
37 
**              .
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**
39 
*******************************************************************/
40 
 
41 
 
42 
 
43 
 
44 
// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
47 
 
48 
 
49 
 
50 
 
51 
 
52 
module gpio #(
53 
        parameter Aw           =   2,
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        parameter SELw         =   4,
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        parameter TAGw         =   3,
56 
        parameter PORT_WIDTH   =   1,
57 
        parameter Dw           =    PORT_WIDTH
58 
 
59 
 
60 
)
61 
(
62 
    clk,
63 
    reset,
64 
 
65 
  //wishbone bus interface
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    sa_dat_i,
67 
    sa_sel_i,
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    sa_addr_i,
69 
    sa_tag_i,
70 
    sa_stb_i,
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    sa_cyc_i,
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    sa_we_i,
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    sa_dat_o,
74 
    sa_ack_o,
75 
    sa_err_o,
76 
    sa_rty_o,
77 
 
78 
    port_io
79 
 
80 
 
81 
);
82 
 
83 
 
84 
        //registers num
85 
        localparam DIR_REG         =0;
86 
        localparam WRITE_REG       =1;
87 
        localparam READ_REG        =2;
88 
 
89 
 
90 
 
91 
    input                               clk;
92 
    input                               reset;
93 
 
94 
    //wishbone bus interface
95 
    input       [Dw-1       :   0]      sa_dat_i;
96 
    input       [SELw-1     :   0]      sa_sel_i;
97 
    input       [Aw-1       :   0]      sa_addr_i;
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    input       [TAGw-1     :   0]      sa_tag_i;
99 
    input                               sa_stb_i;
100 
    input                               sa_cyc_i;
101 
    input                               sa_we_i;
102 
 
103 
    output      [Dw-1       :   0]      sa_dat_o;
104 
    output  reg                         sa_ack_o;
105 
    output                              sa_err_o;
106 
    output                              sa_rty_o;
107 
 
108 
    inout   [PORT_WIDTH-1     :   0]    port_io;
109 
 
110 
 
111 
   assign  sa_err_o=1'b0;
112 
   assign  sa_rty_o=1'b0;
113 
 
114 
 
115 
 
116 
        genvar i;
117 
 
118 
        reg       [PORT_WIDTH-1                 :       0]       io_dir;
119 
        reg       [PORT_WIDTH-1                 :       0]       io_write;
120 
        reg   [PORT_WIDTH-1         :   0] read_reg;
121 
 
122 
 
123 
`ifdef SYNC_RESET_MODE
124 
    always @ (posedge clk )begin
125 
`else
126 
    always @ (posedge clk or posedge reset)begin
127 
`endif
128 
           if(reset) begin
129 
         io_dir         <= {PORT_WIDTH{1'b0}};
130 
                 io_write       <= {PORT_WIDTH{1'b0}};
131 
                end else begin
132 
            if(sa_stb_i && sa_we_i ) begin
133 
                      if( sa_addr_i     == DIR_REG[Aw-1       :   0]    ) io_dir  <=  sa_dat_i[PORT_WIDTH-1               :      0];
134 
              if( sa_addr_i     == WRITE_REG[Aw-1     :   0]    ) io_write        <=  sa_dat_i[PORT_WIDTH-1      :   0];
135 
            end //sa_stb_i && sa_we_i
136 
        end //reset
137 
        end//always
138 
 
139 
 
140 
 
141 
 
142 
    always @(posedge clk) begin
143 
        if(reset)begin
144 
            read_reg    <= {PORT_WIDTH{1'b0}};
145 
            sa_ack_o    <=  1'b0;
146 
        end else begin
147 
            if(sa_stb_i && ~sa_we_i)  read_reg  <=  port_io;
148 
            sa_ack_o    <=   (sa_stb_i & ~sa_ack_o);
149 
        end
150 
    end
151 
 
152 
 
153 
    generate
154 
        for(i=0;i<PORT_WIDTH; i=i+1'b1) begin: out_pin_assign0
155 
            assign port_io =    (io_dir[i]) ?   io_write[i] :   1'bZ;
156 
       end
157 
       if(PORT_WIDTH!=Dw) assign sa_dat_o = {{(Dw-PORT_WIDTH){1'b0}},read_reg};
158 
       else               assign sa_dat_o = read_reg;
159 
    endgenerate
160 
 
161 
endmodule
162 
 
163 
 
164 
 
165 
 
166 
module gpi #(
167 
    parameter Aw            =   2,
168 
    parameter SELw          =   4,
169 
    parameter TAGw          =   3,
170 
    parameter PORT_WIDTH    =   1,
171 
    parameter Dw           =    PORT_WIDTH
172 
 
173 
 
174 
)
175 
(
176 
    clk,
177 
    reset,
178 
 
179 
    //wishbone bus interface
180 
    sa_dat_i,
181 
    sa_sel_i,
182 
    sa_addr_i,
183 
    sa_tag_i,
184 
    sa_stb_i,
185 
    sa_cyc_i,
186 
    sa_we_i,
187 
    sa_dat_o,
188 
    sa_ack_o,
189 
    sa_err_o,
190 
    sa_rty_o,
191 
 
192 
    port_i
193 
 
194 
 
195 
 
196 
 
197 
 
198 
);
199 
 
200 
 
201 
    //registers num
202 
    localparam DIR_REG      =0;
203 
    localparam WRITE_REG    =1;
204 
    localparam READ_REG     =2;
205 
 
206 
 
207 
 
208 
    //wishbone bus interface
209 
    input       [Dw-1       :   0]      sa_dat_i;
210 
    input       [SELw-1     :   0]      sa_sel_i;
211 
    input       [Aw-1       :   0]      sa_addr_i;
212 
    input       [TAGw-1     :   0]      sa_tag_i;
213 
    input                               sa_stb_i;
214 
    input                               sa_cyc_i;
215 
    input                               sa_we_i;
216 
 
217 
    output      [Dw-1       :   0]      sa_dat_o;
218 
    output  reg                         sa_ack_o;
219 
    output                              sa_err_o;
220 
    output                              sa_rty_o;
221 
 
222 
    input   [PORT_WIDTH-1     :   0]    port_i;
223 
 
224 
    input clk,   reset;
225 
 
226 
 
227 
   assign  sa_err_o=1'b0;
228 
   assign  sa_rty_o=1'b0;
229 
 
230 
 
231 
 
232 
 
233 
    reg   [PORT_WIDTH-1         :   0] read_reg;
234 
 
235 
 
236 
 
237 
    always @(posedge clk) begin
238 
        if(reset)begin
239 
            read_reg    <= {PORT_WIDTH{1'b0}};
240 
            sa_ack_o    <=  1'b0;
241 
        end else begin
242 
            if(sa_stb_i && ~sa_we_i)  read_reg  <=  port_i;
243 
            sa_ack_o    <=   sa_stb_i && ~sa_ack_o;
244 
        end
245 
    end
246 
 
247 
 
248 
    generate
249 
       if(PORT_WIDTH!=Dw) assign sa_dat_o = {{(Dw-PORT_WIDTH){1'b0}},read_reg};
250 
       else               assign sa_dat_o = read_reg;
251 
    endgenerate
252 
 
253 
endmodule
254 
 
255 
 
256 
 
257 
 
258 
module gpo #(
259 
 
260 
    parameter Aw           =    2,
261 
    parameter SELw         =    4,
262 
    parameter TAGw         =    3,
263 
    parameter PORT_WIDTH    =   1,
264 
    parameter Dw           =    PORT_WIDTH
265 
 
266 
 
267 
)
268 
(
269 
    clk,
270 
    reset,
271 
 
272 
    //wishbone bus interface
273 
    sa_dat_i,
274 
    sa_sel_i,
275 
    sa_addr_i,
276 
    sa_tag_i,
277 
    sa_stb_i,
278 
    sa_cyc_i,
279 
    sa_we_i,
280 
    sa_dat_o,
281 
    sa_ack_o,
282 
    sa_err_o,
283 
    sa_rty_o,
284 
 
285 
    port_o
286 
 
287 
 
288 
);
289 
 
290 
 
291 
    //registers num
292 
    localparam WRITE_REG                        =1;
293 
 
294 
 
295 
 
296 
 
297 
    input                                 clk;
298 
    input                               reset;
299 
 
300 
   //wishbone bus interface
301 
    input       [Dw-1       :   0]      sa_dat_i;
302 
    input       [SELw-1     :   0]      sa_sel_i;
303 
    input       [Aw-1       :   0]      sa_addr_i;
304 
    input       [TAGw-1     :   0]      sa_tag_i;
305 
    input                               sa_stb_i;
306 
    input                               sa_cyc_i;
307 
    input                               sa_we_i;
308 
 
309 
    output      [Dw-1       :   0]      sa_dat_o;
310 
    output  reg                         sa_ack_o;
311 
    output                              sa_err_o;
312 
    output                              sa_rty_o;
313 
 
314 
    output   [PORT_WIDTH-1     :   0]    port_o;
315 
 
316 
 
317 
 
318 
   assign  sa_err_o=1'b0;
319 
   assign  sa_rty_o=1'b0;
320 
 
321 
 
322 
 
323 
 
324 
    reg   [PORT_WIDTH-1         :   0]  io_write;
325 
 
326 
 
327 
 
328 
`ifdef SYNC_RESET_MODE
329 
    always @ (posedge clk )begin
330 
`else
331 
    always @ (posedge clk or posedge reset)begin
332 
`endif
333 
       if(reset) begin
334 
            io_write   <= {PORT_WIDTH{1'b0}};
335 
            sa_ack_o   <=  1'b0;
336 
        end else begin
337 
            sa_ack_o   <=   (sa_stb_i & ~sa_ack_o);
338 
            if(sa_stb_i && sa_we_i ) begin
339 
               if( sa_addr_i     == WRITE_REG[Aw-1     :   0]    ) io_write   <=  sa_dat_i[PORT_WIDTH-1      :   0];
340 
            end //sa_stb_i && sa_we_i
341 
        end //reset
342 
    end//always
343 
 
344 
 
345 
    assign port_o =      io_write;
346 
 
347 
 
348 
 
349 
 
350 
 
351 
    generate
352 
       if(PORT_WIDTH!=Dw) assign sa_dat_o = {{(Dw-PORT_WIDTH){1'b0}},io_write};
353 
       else               assign sa_dat_o = io_write;
354 
    endgenerate
355 
 
356 
endmodule
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