URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [int_ctrl/] [int_ctrl.v] - Blame information for rev 48

Details | Compare with Previous | View Log


/**********************************************************************
**      File:  int_ctrl.v
**
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**      Description:
**      Intrrupt control module. It is used for CPUs with only one input
**      intrrupt pin to support multiple intrrupt signals
**
**
*******************************************************************/
 
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
 
module int_ctrl #(
 
        parameter INT_NUM               = 3, // number of intrupt  max 32,
        parameter Dw  =    32,   // wishbone bus data width
    parameter Aw  = 3,     // wishbone bus address width
    parameter SELw= 4    // wishbone bus sel width
)
(
    clk,
    reset,
 
        // wishbone interface
    sa_dat_i,
    sa_sel_i,
    sa_addr_i,
    sa_stb_i,
    sa_we_i,
    sa_dat_o,
    sa_ack_o,
    sa_err_o,
    sa_rty_o,
 
 
        //intruupt interface
    int_i,
    int_o
 
);
 
 
 
        input                       clk,reset;
 
    // wishbone interface
    input   [Dw-1       :   0]  sa_dat_i;
    input   [SELw-1     :   0]  sa_sel_i;
    input   [Aw-1       :   0]  sa_addr_i;
    input                       sa_stb_i;
    input                       sa_we_i;
    output  [Dw-1       :   0]  sa_dat_o;
    output  reg                 sa_ack_o;
    //intruupt interface
    input   [INT_NUM-1  :   0]  int_i;
    output                      int_o;
 
     output  sa_err_o, sa_rty_o;
   assign  sa_err_o=1'b0;
   assign  sa_rty_o=1'b0;
 
 
 
        localparam      [Aw-1           :       0]               MER_REG_ADDR    =       0;
        localparam      [Aw-1           :       0]               IER_REG_ADDR    =       1;
        localparam      [Aw-1           :       0]               IAR_REG_ADDR    =       2;
        localparam      [Aw-1           :       0]               IPR_REG_ADDR    =       3;
 
        localparam  LD_ZERO             = (INT_NUM >2 )? INT_NUM-2 : 0;
        //localparam  DATA_BUS_MASK     = (EXT_INT_EN <<2)       + (TIMER_EN << 1)+ NOC_EN ;
//internal register     
        reg [INT_NUM-1  :       0]       ipr,ier,iar;
        reg [INT_NUM-1  :       0]       ipr_next,ier_next,iar_next;
        reg [INT_NUM-1  :       0] read,read_next;
        reg [1:0]                                mer,mer_next;
 
        wire [INT_NUM-1:0]  sa_dat_i_masked, int_i_masked;
 
        assign sa_dat_i_masked = sa_dat_i;// &  DATA_BUS_MASK [INT_NUM-1:0];
        assign int_i_masked    = int_i   ;//&   DATA_BUS_MASK [INT_NUM-1:0];
        always@(*) begin
                mer_next                        = mer;
                ier_next                        = ier;
                iar_next                        = iar   & ~ int_i_masked;
                ipr_next                        = (ipr  | int_i_masked) & ier;
 
                read_next               =       read;
                if(sa_stb_i )
                        if(sa_we_i ) begin
                                case(sa_addr_i)
                                        MER_REG_ADDR:   mer_next        =       sa_dat_i[1:0];
                                        IER_REG_ADDR:   ier_next        =       sa_dat_i_masked[INT_NUM-1       :       0];
                                        IAR_REG_ADDR:   begin
                                                                                iar_next        =       iar | sa_dat_i_masked[INT_NUM-1         :       0];//set iar by writting 1
                                                                                ipr_next        = ipr & ~sa_dat_i_masked[INT_NUM-1              :       0];//reset ipr by writting 1
                                        end
                                        default:                ipr_next                        = ipr   | int_i_masked;
                                endcase
                        end//we
                        else begin
                                case(sa_addr_i)
                                        MER_REG_ADDR:   read_next               =       {{LD_ZERO{1'b0}},mer};
                                        IER_REG_ADDR:   read_next               =       ier;
                                        IAR_REG_ADDR:   read_next               =       iar;
                                        IPR_REG_ADDR:   read_next               =       ipr;
                                        default:                        read_next               =       read;
                                endcase
                        end
                end//stb
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
                if(reset)begin
                        mer             <= 2'b0;
                        ier             <= {INT_NUM{1'b0}};
                        iar             <= {INT_NUM{1'b0}};
                        ipr             <= {INT_NUM{1'b0}};
                        read            <=      {INT_NUM{1'b0}};
                        sa_ack_o        <=      1'b0;
                end else begin
                        mer             <= mer_next;
                        ier             <= ier_next;
                        iar             <= iar_next;
                        ipr             <= ipr_next;
                        read            <= read_next;
                        sa_ack_o        <= sa_stb_i && ~sa_ack_o;
                end
        end
 
                assign int_o    = ((mer == 2'b11)       && ((ier & ipr)>0)       ) ? 1'b1        :1'b0;
                assign sa_dat_o = {{(Dw-INT_NUM){1'b0}},read};
 
 
 
 
 
 
 
        endmodule
 

Line No.	Rev	Author	Line
1	48	alirezamon	`/**********************************************************************`
2			`** File: int_ctrl.v`
3			`**`
4			`**`
5			`** Copyright (C) 2014-2017 Alireza Monemi`
6			`**`
7			`** This file is part of ProNoC`
8			`**`
9			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
10			`** you can redistribute it and/or modify it under the terms of the GNU`
11			`** Lesser General Public License as published by the Free Software Foundation,`
12			`** either version 2 of the License, or (at your option) any later version.`
13			`**`
14			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
21			`**`
22			`**`
23			`** Description:`
24			`** Intrrupt control module. It is used for CPUs with only one input`
25			`** intrrupt pin to support multiple intrrupt signals`
26			`**`
27			`**`
28			`*******************************************************************/`
29
30
31
32			`// synthesis translate_off`
33			`timescale 1ns / 1ps
34			`// synthesis translate_on`
35
36
37			`module int_ctrl #(`
38
39			`parameter INT_NUM = 3, // number of intrupt max 32,`
40			`parameter Dw = 32, // wishbone bus data width`
41			`parameter Aw = 3, // wishbone bus address width`
42			`parameter SELw= 4 // wishbone bus sel width`
43			`)`
44			`(`
45			`clk,`
46			`reset,`
47
48			`// wishbone interface`
49			`sa_dat_i,`
50			`sa_sel_i,`
51			`sa_addr_i,`
52			`sa_stb_i,`
53			`sa_we_i,`
54			`sa_dat_o,`
55			`sa_ack_o,`
56			`sa_err_o,`
57			`sa_rty_o,`
58
59
60			`//intruupt interface`
61			`int_i,`
62			`int_o`
63
64			`);`
65
66
67
68			`input clk,reset;`
69
70			`// wishbone interface`
71			`input [Dw-1 : 0] sa_dat_i;`
72			`input [SELw-1 : 0] sa_sel_i;`
73			`input [Aw-1 : 0] sa_addr_i;`
74			`input sa_stb_i;`
75			`input sa_we_i;`
76			`output [Dw-1 : 0] sa_dat_o;`
77			`output reg sa_ack_o;`
78			`//intruupt interface`
79			`input [INT_NUM-1 : 0] int_i;`
80			`output int_o;`
81
82			`output sa_err_o, sa_rty_o;`
83			`assign sa_err_o=1'b0;`
84			`assign sa_rty_o=1'b0;`
85
86
87
88			`localparam [Aw-1 : 0] MER_REG_ADDR = 0;`
89			`localparam [Aw-1 : 0] IER_REG_ADDR = 1;`
90			`localparam [Aw-1 : 0] IAR_REG_ADDR = 2;`
91			`localparam [Aw-1 : 0] IPR_REG_ADDR = 3;`
92
93			`localparam LD_ZERO = (INT_NUM >2 )? INT_NUM-2 : 0;`
94			`//localparam DATA_BUS_MASK = (EXT_INT_EN <<2) + (TIMER_EN << 1)+ NOC_EN ;`
95			`//internal register`
96			`reg [INT_NUM-1 : 0] ipr,ier,iar;`
97			`reg [INT_NUM-1 : 0] ipr_next,ier_next,iar_next;`
98			`reg [INT_NUM-1 : 0] read,read_next;`
99			`reg [1:0] mer,mer_next;`
100
101			`wire [INT_NUM-1:0] sa_dat_i_masked, int_i_masked;`
102
103			`assign sa_dat_i_masked = sa_dat_i;// & DATA_BUS_MASK [INT_NUM-1:0];`
104			`assign int_i_masked = int_i ;//& DATA_BUS_MASK [INT_NUM-1:0];`
105			`always@(*) begin`
106			`mer_next = mer;`
107			`ier_next = ier;`
108			`iar_next = iar & ~ int_i_masked;`
109			`ipr_next = (ipr \| int_i_masked) & ier;`
110
111			`read_next = read;`
112			`if(sa_stb_i )`
113			`if(sa_we_i ) begin`
114			`case(sa_addr_i)`
115			`MER_REG_ADDR: mer_next = sa_dat_i[1:0];`
116			`IER_REG_ADDR: ier_next = sa_dat_i_masked[INT_NUM-1 : 0];`
117			`IAR_REG_ADDR: begin`
118			`iar_next = iar \| sa_dat_i_masked[INT_NUM-1 : 0];//set iar by writting 1`
119			`ipr_next = ipr & ~sa_dat_i_masked[INT_NUM-1 : 0];//reset ipr by writting 1`
120			`end`
121			`default: ipr_next = ipr \| int_i_masked;`
122			`endcase`
123			`end//we`
124			`else begin`
125			`case(sa_addr_i)`
126			`MER_REG_ADDR: read_next = {{LD_ZERO{1'b0}},mer};`
127			`IER_REG_ADDR: read_next = ier;`
128			`IAR_REG_ADDR: read_next = iar;`
129			`IPR_REG_ADDR: read_next = ipr;`
130			`default: read_next = read;`
131			`endcase`
132			`end`
133			`end//stb`
134
135			`ifdef SYNC_RESET_MODE
136			`always @ (posedge clk )begin`
137			`else
138			`always @ (posedge clk or posedge reset)begin`
139			`endif
140			`if(reset)begin`
141			`mer <= 2'b0;`
142			`ier <= {INT_NUM{1'b0}};`
143			`iar <= {INT_NUM{1'b0}};`
144			`ipr <= {INT_NUM{1'b0}};`
145			`read <= {INT_NUM{1'b0}};`
146			`sa_ack_o <= 1'b0;`
147			`end else begin`
148			`mer <= mer_next;`
149			`ier <= ier_next;`
150			`iar <= iar_next;`
151			`ipr <= ipr_next;`
152			`read <= read_next;`
153			`sa_ack_o <= sa_stb_i && ~sa_ack_o;`
154			`end`
155			`end`
156
157			`assign int_o = ((mer == 2'b11) && ((ier & ipr)>0) ) ? 1'b1 :1'b0;`
158			`assign sa_dat_o = {{(Dw-INT_NUM){1'b0}},read};`
159
160
161
162
163
164
165
166			`endmodule`
167

Browse

Tools

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [int_ctrl/] [int_ctrl.v] - Blame information for rev 48