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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [jtag_wb_test/] [model.tcl] - Blame information for rev 48

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#!/usr/bin/tclsh
 
###################################################################
## Author      : Alireza Monemi
## Email       : 
## Description : Compile all verilog files inside the design folder 
##             : using modelsim
###################################################################
set text "###################################################################"
set text "##                Start Compilation Script "
set text "###################################################################"
 
###################################################################
##---- Specify variables
set text "###################################################################"
set text "##---- Specify variables"
 
##-- Project path variables
 
 
set path0       [pwd]
set path        [pwd]/verilog
set jtag       $path0/../../jtag_wb/xilinx_jtag_wb.v
 
set comp_path                   $::env(PRONOC_WORK)/simulation
set work_path                   $comp_path/work
 
puts "work path is : $work_path"
 
 
##-- change directory
file mkdir $comp_path
 
cd $comp_path
exec rm -Rf *
proc r  {} {uplevel #0 source compile.tcl}
proc rr {} {global last_compile_time
            set last_compile_time 0
            r                            }
proc q  {} {quit -force                  }
 
proc sleep {N} {
    after [expr {int($N * 1000)}]
}
 
 
#Does this installation support Tk?
set tk_ok 1
if [catch {package require Tk}] {set tk_ok 0}
 
###################################################################
##---- 1. Creating working library
set text "###################################################################"
set text "##---- 1. Creating working library"
 
##-- Create work lib
vlib $work_path
 
##-- Mapping work lib
vmap work $work_path
 
 
 
###################################################################
##---- 3. Compile the Design
set text "###################################################################"
set text "##---- 3. Compile the Design"
 
 
# Compile out of date files
set time_now [clock seconds]
 
if {[file isfile start_time.txt] != 0} {
        set fp [open start_time.txt r]
        set line [gets $fp]
        close $fp
        regexp {\d+} $line last_compile_time
        puts "last compiled time is  $last_compile_time"
} else {
        set last_compile_time 0
}
 
 
 
 
 
foreach a [list $path]  {
      puts "$a "
      set lib_file_list [glob -directory $a *.v *.sv]
        foreach f $lib_file_list {
 
                if { $last_compile_time < [file mtime $f] } {
                        vlog  -work  $work_path  +acc=rn +incdir+$a+$path0  $f
 
                         set last_compile_time 0
                } else {
                         puts "$f is uptodate"
                }
        }
  }
 
vlog  -work  $work_path  +acc=rn +incdir+$a+$path0  $jtag
 
 
 
 
set last_compile_time $time_now
 
 
 
set text "###################################################################"
set text "##                       END OF COMPILATION"
set text "###################################################################"
 
 
#vsim -t ps -L altera_mf_ver work.testbench_router
vsim   -t ps  work.testbench
 
#do "$comp_path/wave.do"
 
run 100 ms
 
quit
 
 
#####################################################################################
 

Line No.	Rev	Author	Line
1	48	alirezamon	`#!/usr/bin/tclsh`
2
3			`###################################################################`
4			`## Author : Alireza Monemi`
5			`## Email :`
6			`## Description : Compile all verilog files inside the design folder`
7			`## : using modelsim`
8			`###################################################################`
9			`set text "###################################################################"`
10			`set text "## Start Compilation Script "`
11			`set text "###################################################################"`
12
13			`###################################################################`
14			`##---- Specify variables`
15			`set text "###################################################################"`
16			`set text "##---- Specify variables"`
17
18			`##-- Project path variables`
19
20
21			`set path0 [pwd]`
22			`set path [pwd]/verilog`
23			`set jtag $path0/../../jtag_wb/xilinx_jtag_wb.v`
24
25			`set comp_path $::env(PRONOC_WORK)/simulation`
26			`set work_path $comp_path/work`
27
28			`puts "work path is : $work_path"`
29
30
31			`##-- change directory`
32			`file mkdir $comp_path`
33
34			`cd $comp_path`
35			`exec rm -Rf *`
36			`proc r {} {uplevel #0 source compile.tcl}`
37			`proc rr {} {global last_compile_time`
38			`set last_compile_time 0`
39			`r }`
40			`proc q {} {quit -force }`
41
42			`proc sleep {N} {`
43			`after [expr {int($N * 1000)}]`
44			`}`
45
46
47			`#Does this installation support Tk?`
48			`set tk_ok 1`
49			`if [catch {package require Tk}] {set tk_ok 0}`
50
51			`###################################################################`
52			`##---- 1. Creating working library`
53			`set text "###################################################################"`
54			`set text "##---- 1. Creating working library"`
55
56			`##-- Create work lib`
57			`vlib $work_path`
58
59			`##-- Mapping work lib`
60			`vmap work $work_path`
61
62
63
64			`###################################################################`
65			`##---- 3. Compile the Design`
66			`set text "###################################################################"`
67			`set text "##---- 3. Compile the Design"`
68
69
70			`# Compile out of date files`
71			`set time_now [clock seconds]`
72
73			`if {[file isfile start_time.txt] != 0} {`
74			`set fp [open start_time.txt r]`
75			`set line [gets $fp]`
76			`close $fp`
77			`regexp {\d+} $line last_compile_time`
78			`puts "last compiled time is $last_compile_time"`
79			`} else {`
80			`set last_compile_time 0`
81			`}`
82
83
84
85
86
87			`foreach a [list $path] {`
88			`puts "$a "`
89			`set lib_file_list [glob -directory $a .v .sv]`
90			`foreach f $lib_file_list {`
91
92			`if { $last_compile_time < [file mtime $f] } {`
93			`vlog -work $work_path +acc=rn +incdir+$a+$path0 $f`
94
95			`set last_compile_time 0`
96			`} else {`
97			`puts "$f is uptodate"`
98			`}`
99			`}`
100			`}`
101
102			`vlog -work $work_path +acc=rn +incdir+$a+$path0 $jtag`
103
104
105
106
107			`set last_compile_time $time_now`
108
109
110
111			`set text "###################################################################"`
112			`set text "## END OF COMPILATION"`
113			`set text "###################################################################"`
114
115
116			`#vsim -t ps -L altera_mf_ver work.testbench_router`
117			`vsim -t ps work.testbench`
118
119			`#do "$comp_path/wave.do"`
120
121			`run 100 ms`
122
123			`quit`
124
125
126			`#####################################################################################`
127

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [jtag_wb_test/] [model.tcl] - Blame information for rev 48