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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [jtag_wb_test/] [verilog/] [BSCANE2_sim.v] - Blame information for rev 48

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Line No. Rev Author Line
1 48 alirezamon 
// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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module BSCANE2_sim # (
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parameter   JTAG_CHAIN  =4
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)(
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     output CAPTURE, // 1-bit output: CAPTURE output from TAP controller.
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     output DRCK, // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.
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     output RESET, // 1-bit output: Reset output for TAP controller.
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     output RUNTEST, // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
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     output SEL, // 1-bit output: USER instruction active output.
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     output SHIFT, // 1-bit output: SHIFT output from TAP controller.
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     output TCK, // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
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     output TDI, // 1-bit output: Test Data Input (TDI) output from TAP controller.
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     output TMS, // 1-bit output: Test Mode Select output. Fabric connection to TAP.
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     output UPDATE, // 1-bit output: UPDATE output from TAP controller
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     input  TDO // 1-bit input: Test Data Output (TDO) input for USER function.
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);
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    wire    [2:0]  ir_out;
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    wire    tdo;
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    wire    [2:0]  ir_in;
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    wire    tck;
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    wire    tdi;
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    wire    virtual_state_cdr;
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    wire    virtual_state_cir;
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    wire    virtual_state_e1dr;
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    wire    virtual_state_e2dr;
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    wire    virtual_state_pdr;
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    wire    virtual_state_sdr;
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    wire    virtual_state_udr;
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    wire    virtual_state_uir;
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    assign CAPTURE = virtual_state_cdr;
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    assign DRCK = tck & (SEL & (CAPTURE | SHIFT)); // I am not using it. So I am not sure if the definition is correct
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    assign RESET=1'b0;
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    assign RUNTEST = 1'b0; // not used
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    assign SEL = virtual_state_cdr | virtual_state_sdr | virtual_state_udr;
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    assign SHIFT=virtual_state_sdr;
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    assign TCK = tck;
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    assign TDI = tdi;
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    assign TMS=1'b0;//not used by me
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    assign UPDATE = virtual_state_udr;
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    assign tdo = TDO;
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    assign ir_out =ir_in;
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    vjtag_sim #(
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        .VJTAG_INDEX(0)
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    )
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    the_vjtag_sim
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    (
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        .ir_out(ir_out),
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        .tdo(tdo),
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        .ir_in(ir_in),
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        .tck(tck),
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        .tdi(tdi),
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        .virtual_state_cdr(virtual_state_cdr),
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        .virtual_state_cir(virtual_state_cir),
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        .virtual_state_e1dr(virtual_state_e1dr),
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        .virtual_state_e2dr(virtual_state_e2dr),
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        .virtual_state_pdr(virtual_state_pdr),
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        .virtual_state_sdr(virtual_state_sdr),
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        .virtual_state_udr(virtual_state_udr),
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        .virtual_state_uir(virtual_state_uir)
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    );
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endmodule
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module vjtag_sim
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(
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        ir_out,
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        tdo,
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        ir_in,
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        tck,
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        tdi,
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        virtual_state_cdr,
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        virtual_state_cir,
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        virtual_state_e1dr,
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        virtual_state_e2dr,
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        virtual_state_pdr,
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        virtual_state_sdr,
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        virtual_state_udr,
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        virtual_state_uir);
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        input   [2:0]  ir_out;
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        input     tdo;
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        output  [2:0]  ir_in;
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        output    tck;
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        output    tdi;
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        output    virtual_state_cdr;
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        output    virtual_state_cir;
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        output    virtual_state_e1dr;
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        output    virtual_state_e2dr;
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        output    virtual_state_pdr;
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        output    virtual_state_sdr;
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        output    virtual_state_udr;
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        output    virtual_state_uir;
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        wire  sub_wire0;
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        wire  sub_wire1;
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        wire [2:0] sub_wire2;
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        wire  sub_wire3;
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        wire  sub_wire4;
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        wire  sub_wire5;
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        wire  sub_wire6;
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        wire  sub_wire7;
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        wire  sub_wire8;
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        wire  sub_wire9;
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        wire  sub_wire10;
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        wire  virtual_state_cir = sub_wire0;
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        wire  virtual_state_pdr = sub_wire1;
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        wire [2:0] ir_in = sub_wire2[2:0];
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        wire  tdi = sub_wire3;
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        wire  virtual_state_udr = sub_wire4;
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        wire  tck = sub_wire5;
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        wire  virtual_state_e1dr = sub_wire6;
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        wire  virtual_state_uir = sub_wire7;
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        wire  virtual_state_cdr = sub_wire8;
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        wire  virtual_state_e2dr = sub_wire9;
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        wire  virtual_state_sdr = sub_wire10;
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        parameter  VJTAG_INDEX=0;
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        /*
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    parameter SIM_ACTION = "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))",
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    parameter SIM_N_SCAN=8,
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    parameter SIM_SIM_LENGTH=198
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        */
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    `define INCLUDE_SIM_INPUT
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    `include "jtag_sim_input.v"
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        sld_virtual_jtag        sld_virtual_jtag_component (
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                                .ir_out (ir_out),
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                                .tdo (tdo),
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                                .virtual_state_cir (sub_wire0),
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                                .virtual_state_pdr (sub_wire1),
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                                .ir_in (sub_wire2),
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                                .tdi (sub_wire3),
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                                .virtual_state_udr (sub_wire4),
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                                .tck (sub_wire5),
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                                .virtual_state_e1dr (sub_wire6),
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                                .virtual_state_uir (sub_wire7),
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                                .virtual_state_cdr (sub_wire8),
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                                .virtual_state_e2dr (sub_wire9),
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                                .virtual_state_sdr (sub_wire10)
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                                // synopsys translate_off
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                                ,
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                                .jtag_state_cdr (),
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                                .jtag_state_cir (),
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                                .jtag_state_e1dr (),
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                                .jtag_state_e1ir (),
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                                .jtag_state_e2dr (),
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                                .jtag_state_e2ir (),
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                                .jtag_state_pdr (),
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                                .jtag_state_pir (),
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                                .jtag_state_rti (),
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                                .jtag_state_sdr (),
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                                .jtag_state_sdrs (),
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                                .jtag_state_sir (),
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                                .jtag_state_sirs (),
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                                .jtag_state_tlr (),
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                                .jtag_state_udr (),
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                                .jtag_state_uir (),
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                                .tms ()
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                                // synopsys translate_on
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                                );
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        defparam
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                sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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                sld_virtual_jtag_component.sld_instance_index = VJTAG_INDEX,
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                sld_virtual_jtag_component.sld_ir_width = 3,
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                sld_virtual_jtag_component.sld_sim_action = SIM_ACTION,
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                sld_virtual_jtag_component.sld_sim_n_scan = SIM_N_SCAN,
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                sld_virtual_jtag_component.sld_sim_total_length = SIM_LENGTH;
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endmodule
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