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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [jtag_wb_test/] [verilog/] [altera.v] - Blame information for rev 48

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Line No. Rev Author Line
1 48 alirezamon 
//synthesis translate_off
2 
//synopsys  translate_off
3 
 
4 
`timescale 1 ps / 1 ps
5 
 
6 
 
7 
 
8 
 
9 
`define IR_REGISTER_WIDTH 10;
10 
 
11 
 
12 
// VIRTUAL JTAG MODULE CONSTANTS
13 
 
14 
// VIRTUAL JTAG MODULE CONSTANTS
15 
 
16 
// the default bit length for time and value
17 
`define DEFAULT_BIT_LENGTH 32
18 
 
19 
// the bit length for type
20 
`define TYPE_BIT_LENGTH 4
21 
 
22 
// the bit length for delay time
23 
`define TIME_BIT_LENGTH 64
24 
 
25 
// the number of selection bits + width of hub instructions(3)
26 
`define NUM_SELECTION_BITS 4
27 
 
28 
// the states for the parser state machine
29 
`define STARTSTATE    3'b000
30 
`define LENGTHSTATE   3'b001
31 
`define VALUESTATE    3'b011
32 
`define TYPESTATE     3'b111
33 
`define TIMESTATE     3'b101
34 
 
35 
`define V_DR_SCAN_TYPE 4'b0010
36 
`define V_IR_SCAN_TYPE 4'b0001
37 
 
38 
// specify time scale
39 
`define CLK_PERIOD 100
40 
 
41 
`define DELAY_RESOLUTION 100
42 
 
43 
 
44 
// the states for the tap controller state machine
45 
`define TLR_ST  5'b00000
46 
`define RTI_ST  5'b00001
47 
`define DRS_ST  5'b00011
48 
`define CDR_ST  5'b00111
49 
`define SDR_ST  5'b01111
50 
`define E1DR_ST 5'b01011
51 
`define PDR_ST  5'b01101
52 
`define E2DR_ST 5'b01000
53 
`define UDR_ST  5'b01001
54 
`define IRS_ST  5'b01100
55 
`define CIR_ST  5'b01010
56 
`define SIR_ST  5'b00101
57 
`define E1IR_ST 5'b00100
58 
`define PIR_ST  5'b00010
59 
`define E2IR_ST 5'b00110
60 
`define UIR_ST  5'b01110
61 
`define INIT_ST 5'b10000
62 
 
63 
// usr1 instruction for tap controller
64 
`define JTAG_USR1_INSTR 10'b0000001110
65 
 
66 
// MODULE DECLARATION
67 
module sld_virtual_jtag (tdo,ir_out,tck,tdi,ir_in,virtual_state_cdr,virtual_state_sdr,
68 
                        virtual_state_e1dr,virtual_state_pdr,virtual_state_e2dr,
69 
                        virtual_state_udr,virtual_state_cir,virtual_state_uir,
70 
                        jtag_state_tlr,jtag_state_rti,jtag_state_sdrs,jtag_state_cdr,
71 
                        jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr,
72 
                        jtag_state_udr,jtag_state_sirs,jtag_state_cir,jtag_state_sir,
73 
                        jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir,
74 
                        tms);
75 
 
76 
 
77 
    // GLOBAL PARAMETER DECLARATION
78 
    parameter lpm_type = "SLD_VIRTUAL_JTAG"; // required by coding standard
79 
    parameter lpm_hint = "SLD_VIRTUAL_JTAG"; // required by coding standard
80 
    parameter sld_auto_instance_index = "NO"; //Yes if auto index is desired and no otherwise
81 
    parameter sld_instance_index = 0; // index to be used if SLD_AUTO_INDEX is no
82 
    parameter sld_ir_width = 1; //the width of the IR register
83 
    parameter sld_sim_n_scan = 0; // the number of scans in the simulatiom parameters
84 
    parameter sld_sim_total_length = 0; // The total bit width of all scan values
85 
    parameter sld_sim_action = ""; // the actions to be simulated
86 
 
87 
    // local parameter declaration
88 
    defparam  user_input.sld_node_ir_width = sld_ir_width;
89 
    defparam  user_input.sld_node_n_scan = sld_sim_n_scan;
90 
    defparam  user_input.sld_node_total_length = sld_sim_total_length;
91 
    defparam  user_input.sld_node_sim_action = sld_sim_action;
92 
    defparam  jtag.ir_register_width = 10 ;  // compilation fails if defined constant is used
93 
    defparam  hub.sld_node_ir_width = sld_ir_width;
94 
 
95 
 
96 
    // INPUT PORTS DECLARATION
97 
    input   tdo;  // tdo signal into megafunction
98 
    input [sld_ir_width - 1 : 0] ir_out;// parallel ir data into megafunction
99 
 
100 
    // OUTPUT PORTS DECLARATION
101 
    output   tck;  // tck signal from megafunction
102 
    output   tdi;  // tdi signal from megafunction
103 
    output   virtual_state_cdr; // cdr state signal of megafunction
104 
    output   virtual_state_sdr; // sdr state signal of megafunction
105 
    output   virtual_state_e1dr;//  e1dr state signal of megafunction
106 
    output   virtual_state_pdr; // pdr state signal of megafunction
107 
    output   virtual_state_e2dr;// e2dr state signal of megafunction
108 
    output   virtual_state_udr; // udr state signal of megafunction
109 
    output   virtual_state_cir; // cir state signal of megafunction
110 
    output   virtual_state_uir; // uir state signal of megafunction
111 
    output   jtag_state_tlr;    // Test, Logic, Reset state
112 
    output   jtag_state_rti;    // Run, Test, Idle state
113 
    output   jtag_state_sdrs;   // Select DR scan state
114 
    output   jtag_state_cdr;    // capture DR state
115 
    output   jtag_state_sdr;    // Shift DR state
116 
    output   jtag_state_e1dr;   // exit 1 dr state
117 
    output   jtag_state_pdr;    // pause dr state
118 
    output   jtag_state_e2dr;   // exit 2 dr state
119 
    output   jtag_state_udr;    // update dr state
120 
    output   jtag_state_sirs;   // Select IR scan state
121 
    output   jtag_state_cir;    // capture IR state
122 
    output   jtag_state_sir;    // shift IR state
123 
    output   jtag_state_e1ir;   // exit 1 IR state
124 
    output   jtag_state_pir;    // pause IR state
125 
    output   jtag_state_e2ir;   // exit 2 IR state
126 
    output   jtag_state_uir;    // update IR state
127 
    output   tms;               // tms signal
128 
    output [sld_ir_width - 1 : 0] ir_in; // paraller ir data from megafunction
129 
 
130 
    // connecting wires
131 
    wire   tck_i;
132 
    wire   tms_i;
133 
    wire   tdi_i;
134 
    wire   jtag_usr1_i;
135 
    wire   tdo_i;
136 
    wire   jtag_tdo_i;
137 
    wire   jtag_tck_i;
138 
    wire   jtag_tms_i;
139 
    wire   jtag_tdi_i;
140 
    wire   jtag_state_tlr_i;
141 
    wire   jtag_state_rti_i;
142 
    wire   jtag_state_drs_i;
143 
    wire   jtag_state_cdr_i;
144 
    wire   jtag_state_sdr_i;
145 
    wire   jtag_state_e1dr_i;
146 
    wire   jtag_state_pdr_i;
147 
    wire   jtag_state_e2dr_i;
148 
    wire   jtag_state_udr_i;
149 
    wire   jtag_state_irs_i;
150 
    wire   jtag_state_cir_i;
151 
    wire   jtag_state_sir_i;
152 
    wire   jtag_state_e1ir_i;
153 
    wire   jtag_state_pir_i;
154 
    wire   jtag_state_e2ir_i;
155 
    wire   jtag_state_uir_i;
156 
 
157 
 
158 
    // COMPONENT INSTANTIATIONS
159 
    // generates input to jtag controller
160 
    signal_gen user_input (tck_i,tms_i,tdi_i,jtag_usr1_i,tdo_i);
161 
 
162 
    // the JTAG TAP controller
163 
    jtag_tap_controller jtag (tck_i,tms_i,tdi_i,jtag_tdo_i,
164 
                                tdo_i,jtag_tck_i,jtag_tms_i,jtag_tdi_i,
165 
                                jtag_state_tlr_i,jtag_state_rti_i,
166 
                                jtag_state_drs_i,jtag_state_cdr_i,
167 
                                jtag_state_sdr_i,jtag_state_e1dr_i,
168 
                                jtag_state_pdr_i,jtag_state_e2dr_i,
169 
                                jtag_state_udr_i,jtag_state_irs_i,
170 
                                jtag_state_cir_i,jtag_state_sir_i,
171 
                                jtag_state_e1ir_i,jtag_state_pir_i,
172 
                                jtag_state_e2ir_i,jtag_state_uir_i,
173 
                                jtag_usr1_i);
174 
 
175 
    // the HUB
176 
    dummy_hub hub (jtag_tck_i,jtag_tdi_i,jtag_tms_i,jtag_usr1_i,
177 
                    jtag_state_tlr_i,jtag_state_rti_i,jtag_state_drs_i,
178 
                    jtag_state_cdr_i,jtag_state_sdr_i,jtag_state_e1dr_i,
179 
                    jtag_state_pdr_i,jtag_state_e2dr_i,jtag_state_udr_i,
180 
                    jtag_state_irs_i,jtag_state_cir_i,jtag_state_sir_i,
181 
                    jtag_state_e1ir_i,jtag_state_pir_i,jtag_state_e2ir_i,
182 
                    jtag_state_uir_i,tdo,ir_out,jtag_tdo_i,tck,tdi,tms,
183 
                    jtag_state_tlr,jtag_state_rti,jtag_state_sdrs,jtag_state_cdr,
184 
                    jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr,
185 
                    jtag_state_udr,jtag_state_sirs,jtag_state_cir,jtag_state_sir,
186 
                    jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir,
187 
                    virtual_state_cdr,virtual_state_sdr,virtual_state_e1dr,
188 
                    virtual_state_pdr,virtual_state_e2dr,virtual_state_udr,
189 
                    virtual_state_cir,virtual_state_uir,ir_in);
190 
 
191 
endmodule
192 
 
193 
 
194 
 
195 
 
196 
 
197 
module dummy_hub (jtag_tck,jtag_tdi,jtag_tms,jtag_usr1,jtag_state_tlr,jtag_state_rti,
198 
                    jtag_state_drs,jtag_state_cdr,jtag_state_sdr,jtag_state_e1dr,
199 
                    jtag_state_pdr,jtag_state_e2dr,jtag_state_udr,jtag_state_irs,
200 
                    jtag_state_cir,jtag_state_sir,jtag_state_e1ir,jtag_state_pir,
201 
                    jtag_state_e2ir,jtag_state_uir,dummy_tdo,virtual_ir_out,
202 
                    jtag_tdo,dummy_tck,dummy_tdi,dummy_tms,dummy_state_tlr,
203 
                    dummy_state_rti,dummy_state_drs,dummy_state_cdr,dummy_state_sdr,
204 
                    dummy_state_e1dr,dummy_state_pdr,dummy_state_e2dr,dummy_state_udr,
205 
                    dummy_state_irs,dummy_state_cir,dummy_state_sir,dummy_state_e1ir,
206 
                    dummy_state_pir,dummy_state_e2ir,dummy_state_uir,virtual_state_cdr,
207 
                    virtual_state_sdr,virtual_state_e1dr,virtual_state_pdr,virtual_state_e2dr,
208 
                    virtual_state_udr,virtual_state_cir,virtual_state_uir,virtual_ir_in);
209 
 
210 
 
211 
    // GLOBAL PARAMETER DECLARATION
212 
    parameter sld_node_ir_width = 16;
213 
 
214 
    // INPUT PORTS
215 
 
216 
    input   jtag_tck;       // tck signal from tap controller
217 
    input   jtag_tdi;       // tdi signal from tap controller
218 
    input   jtag_tms;       // tms signal from tap controller
219 
    input   jtag_usr1;      // usr1 signal from tap controller
220 
    input   jtag_state_tlr; // tlr state signal from tap controller
221 
    input   jtag_state_rti; // rti state signal from tap controller
222 
    input   jtag_state_drs; // drs state signal from tap controller
223 
    input   jtag_state_cdr; // cdr state signal from tap controller
224 
    input   jtag_state_sdr; // sdr state signal from tap controller
225 
    input   jtag_state_e1dr;// e1dr state signal from tap controller
226 
    input   jtag_state_pdr; // pdr state signal from tap controller
227 
    input   jtag_state_e2dr;// esdr state signal from tap controller
228 
    input   jtag_state_udr; // udr state signal from tap controller
229 
    input   jtag_state_irs; // irs state signal from tap controller
230 
    input   jtag_state_cir; // cir state signals from tap controller
231 
    input   jtag_state_sir; // sir state signal from tap controller
232 
    input   jtag_state_e1ir;// e1ir state signal from tap controller
233 
    input   jtag_state_pir; // pir state signals from tap controller
234 
    input   jtag_state_e2ir;// e2ir state signal from tap controller
235 
    input   jtag_state_uir; // uir state signal from tap controller
236 
    input   dummy_tdo;      // tdo signal from world
237 
    input [sld_node_ir_width - 1 : 0] virtual_ir_out; // captures parallel input from
238 
 
239 
    // OUTPUT PORTS
240 
    output   jtag_tdo;             // tdo signal to tap controller
241 
    output   dummy_tck;           // tck signal to world
242 
    output   dummy_tdi;           // tdi signal to world
243 
    output   dummy_tms;           // tms signal to world
244 
    output   dummy_state_tlr;     // tlr state signal to world
245 
    output   dummy_state_rti;     // rti state signal to world
246 
    output   dummy_state_drs;     // drs state signal to world
247 
    output   dummy_state_cdr;     // cdr state signal to world
248 
    output   dummy_state_sdr;     // sdr state signal to world
249 
    output   dummy_state_e1dr;    // e1dr state signal to the world
250 
    output   dummy_state_pdr;     // pdr state signal to world
251 
    output   dummy_state_e2dr;    // e2dr state signal to world
252 
    output   dummy_state_udr;     // udr state signal to world
253 
    output   dummy_state_irs;     // irs state signal to world
254 
    output   dummy_state_cir;    // cir state signal to world
255 
    output   dummy_state_sir;    // sir state signal to world
256 
    output   dummy_state_e1ir;   // e1ir state signal to world
257 
    output   dummy_state_pir;    // pir state signal to world
258 
    output   dummy_state_e2ir;   // e2ir state signal to world
259 
    output   dummy_state_uir;    // uir state signal to world
260 
    output   virtual_state_cdr;  // virtual cdr state signal
261 
    output   virtual_state_sdr;  // virtual sdr state signal
262 
    output   virtual_state_e1dr; // virtual e1dr state signal
263 
    output   virtual_state_pdr;  // virtula pdr state signal
264 
    output   virtual_state_e2dr; // virtual e2dr state signal
265 
    output   virtual_state_udr;  // virtual udr state signal
266 
    output   virtual_state_cir;  // virtual cir state signal
267 
    output   virtual_state_uir;  // virtual uir state signal
268 
    output [sld_node_ir_width - 1 : 0] virtual_ir_in;      // parallel output to user design
269 
 
270 
 
271 
`define SLD_NODE_IR_WIDTH_I sld_node_ir_width + `NUM_SELECTION_BITS // internal ir width
272 
 
273 
    // INTERNAL REGISTERS
274 
    reg   capture_ir;    // signals force_ir_capture instruction
275 
    reg   jtag_tdo_reg;  // register for jtag_tdo
276 
    reg   dummy_tdi_reg; // register for dummy_tdi
277 
    reg   dummy_tck_reg; // register for dummy_tck.
278 
    reg  [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl; // ir shift register
279 
    wire [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl_tmp; // ir shift register
280 
    reg  [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl_hold; //hold register for ir shift register
281 
 
282 
    // OUTPUT REGISTERS
283 
    reg [sld_node_ir_width - 1 : 0]     virtual_ir_in;
284 
 
285 
    // INITIAL STATEMENTS
286 
    always @ (posedge jtag_tck or posedge jtag_state_tlr)
287 
        begin : simulation_logic
288 
            if (jtag_state_tlr) // asynchronous active high reset
289 
                begin : active_hi_async_reset
290 
                    ir_srl <= 'b0;
291 
                    jtag_tdo_reg <= 1'b0;
292 
                    dummy_tdi_reg <= 1'b0;
293 
                end  // active_hi_async_reset
294 
            else
295 
                begin : rising_edge_jtag_tck
296 
                    // logic for shifting in data and piping data through
297 
                    // logic for muxing inputs to outputs and otherwise
298 
                    if (jtag_usr1 && jtag_state_sdr)
299 
                        begin : shift_in_out_usr1
300 
                            jtag_tdo_reg <= ir_srl_tmp[0];
301 
                            ir_srl <= ir_srl_tmp >> 1;
302 
                            ir_srl[`SLD_NODE_IR_WIDTH_I - 1] <= jtag_tdi;
303 
                        end // shift_in_out_usr1
304 
                    else
305 
                        begin
306 
                            if (capture_ir && jtag_state_cdr)
307 
                                begin : capture_virtual_ir_out
308 
                                    ir_srl[`SLD_NODE_IR_WIDTH_I - 2 : `NUM_SELECTION_BITS - 1] <= virtual_ir_out;
309 
                                end // capture_virtual_ir_out
310 
                            else
311 
                                begin
312 
                                    if (capture_ir && jtag_state_sdr)
313 
                                        begin : shift_in_out_usr0
314 
                                            jtag_tdo_reg <= ir_srl_tmp[0];
315 
                                            ir_srl <= ir_srl_tmp >> 1;
316 
                                            ir_srl[`SLD_NODE_IR_WIDTH_I - 1] <= jtag_tdi;
317 
                                        end // shift_in_out_usr0
318 
                                    else
319 
                                        begin
320 
                                            if (jtag_state_sdr)
321 
                                                begin : pipe_through
322 
                                                    dummy_tdi_reg <= jtag_tdi;
323 
                                                    jtag_tdo_reg <= dummy_tdo;
324 
                                                end // pipe_through
325 
                                        end
326 
                                end
327 
                        end
328 
                end // rising_edge_jtag_tck
329 
        end // simulation_logic
330 
 
331 
    // always block for writing to capture_ir
332 
    // stops nlint from complaining.
333 
    always @ (posedge jtag_tck or posedge jtag_state_tlr)
334 
        begin : capture_ir_logic
335 
            if (jtag_state_tlr) // asynchronous active high reset
336 
                begin : active_hi_async_reset
337 
                    capture_ir <= 1'b0;
338 
                end  // active_hi_async_reset
339 
            else
340 
                begin : rising_edge_jtag_tck
341 
                    // should check for 011 instruction
342 
                    // but we know that it is the only instruction ever sent to the
343 
                    // hub. So all we have to do is check the selection bit and udr
344 
                    // and usr1 state
345 
                    // logic for capture_ir signal
346 
                    if (jtag_state_udr && (ir_srl[`SLD_NODE_IR_WIDTH_I - 1] == 1'b0))
347 
                        begin
348 
                            capture_ir <= jtag_usr1;
349 
                        end
350 
                    else
351 
                        begin
352 
                            if (jtag_state_e1dr)
353 
                                begin
354 
                                    capture_ir <= 1'b0;
355 
                                end
356 
                        end
357 
                end  // rising_edge_jtag_tck
358 
        end // capture_ir_logic
359 
 
360 
    // outputs -  rising edge of clock
361 
    always @ (posedge jtag_tck or posedge jtag_state_tlr)
362 
        begin : parallel_ir_out
363 
            if (jtag_state_tlr)
364 
                begin : active_hi_async_reset
365 
                    virtual_ir_in <= 'b0;
366 
                end
367 
            else
368 
                begin : rising_edge_jtag_tck
369 
                    virtual_ir_in <= ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 2 : `NUM_SELECTION_BITS - 1];
370 
                end
371 
        end
372 
 
373 
    // outputs -  falling edge of clock, separated for clarity
374 
    always @ (negedge jtag_tck or posedge jtag_state_tlr)
375 
        begin : shift_reg_hold
376 
            if (jtag_state_tlr)
377 
                begin : active_hi_async_reset
378 
                    ir_srl_hold <= 'b0;
379 
                end
380 
            else
381 
                begin
382 
                    if (ir_srl[`SLD_NODE_IR_WIDTH_I - 1] && jtag_state_e1dr)
383 
                        begin
384 
                            ir_srl_hold <= ir_srl;
385 
                        end
386 
                end
387 
        end // shift_reg_hold
388 
 
389 
    // generate tck in sync with tdi
390 
    always @ (posedge jtag_tck or negedge jtag_tck)
391 
        begin : gen_tck
392 
            dummy_tck_reg <= jtag_tck;
393 
        end // gen_tck
394 
    // temporary signals
395 
    assign ir_srl_tmp = ir_srl;
396 
 
397 
    // Pipe through signals
398 
    assign dummy_state_tlr    = jtag_state_tlr;
399 
    assign dummy_state_rti    = jtag_state_rti;
400 
    assign dummy_state_drs    = jtag_state_drs;
401 
    assign dummy_state_cdr    = jtag_state_cdr;
402 
    assign dummy_state_sdr    = jtag_state_sdr;
403 
    assign dummy_state_e1dr   = jtag_state_e1dr;
404 
    assign dummy_state_pdr    = jtag_state_pdr;
405 
    assign dummy_state_e2dr   = jtag_state_e2dr;
406 
    assign dummy_state_udr    = jtag_state_udr;
407 
    assign dummy_state_irs    = jtag_state_irs;
408 
    assign dummy_state_cir    = jtag_state_cir;
409 
    assign dummy_state_sir    = jtag_state_sir;
410 
    assign dummy_state_e1ir   = jtag_state_e1ir;
411 
    assign dummy_state_pir    = jtag_state_pir;
412 
    assign dummy_state_e2ir   = jtag_state_e2ir;
413 
    assign dummy_state_uir    = jtag_state_uir;
414 
    assign dummy_tms          = jtag_tms;
415 
 
416 
 
417 
    // Virtual signals
418 
    assign virtual_state_uir  = jtag_usr1 && jtag_state_udr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
419 
    assign virtual_state_cir  = jtag_usr1 && jtag_state_cdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
420 
    assign virtual_state_udr  = (! jtag_usr1) && jtag_state_udr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
421 
    assign virtual_state_e2dr = (! jtag_usr1) && jtag_state_e2dr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
422 
    assign virtual_state_pdr  = (! jtag_usr1) && jtag_state_pdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
423 
    assign virtual_state_e1dr = (! jtag_usr1) && jtag_state_e1dr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
424 
    assign virtual_state_sdr  = (! jtag_usr1) && jtag_state_sdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
425 
    assign virtual_state_cdr  = (! jtag_usr1) && jtag_state_cdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1];
426 
 
427 
    // registered output
428 
    assign jtag_tdo = jtag_tdo_reg;
429 
    assign dummy_tdi = dummy_tdi_reg;
430 
    assign dummy_tck = dummy_tck_reg;
431 
 
432 
endmodule
433 
 
434 
 
435 
 
436 
 
437 
 
438 
 
439 
 
440 
module jtag_tap_controller (tck,tms,tdi,jtag_tdo,tdo,jtag_tck,jtag_tms,jtag_tdi,
441 
                            jtag_state_tlr,jtag_state_rti,jtag_state_drs,jtag_state_cdr,
442 
                            jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr,
443 
                            jtag_state_udr,jtag_state_irs,jtag_state_cir,jtag_state_sir,
444 
                            jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir,
445 
                            jtag_usr1);
446 
 
447 
 
448 
    // GLOBAL PARAMETER DECLARATION
449 
    parameter ir_register_width = 16;
450 
 
451 
    // INPUT PORTS
452 
    input     tck;  // tck signal from signal_gen
453 
    input     tms;  // tms signal from signal_gen
454 
    input     tdi;  // tdi signal from signal_gen
455 
    input     jtag_tdo; // tdo signal from hub
456 
 
457 
    // OUTPUT PORTS
458 
    output    tdo;  // tdo signal to signal_gen
459 
    output    jtag_tck;  // tck signal from jtag
460 
    output    jtag_tms;  // tms signal from jtag
461 
    output    jtag_tdi;  // tdi signal from jtag
462 
    output    jtag_state_tlr;   // tlr state
463 
    output    jtag_state_rti;   // rti state
464 
    output    jtag_state_drs;   // select dr scan state
465 
    output    jtag_state_cdr;   // capture dr state
466 
    output    jtag_state_sdr;   // shift dr state
467 
    output    jtag_state_e1dr;  // exit1 dr state
468 
    output    jtag_state_pdr;   // pause dr state
469 
    output    jtag_state_e2dr;  // exit2 dr state
470 
    output    jtag_state_udr;   // update dr state
471 
    output    jtag_state_irs;   // select ir scan state
472 
    output    jtag_state_cir;   // capture ir state
473 
    output    jtag_state_sir;   // shift ir state
474 
    output    jtag_state_e1ir;  // exit1 ir state
475 
    output    jtag_state_pir;   // pause ir state
476 
    output    jtag_state_e2ir;  // exit2 ir state
477 
    output    jtag_state_uir;   // update ir state
478 
    output    jtag_usr1;        // jtag has usr1 instruction
479 
 
480 
    // INTERNAL REGISTERS
481 
 
482 
    reg       tdo_reg;
483 
    // temporary tdo output register
484 
    reg       tdo_rom_reg;
485 
    // temporary register used to generate 0101... during SIR_ST
486 
    reg       jtag_usr1_reg;
487 
    // temporary jtag_usr1 register
488 
    reg       jtag_reset_i;
489 
    // internal reset
490 
    reg [ 4 : 0 ] cState;
491 
    // register for current state
492 
    reg [ 4 : 0 ] nState;
493 
    // register for the next state signal
494 
    reg [ ir_register_width - 1 : 0] ir_srl;
495 
    // the ir shift register
496 
    reg [ ir_register_width - 1 : 0] ir_srl_hold;
497 
    // the ir shift register
498 
 
499 
    // INTERNAL WIRES
500 
    wire [ 4 : 0 ] cState_tmp;
501 
    wire [ ir_register_width - 1 : 0] ir_srl_tmp;
502 
 
503 
 
504 
    // OUTPUT REGISTERS
505 
    reg   jtag_state_tlr;   // tlr state
506 
    reg   jtag_state_rti;   // rti state
507 
    reg   jtag_state_drs;   // select dr scan state
508 
    reg   jtag_state_cdr;   // capture dr state
509 
    reg   jtag_state_sdr;   // shift dr state
510 
    reg   jtag_state_e1dr;  // exit1 dr state
511 
    reg   jtag_state_pdr;   // pause dr state
512 
    reg   jtag_state_e2dr;  // exit2 dr state
513 
    reg   jtag_state_udr;   // update dr state
514 
    reg   jtag_state_irs;   // select ir scan state
515 
    reg   jtag_state_cir;   // capture ir state
516 
    reg   jtag_state_sir;   // shift ir state
517 
    reg   jtag_state_e1ir;  // exit1 ir state
518 
    reg   jtag_state_pir;   // pause ir state
519 
    reg   jtag_state_e2ir;  // exit2 ir state
520 
    reg   jtag_state_uir;   // update ir state
521 
 
522 
 
523 
    // INITIAL STATEMENTS
524 
    initial
525 
        begin
526 
            // initialize state registers
527 
            cState = `INIT_ST;
528 
            nState = `TLR_ST;
529 
        end
530 
 
531 
    // State Register block
532 
    always @ (posedge tck or posedge jtag_reset_i)
533 
        begin : stateReg
534 
            if (jtag_reset_i)
535 
                begin
536 
                    cState <= `TLR_ST;
537 
                    ir_srl <= 'b0;
538 
                    tdo_reg <= 1'b0;
539 
                    tdo_rom_reg <= 1'b0;
540 
                    jtag_usr1_reg <= 1'b0;
541 
                end
542 
            else
543 
                begin
544 
                    // in capture ir, set-up tdo_rom_reg
545 
                    // to generate 010101...
546 
                    if(cState_tmp == `CIR_ST)
547 
                        begin
548 
                            tdo_rom_reg <= 1'b0;
549 
                        end
550 
                    else
551 
                        begin
552 
                            // write to shift register else pipe
553 
                            if (cState_tmp == `SIR_ST)
554 
                                begin
555 
                                    tdo_rom_reg <= ~tdo_rom_reg;
556 
                                    tdo_reg <= tdo_rom_reg;
557 
                                    ir_srl <= ir_srl_tmp >> 1;
558 
                                    ir_srl[ir_register_width - 1] <= tdi;
559 
                                end
560 
                            else
561 
                                begin
562 
                                    tdo_reg <= jtag_tdo;
563 
                                end
564 
                        end
565 
                    // check if in usr1 state
566 
                    if (cState_tmp == `UIR_ST)
567 
                        begin
568 
                            if (ir_srl_hold == `JTAG_USR1_INSTR)
569 
                                begin
570 
                                    jtag_usr1_reg <= 1'b1;
571 
                                end
572 
                            else
573 
                                begin
574 
                                    jtag_usr1_reg <= 1'b0;
575 
                                end
576 
                        end
577 
                    cState <= nState;
578 
                end
579 
        end // stateReg
580 
 
581 
    // hold register
582 
    always @ (negedge tck or posedge jtag_reset_i)
583 
        begin : holdReg
584 
            if (jtag_reset_i)
585 
                begin
586 
                    ir_srl_hold <= 'b0;
587 
                end
588 
            else
589 
                begin
590 
                    if (cState == `E1IR_ST)
591 
                        begin
592 
                            ir_srl_hold <= ir_srl;
593 
                        end
594 
                end
595 
        end // holdReg
596 
 
597 
    // next state logic
598 
    always @(cState or tms)
599 
        begin : stateTrans
600 
            nState = cState;
601 
            case (cState)
602 
                `TLR_ST :
603 
                    begin
604 
                        if (tms == 1'b0)
605 
                            begin
606 
                                nState = `RTI_ST;
607 
                                jtag_reset_i = 1'b0;
608 
                            end
609 
                        else
610 
                            begin
611 
                                jtag_reset_i = 1'b1;
612 
                            end
613 
                    end
614 
                `RTI_ST :
615 
                    begin
616 
                        if (tms)
617 
                            begin
618 
                                nState = `DRS_ST;
619 
                            end
620 
                    end
621 
                `DRS_ST :
622 
                    begin
623 
                        if (tms)
624 
                            begin
625 
                                nState = `IRS_ST;
626 
                            end
627 
                        else
628 
                            begin
629 
                                nState = `CDR_ST;
630 
                            end
631 
                    end
632 
                `CDR_ST :
633 
                    begin
634 
                        if (tms)
635 
                            begin
636 
                                nState = `E1DR_ST;
637 
                            end
638 
                        else
639 
                            begin
640 
                                nState = `SDR_ST;
641 
                            end
642 
                    end
643 
                `SDR_ST :
644 
                    begin
645 
                        if (tms)
646 
                            begin
647 
                                nState = `E1DR_ST;
648 
                            end
649 
                    end
650 
                `E1DR_ST :
651 
                    begin
652 
                        if (tms)
653 
                            begin
654 
                                nState = `UDR_ST;
655 
                            end
656 
                        else
657 
                            begin
658 
                                nState = `PDR_ST;
659 
                            end
660 
                    end
661 
                `PDR_ST :
662 
                    begin
663 
                        if (tms)
664 
                            begin
665 
                                nState = `E2DR_ST;
666 
                            end
667 
                    end
668 
                `E2DR_ST :
669 
                    begin
670 
                        if (tms)
671 
                            begin
672 
                                nState = `UDR_ST;
673 
                            end
674 
                        else
675 
                            begin
676 
                                nState = `SDR_ST;
677 
                            end
678 
                    end
679 
                `UDR_ST :
680 
                    begin
681 
                        if (tms)
682 
                            begin
683 
                                nState = `DRS_ST;
684 
                            end
685 
                        else
686 
                            begin
687 
                                nState = `RTI_ST;
688 
                            end
689 
                    end
690 
                `IRS_ST :
691 
                    begin
692 
                        if (tms)
693 
                            begin
694 
                                nState = `TLR_ST;
695 
                            end
696 
                        else
697 
                            begin
698 
                                nState = `CIR_ST;
699 
                            end
700 
                    end
701 
                `CIR_ST :
702 
                    begin
703 
                        if (tms)
704 
                            begin
705 
                                nState = `E1IR_ST;
706 
                            end
707 
                        else
708 
                            begin
709 
                                nState = `SIR_ST;
710 
                            end
711 
                    end
712 
                `SIR_ST :
713 
                    begin
714 
                        if (tms)
715 
                            begin
716 
                                nState = `E1IR_ST;
717 
                            end
718 
                    end
719 
                `E1IR_ST :
720 
                    begin
721 
                        if (tms)
722 
                            begin
723 
                                nState = `UIR_ST;
724 
                            end
725 
                        else
726 
                            begin
727 
                                nState = `PIR_ST;
728 
                            end
729 
                    end
730 
                `PIR_ST :
731 
                    begin
732 
                        if (tms)
733 
                            begin
734 
                                nState = `E2IR_ST;
735 
                            end
736 
                    end
737 
                `E2IR_ST :
738 
                    begin
739 
                        if (tms)
740 
                            begin
741 
                                nState = `UIR_ST;
742 
                            end
743 
                        else
744 
                            begin
745 
                                nState = `SIR_ST;
746 
                            end
747 
                    end
748 
                `UIR_ST :
749 
                    begin
750 
                        if (tms)
751 
                            begin
752 
                                nState = `DRS_ST;
753 
                            end
754 
                        else
755 
                            begin
756 
                                nState = `RTI_ST;
757 
                            end
758 
                    end
759 
                `INIT_ST :
760 
                    begin
761 
                        nState = `TLR_ST;
762 
                    end
763 
                default :
764 
                    begin
765 
                        $display("Tap Controller State machine error");
766 
                        $display ("Time: %0t  Instance: %m", $time);
767 
                        nState = `TLR_ST;
768 
                    end
769 
            endcase
770 
        end // stateTrans
771 
 
772 
    // Output logic
773 
    always @ (cState)
774 
        begin : output_logic
775 
            jtag_state_tlr <= 1'b0;
776 
            jtag_state_rti <= 1'b0;
777 
            jtag_state_drs <= 1'b0;
778 
            jtag_state_cdr <= 1'b0;
779 
            jtag_state_sdr <= 1'b0;
780 
            jtag_state_e1dr <= 1'b0;
781 
            jtag_state_pdr <= 1'b0;
782 
            jtag_state_e2dr <= 1'b0;
783 
            jtag_state_udr <= 1'b0;
784 
            jtag_state_irs <= 1'b0;
785 
            jtag_state_cir <= 1'b0;
786 
            jtag_state_sir <= 1'b0;
787 
            jtag_state_e1ir <= 1'b0;
788 
            jtag_state_pir <= 1'b0;
789 
            jtag_state_e2ir <= 1'b0;
790 
            jtag_state_uir <= 1'b0;
791 
            case (cState)
792 
                `TLR_ST :
793 
                    begin
794 
                        jtag_state_tlr <= 1'b1;
795 
                    end
796 
                `RTI_ST :
797 
                    begin
798 
                        jtag_state_rti <= 1'b1;
799 
                    end
800 
                `DRS_ST :
801 
                    begin
802 
                        jtag_state_drs <= 1'b1;
803 
                    end
804 
                `CDR_ST :
805 
                    begin
806 
                        jtag_state_cdr <= 1'b1;
807 
                    end
808 
                `SDR_ST :
809 
                    begin
810 
                        jtag_state_sdr <= 1'b1;
811 
                    end
812 
                `E1DR_ST :
813 
                    begin
814 
                        jtag_state_e1dr <= 1'b1;
815 
                    end
816 
                `PDR_ST :
817 
                    begin
818 
                        jtag_state_pdr <= 1'b1;
819 
                    end
820 
                `E2DR_ST :
821 
                    begin
822 
                        jtag_state_e2dr <= 1'b1;
823 
                    end
824 
                `UDR_ST :
825 
                    begin
826 
                        jtag_state_udr <= 1'b1;
827 
                    end
828 
                `IRS_ST :
829 
                    begin
830 
                        jtag_state_irs <= 1'b1;
831 
                    end
832 
                `CIR_ST :
833 
                    begin
834 
                        jtag_state_cir <= 1'b1;
835 
                    end
836 
                `SIR_ST :
837 
                    begin
838 
                        jtag_state_sir <= 1'b1;
839 
                    end
840 
                `E1IR_ST :
841 
                    begin
842 
                        jtag_state_e1ir <= 1'b1;
843 
                    end
844 
                `PIR_ST :
845 
                    begin
846 
                        jtag_state_pir <= 1'b1;
847 
                    end
848 
                `E2IR_ST :
849 
                    begin
850 
                        jtag_state_e2ir <= 1'b1;
851 
                    end
852 
                `UIR_ST :
853 
                    begin
854 
                        jtag_state_uir <= 1'b1;
855 
                    end
856 
                default :
857 
                    begin
858 
                        $display("Tap Controller State machine output error");
859 
                        $display ("Time: %0t  Instance: %m", $time);
860 
                    end
861 
            endcase
862 
        end // output_logic
863 
    // temporary values
864 
    assign ir_srl_tmp = ir_srl;
865 
    assign cState_tmp = cState;
866 
 
867 
    // Pipe through signals
868 
    assign tdo = tdo_reg;
869 
    assign jtag_tck = tck;
870 
    assign jtag_tdi = tdi;
871 
    assign jtag_tms = tms;
872 
    assign jtag_usr1 = jtag_usr1_reg;
873 
 
874 
endmodule
875 
 
876 
 
877 
 
878 
 
879 
// MODULE DECLARATION
880 
module signal_gen (tck,tms,tdi,jtag_usr1,tdo);
881 
 
882 
 
883 
    // GLOBAL PARAMETER DECLARATION
884 
    parameter sld_node_ir_width = 1;
885 
    parameter sld_node_n_scan = 0;
886 
    parameter sld_node_total_length = 0;
887 
    parameter sld_node_sim_action = "()";
888 
 
889 
    // INPUT PORTS
890 
    input     jtag_usr1;
891 
    input     tdo;
892 
 
893 
    // OUTPUT PORTS
894 
    output    tck;
895 
    output    tms;
896 
    output    tdi;
897 
 
898 
    // CONSTANT DECLARATIONS
899 
`define DECODED_SCANS_LENGTH (sld_node_total_length + ((sld_node_n_scan * `DEFAULT_BIT_LENGTH) * 2) + (sld_node_n_scan * `TYPE_BIT_LENGTH) - 1)
900 
`define DEFAULT_SCAN_LENGTH (sld_node_n_scan * `DEFAULT_BIT_LENGTH)
901 
`define TYPE_SCAN_LENGTH (sld_node_n_scan * `TYPE_BIT_LENGTH) - 1
902 
 
903 
    // INTEGER DECLARATION
904 
    integer   char_idx;       // character_loop index
905 
    integer   value_idx;      // decoding value index
906 
    integer   value_idx_old;  // previous decoding value index
907 
    integer   value_idx_cur;  // reading/outputing value index
908 
    integer   length_idx;     // decoding length index
909 
    integer   length_idx_old; // previous decoding length index
910 
    integer   length_idx_cur; // reading/outputing length index
911 
    integer   last_length_idx;// decoding previous length index
912 
    integer   type_idx;       // decoding type index
913 
    integer   type_idx_old;   // previous decoding type index
914 
    integer   type_idx_cur;   // reading/outputing type index
915 
    integer   time_idx;       // decoding time index
916 
    integer   time_idx_old;   // previous decoding time index
917 
    integer   time_idx_cur;   // reading/outputing time index
918 
 
919 
    // REGISTERS
920 
    reg [ `DEFAULT_SCAN_LENGTH - 1 : 0 ]    scan_length;
921 
    // register for the 32-bit length values
922 
    reg [ sld_node_total_length  - 1 : 0 ]  scan_values;
923 
    // register for values
924 
    reg [ `TYPE_SCAN_LENGTH : 0 ]           scan_type;
925 
    // register for 4-bit type
926 
    reg [ `DEFAULT_SCAN_LENGTH - 1 : 0 ]    scan_time;
927 
    // register to hold time values
928 
    reg [15 : 0]                            two_character;
929 
    // two ascii characters. Used in decoding
930 
    reg [2 : 0]                             c_state;
931 
    // the current state register
932 
    reg [3 : 0]                             hex_value;
933 
    // temporary value to hold hex value of ascii character
934 
    reg [31 : 0]                             last_length;
935 
    // register to hold the previous length value read
936 
    reg                                     tms_reg;
937 
    // register to hold tms value before its clocked
938 
    reg                                     tdi_reg;
939 
    // register to hold tdi vale before its clocked
940 
 
941 
    // OUTPUT REGISTERS
942 
    reg    tms;
943 
    reg    tck;
944 
    reg    tdi;
945 
 
946 
    // input registers
947 
 
948 
    // LOCAL TIME DECLARATION
949 
 
950 
    // FUNCTION DECLARATION
951 
 
952 
    // hexToBits - takes in a hexadecimal character and
953 
    // returns the 4-bit value of the character.
954 
    // Returns 0 if character is not a hexadeciaml character
955 
    function [3 : 0]  hexToBits;
956 
        input [7 : 0] character;
957 
        begin
958 
            case ( character )
959 
                "0" : hexToBits = 4'b0000;
960 
                "1" : hexToBits = 4'b0001;
961 
                "2" : hexToBits = 4'b0010;
962 
                "3" : hexToBits = 4'b0011;
963 
                "4" : hexToBits = 4'b0100;
964 
                "5" : hexToBits = 4'b0101;
965 
                "6" : hexToBits = 4'b0110;
966 
                "7" : hexToBits = 4'b0111;
967 
                "8" : hexToBits = 4'b1000;
968 
                "9" : hexToBits = 4'b1001;
969 
                "A" : hexToBits = 4'b1010;
970 
                "a" : hexToBits = 4'b1010;
971 
                "B" : hexToBits = 4'b1011;
972 
                "b" : hexToBits = 4'b1011;
973 
                "C" : hexToBits = 4'b1100;
974 
                "c" : hexToBits = 4'b1100;
975 
                "D" : hexToBits = 4'b1101;
976 
                "d" : hexToBits = 4'b1101;
977 
                "E" : hexToBits = 4'b1110;
978 
                "e" : hexToBits = 4'b1110;
979 
                "F" : hexToBits = 4'b1111;
980 
                "f" : hexToBits = 4'b1111;
981 
                default :
982 
                    begin
983 
                        hexToBits = 4'b0000;
984 
                        $display("%s is not a hexadecimal value",character);
985 
                    end
986 
            endcase
987 
        end
988 
    endfunction
989 
 
990 
    // TASK DECLARATIONS
991 
 
992 
    // clocks tck
993 
    task clock_tck;
994 
        input in_tms;
995 
        input in_tdi;
996 
        begin : clock_tck_tsk
997 
            #(`CLK_PERIOD/2) tck <= ~tck;
998 
            tms <= in_tms;
999 
            tdi <= in_tdi;
1000 
            #(`CLK_PERIOD/2) tck <= ~tck;
1001 
        end // clock_tck_tsk
1002 
    endtask // clock_tck
1003 
 
1004 
    // move tap controller from dr/ir shift state to ir/dr update state
1005 
    task goto_update_state;
1006 
        begin : goto_update_state_tsk
1007 
            // get into e1(i/d)r state
1008 
            tms_reg = 1'b1;
1009 
            clock_tck(tms_reg,tdi_reg);
1010 
            // get into u(i/d)r state
1011 
            tms_reg = 1'b1;
1012 
            clock_tck(tms_reg,tdi_reg);
1013 
        end // goto_update_state_tsk
1014 
    endtask // goto_update_state
1015 
 
1016 
    // resets the jtag TAP controller by holding tms high
1017 
    // for 6 tck cycles
1018 
    task reset_jtag;
1019 
        integer idx;
1020 
        begin
1021 
            for (idx = 0; idx < 6; idx= idx + 1)
1022 
                begin
1023 
                    tms_reg = 1'b1;
1024 
                    clock_tck(tms_reg,tdi_reg);
1025 
                end
1026 
            // get into rti state
1027 
            tms_reg = 1'b0;
1028 
            clock_tck(tms_reg,tdi_reg);
1029 
            jtag_ir_usr1;
1030 
        end
1031 
    endtask // reset_jtag
1032 
 
1033 
    // sends a jtag_usr0 intsruction
1034 
    task jtag_ir_usr0;
1035 
        integer i;
1036 
        begin : jtag_ir_usr0_tsk
1037 
            // get into drs state
1038 
            tms_reg = 1'b1;
1039 
            clock_tck(tms_reg,tdi_reg);
1040 
            // get into irs state
1041 
            tms_reg = 1'b1;
1042 
            clock_tck(tms_reg,tdi_reg);
1043 
            // get into cir state
1044 
            tms_reg = 1'b0;
1045 
            clock_tck(tms_reg,tdi_reg);
1046 
            // get into sir state
1047 
            tms_reg = 1'b0;
1048 
            clock_tck(tms_reg,tdi_reg);
1049 
            // shift in data i.e usr0 instruction
1050 
            // usr1 = 0x0E = 0b00 0000 1100
1051 
            for ( i = 0; i < 2; i = i + 1)
1052 
                begin :ir_usr0_loop1
1053 
                    tdi_reg = 1'b0;
1054 
                    tms_reg = 1'b0;
1055 
                    clock_tck(tms_reg,tdi_reg);
1056 
                end // ir_usr0_loop1
1057 
            for ( i = 0; i < 2; i = i + 1)
1058 
                begin :ir_usr0_loop2
1059 
                    tdi_reg = 1'b1;
1060 
                    tms_reg = 1'b0;
1061 
                    clock_tck(tms_reg,tdi_reg);
1062 
                end // ir_usr0_loop2
1063 
            // done with 1100
1064 
            for ( i = 0; i < 6; i = i + 1)
1065 
                begin :ir_usr0_loop3
1066 
                    tdi_reg = 1'b0;
1067 
                    tms_reg = 1'b0;
1068 
                    clock_tck(tms_reg,tdi_reg);
1069 
                end // ir_usr0_loop3
1070 
            // done  with 00 0000
1071 
            // get into e1ir state
1072 
            tms_reg = 1'b1;
1073 
            clock_tck(tms_reg,tdi_reg);
1074 
            // get into uir state
1075 
            tms_reg = 1'b1;
1076 
            clock_tck(tms_reg,tdi_reg);
1077 
        end // jtag_ir_usr0_tsk
1078 
    endtask // jtag_ir_usr0
1079 
 
1080 
    // sends a jtag_usr1 intsruction
1081 
    task jtag_ir_usr1;
1082 
        integer i;
1083 
        begin : jtag_ir_usr1_tsk
1084 
            // get into drs state
1085 
            tms_reg = 1'b1;
1086 
            clock_tck(tms_reg,tdi_reg);
1087 
            // get into irs state
1088 
            tms_reg = 1'b1;
1089 
            clock_tck(tms_reg,tdi_reg);
1090 
            // get into cir state
1091 
            tms_reg = 1'b0;
1092 
            clock_tck(tms_reg,tdi_reg);
1093 
            // get into sir state
1094 
            tms_reg = 1'b0;
1095 
            clock_tck(tms_reg,tdi_reg);
1096 
            // shift in data i.e usr1 instruction
1097 
            // usr1 = 0x0E = 0b00 0000 1110
1098 
            tdi_reg = 1'b0;
1099 
            tms_reg = 1'b0;
1100 
            clock_tck(tms_reg,tdi_reg);
1101 
            for ( i = 0; i < 3; i = i + 1)
1102 
                begin :ir_usr1_loop1
1103 
                    tdi_reg = 1'b1;
1104 
                    tms_reg = 1'b0;
1105 
                    clock_tck(tms_reg,tdi_reg);
1106 
                end // ir_usr1_loop1
1107 
            // done with 1110
1108 
            for ( i = 0; i < 5; i = i + 1)
1109 
                begin :ir_usr1_loop2
1110 
                    tdi_reg = 1'b0;
1111 
                    tms_reg = 1'b0;
1112 
                    clock_tck(tms_reg,tdi_reg);
1113 
                end // ir_sur1_loop2
1114 
            tdi_reg = 1'b0;
1115 
            tms_reg = 1'b1;
1116 
            clock_tck(tms_reg,tdi_reg);
1117 
            // done  with 00 0000
1118 
            // now in e1ir state
1119 
            // get into uir state
1120 
            tms_reg = 1'b1;
1121 
            clock_tck(tms_reg,tdi_reg);
1122 
        end // jtag_ir_usr1_tsk
1123 
    endtask // jtag_ir_usr1
1124 
 
1125 
    // sends a force_ir_capture instruction to the node
1126 
    task send_force_ir_capture;
1127 
        integer i;
1128 
        begin : send_force_ir_capture_tsk
1129 
            goto_dr_shift_state;
1130 
            // start shifting in the instruction
1131 
            tdi_reg = 1'b1;
1132 
            tms_reg = 1'b0;
1133 
            clock_tck(tms_reg,tdi_reg);
1134 
            tdi_reg = 1'b1;
1135 
            tms_reg = 1'b0;
1136 
            clock_tck(tms_reg,tdi_reg);
1137 
            tdi_reg = 1'b0;
1138 
            tms_reg = 1'b0;
1139 
            clock_tck(tms_reg,tdi_reg);
1140 
            // done with 011
1141 
            tdi_reg = 1'b0;
1142 
            tms_reg = 1'b0;
1143 
            clock_tck(tms_reg,tdi_reg);
1144 
            // done with select bit
1145 
            // fill up with zeros up to ir_width
1146 
            for ( i = 0; i < sld_node_ir_width - 4; i = i + 1 )
1147 
                begin
1148 
                    tdi_reg = 1'b0;
1149 
                    tms_reg = 1'b0;
1150 
                    clock_tck(tms_reg,tdi_reg);
1151 
                end
1152 
            goto_update_state;
1153 
        end // send_force_ir_capture_tsk
1154 
    endtask // send_forse_ir_capture
1155 
 
1156 
    // puts the JTAG tap controller in DR shift state
1157 
    task goto_dr_shift_state;
1158 
        begin : goto_dr_shift_state_tsk
1159 
            // get into drs state
1160 
            tms_reg = 1'b1;
1161 
            clock_tck(tms_reg,tdi_reg);
1162 
            // get into cdr state
1163 
            tms_reg = 1'b0;
1164 
            clock_tck(tms_reg,tdi_reg);
1165 
            // get into sdr state
1166 
            tms_reg = 1'b0;
1167 
            clock_tck(tms_reg,tdi_reg);
1168 
        end // goto_dr_shift_state_tsk
1169 
    endtask // goto_dr_shift_state
1170 
 
1171 
    // performs a virtual_ir_scan
1172 
    task v_ir_scan;
1173 
        input [`DEFAULT_BIT_LENGTH - 1 : 0] length;
1174 
        integer i;
1175 
        begin : v_ir_scan_tsk
1176 
            // if we are not in usr1 then go to usr1 state
1177 
            if (jtag_usr1 == 1'b0)
1178 
                begin
1179 
                    jtag_ir_usr1;
1180 
                end
1181 
            // send force_ir_capture
1182 
            send_force_ir_capture;
1183 
            // shift in the ir value
1184 
            goto_dr_shift_state;
1185 
            value_idx_cur = value_idx_cur - length;
1186 
            for ( i = 0; i < length; i = i + 1)
1187 
                begin
1188 
                    tms_reg = 1'b0;
1189 
                    tdi_reg = scan_values[value_idx_cur + i];
1190 
                    clock_tck(tms_reg,tdi_reg);
1191 
                end
1192 
            // pad with zeros if necessary
1193 
            for(i = length; i < sld_node_ir_width; i = i + 1)
1194 
                begin : zero_padding
1195 
                    tdi_reg = 1'b0;
1196 
                    tms_reg = 1'b0;
1197 
                    clock_tck(tms_reg,tdi_reg);
1198 
                end //zero_padding
1199 
            tdi_reg = 1'b1;
1200 
            goto_update_state;
1201 
        end // v_ir_scan_tsk
1202 
    endtask // v_ir_scan
1203 
 
1204 
    // performs a virtual dr scan
1205 
    task v_dr_scan;
1206 
        input [`DEFAULT_BIT_LENGTH - 1 : 0] length;
1207 
        integer                             i;
1208 
        begin : v_dr_scan_tsk
1209 
            // if we are in usr1 then go to usr0 state
1210 
            if (jtag_usr1 == 1'b1)
1211 
                begin
1212 
                    jtag_ir_usr0;
1213 
                end
1214 
            // shift in the dr value
1215 
            goto_dr_shift_state;
1216 
            value_idx_cur = value_idx_cur - length;
1217 
            for ( i = 0; i < length - 1; i = i + 1)
1218 
                begin
1219 
                    tms_reg = 1'b0;
1220 
                    tdi_reg = scan_values[value_idx_cur + i];
1221 
                    clock_tck(tms_reg,tdi_reg);
1222 
                end
1223 
            // last bit is clocked together with state transition
1224 
            tdi_reg = scan_values[value_idx_cur + i];
1225 
            goto_update_state;
1226 
        end // v_dr_scan_tsk
1227 
    endtask // v_dr_scan
1228 
 
1229 
    initial
1230 
        begin : sim_model
1231 
            // initialize output registers
1232 
            tck = 1'b1;
1233 
            tms = 1'b0;
1234 
            tdi = 1'b0;
1235 
            // initialize variables
1236 
            tms_reg = 1'b0;
1237 
            tdi_reg = 1'b0;
1238 
            two_character = 'b0;
1239 
            last_length_idx = 0;
1240 
            value_idx = 0;
1241 
            value_idx_old = 0;
1242 
            length_idx = 0;
1243 
            length_idx_old = 0;
1244 
            type_idx = 0;
1245 
            type_idx_old = 0;
1246 
            time_idx = 0;
1247 
            time_idx_old = 0;
1248 
            scan_length = 'b0;
1249 
            scan_values = 'b0;
1250 
            scan_type = 'b0;
1251 
            scan_time = 'b0;
1252 
            last_length = 'b0;
1253 
            hex_value = 'b0;
1254 
            c_state = `STARTSTATE;
1255 
            // initialize current indices
1256 
            value_idx_cur = sld_node_total_length;
1257 
            type_idx_cur = `TYPE_SCAN_LENGTH;
1258 
            time_idx_cur = `DEFAULT_SCAN_LENGTH;
1259 
            length_idx_cur = `DEFAULT_SCAN_LENGTH;
1260 
            for(char_idx = 0;two_character != "((";char_idx = char_idx + 8)
1261 
                begin : character_loop
1262 
 
1263 
                // convert two characters to equivalent 16-bit value
1264 
                    two_character[0]  = sld_node_sim_action[char_idx];
1265 
                    two_character[1]  = sld_node_sim_action[char_idx+1];
1266 
                    two_character[2]  = sld_node_sim_action[char_idx+2];
1267 
                    two_character[3]  = sld_node_sim_action[char_idx+3];
1268 
                    two_character[4]  = sld_node_sim_action[char_idx+4];
1269 
                    two_character[5]  = sld_node_sim_action[char_idx+5];
1270 
                    two_character[6]  = sld_node_sim_action[char_idx+6];
1271 
                    two_character[7]  = sld_node_sim_action[char_idx+7];
1272 
                    two_character[8]  = sld_node_sim_action[char_idx+8];
1273 
                    two_character[9]  = sld_node_sim_action[char_idx+9];
1274 
                    two_character[10] = sld_node_sim_action[char_idx+10];
1275 
                    two_character[11] = sld_node_sim_action[char_idx+11];
1276 
                    two_character[12] = sld_node_sim_action[char_idx+12];
1277 
                    two_character[13] = sld_node_sim_action[char_idx+13];
1278 
                    two_character[14] = sld_node_sim_action[char_idx+14];
1279 
                    two_character[15] = sld_node_sim_action[char_idx+15];
1280 
                    // use state machine to decode
1281 
                    case (c_state)
1282 
                        `STARTSTATE :
1283 
                            begin
1284 
                                if (two_character[15 : 8] != ")")
1285 
                                    begin
1286 
                                        c_state = `LENGTHSTATE;
1287 
                                    end
1288 
                            end
1289 
                        `LENGTHSTATE :
1290 
                            begin
1291 
                                if (two_character[7 : 0] == ",")
1292 
                                    begin
1293 
                                        length_idx = length_idx_old + 32;
1294 
                                        length_idx_old = length_idx;
1295 
                                        c_state = `VALUESTATE;
1296 
                                    end
1297 
                                else
1298 
                                    begin
1299 
                                        hex_value = hexToBits(two_character[7:0]);
1300 
                                        scan_length [ length_idx] = hex_value[0];
1301 
                                        scan_length [ length_idx + 1] = hex_value[1];
1302 
                                        scan_length [ length_idx + 2] = hex_value[2];
1303 
                                        scan_length [ length_idx + 3] = hex_value[3];
1304 
                                        last_length [ last_length_idx] = hex_value[0];
1305 
                                        last_length [ last_length_idx + 1] = hex_value[1];
1306 
                                        last_length [ last_length_idx + 2] = hex_value[2];
1307 
                                        last_length [ last_length_idx + 3] = hex_value[3];
1308 
                                        length_idx = length_idx + 4;
1309 
                                        last_length_idx = last_length_idx + 4;
1310 
                                    end
1311 
                            end
1312 
                        `VALUESTATE :
1313 
                            begin
1314 
                                if (two_character[7 : 0] == ",")
1315 
                                    begin
1316 
                                        value_idx = value_idx_old + last_length;
1317 
                                        value_idx_old = value_idx;
1318 
                                        last_length = 'b0; // reset the last length value
1319 
                                        last_length_idx = 0; // reset index for length
1320 
                                        c_state = `TYPESTATE;
1321 
                                    end
1322 
                                else
1323 
                                    begin
1324 
                                        hex_value = hexToBits(two_character[7:0]);
1325 
                                        scan_values [ value_idx] = hex_value[0];
1326 
                                        scan_values [ value_idx + 1] = hex_value[1];
1327 
                                        scan_values [ value_idx + 2] = hex_value[2];
1328 
                                        scan_values [ value_idx + 3] = hex_value[3];
1329 
                                        value_idx = value_idx + 4;
1330 
                                    end
1331 
                            end
1332 
                        `TYPESTATE :
1333 
                            begin
1334 
                                if (two_character[7 : 0] == ",")
1335 
                                    begin
1336 
                                        type_idx = type_idx + 4;
1337 
                                        c_state = `TIMESTATE;
1338 
                                    end
1339 
                                else
1340 
                                    begin
1341 
                                        hex_value = hexToBits(two_character[7:0]);
1342 
                                        scan_type [ type_idx] = hex_value[0];
1343 
                                        scan_type [ type_idx + 1] = hex_value[1];
1344 
                                        scan_type [ type_idx + 2] = hex_value[2];
1345 
                                        scan_type [ type_idx + 3] = hex_value[3];
1346 
                                    end
1347 
                            end
1348 
                        `TIMESTATE :
1349 
                            begin
1350 
                                if (two_character[7 : 0] == "(")
1351 
                                    begin
1352 
                                        time_idx = time_idx_old + 32;
1353 
                                        time_idx_old = time_idx;
1354 
                                        c_state = `STARTSTATE;
1355 
                                    end
1356 
                                else
1357 
                                    begin
1358 
                                        hex_value = hexToBits(two_character[7:0]);
1359 
                                        scan_time [ time_idx] = hex_value[0];
1360 
                                        scan_time [ time_idx + 1] = hex_value[1];
1361 
                                        scan_time [ time_idx + 2] = hex_value[2];
1362 
                                        scan_time [ time_idx + 3] = hex_value[3];
1363 
                                        time_idx = time_idx + 4;
1364 
                                    end
1365 
                            end
1366 
                        default :
1367 
                            c_state = `STARTSTATE;
1368 
                    endcase
1369 
                end // block: character_loop
1370 
           end // block: sim_model
1371 
 
1372 
      integer write_scan_idx;
1373 
                integer tempLength_idx;
1374 
                reg [`TYPE_BIT_LENGTH - 1 : 0] tempType;
1375 
                reg [`DEFAULT_BIT_LENGTH - 1 : 0 ] tempLength;
1376 
                reg [`DEFAULT_BIT_LENGTH - 1 : 0 ] tempTime;
1377 
                reg [`TIME_BIT_LENGTH - 1 : 0 ] delayTime;
1378 
 
1379 
        initial begin : execute
1380 
 
1381 
           # (`CLK_PERIOD/2);
1382 
 
1383 
 
1384 
                reset_jtag;
1385 
                for (write_scan_idx = 0; write_scan_idx < sld_node_n_scan; write_scan_idx = write_scan_idx + 1)
1386 
                    begin : all_scans_loop
1387 
                        tempType[3] = scan_type[type_idx_cur];
1388 
                        tempType[2] = scan_type[type_idx_cur - 1];
1389 
                        tempType[1] = scan_type[type_idx_cur - 2];
1390 
                        tempType[0] = scan_type[type_idx_cur - 3];
1391 
                        time_idx_cur = time_idx_cur - `DEFAULT_BIT_LENGTH;
1392 
                        length_idx_cur = length_idx_cur - `DEFAULT_BIT_LENGTH;
1393 
                        for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1)
1394 
                            begin : get_scan_time
1395 
                                tempTime[tempLength_idx] = scan_time[time_idx_cur + tempLength_idx];
1396 
                            end // get_scan_time
1397 
                            delayTime =(`DELAY_RESOLUTION * `CLK_PERIOD * tempTime);
1398 
                            # delayTime;
1399 
                        if (tempType == `V_IR_SCAN_TYPE)
1400 
                            begin
1401 
                                for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1)
1402 
                                    begin : ir_get_length
1403 
                                        tempLength[tempLength_idx] = scan_length[length_idx_cur + tempLength_idx];
1404 
                                    end // ir_get_length
1405 
                                v_ir_scan(tempLength);
1406 
                            end
1407 
                        else
1408 
                            begin
1409 
                                if (tempType == `V_DR_SCAN_TYPE)
1410 
                                    begin
1411 
                                        for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1)
1412 
                                            begin : dr_get_length
1413 
                                                tempLength[tempLength_idx] = scan_length[length_idx_cur + tempLength_idx];
1414 
                                            end // dr_get_length
1415 
                                        v_dr_scan(tempLength);
1416 
                                    end
1417 
                                else
1418 
                                    begin
1419 
                                        $display("Invalid scan type");
1420 
                                    end
1421 
                            end
1422 
                        type_idx_cur = type_idx_cur - 4;
1423 
                    end // all_scans_loop
1424 
                //get into tlr state
1425 
                for (tempLength_idx = 0; tempLength_idx < 6; tempLength_idx= tempLength_idx + 1)
1426 
                    begin
1427 
                        tms_reg = 1'b1;
1428 
                        clock_tck(tms_reg,tdi_reg);
1429 
                    end
1430 
            end //execute
1431 
 
1432 
endmodule // signal_gen
1433 
 
1434 
 
1435 
//synopsys  translate_on
1436 
//synthesis translate_on

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