URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [jtag_wb_test/] [verilog/] [testbench.v] - Blame information for rev 48

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`timescale 1 ps / 1 ps
 
module testbench;
 
 
    reg clk;
    reg reset;
    wire [3: 0]led;
    reg  [3: 0]btn;
 
 
   initial begin
       clk = 1'b0;
       forever clk = #10 ~clk;
   end
 
  initial begin
        reset=1'b1;
        #10
        @(posedge clk) #1 reset=1'b0;
 
   end
 
 
         xilinx_jtag_test uut (
                .clk(clk),
                .led(led),
                .btn(btn),
                .reset(reset)
        );
 
 
 
 
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	48	alirezamon	`timescale 1 ps / 1 ps
2
3			`module testbench;`
4
5
6			`reg clk;`
7			`reg reset;`
8			`wire [3: 0]led;`
9			`reg [3: 0]btn;`
10
11
12			`initial begin`
13			`clk = 1'b0;`
14			`forever clk = #10 ~clk;`
15			`end`
16
17			`initial begin`
18			`reset=1'b1;`
19			`#10`
20			`@(posedge clk) #1 reset=1'b0;`
21
22			`end`
23
24
25			`xilinx_jtag_test uut (`
26			`.clk(clk),`
27			`.led(led),`
28			`.btn(btn),`
29			`.reset(reset)`
30			`);`
31
32
33
34
35
36			`endmodule`
37
38
39

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [jtag_wb_test/] [verilog/] [testbench.v] - Blame information for rev 48