URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [pronoc_uart/] [model.tcl] - Blame information for rev 48

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#!/usr/bin/tclsh
 
###################################################################
## Author      : Alireza Monemi
## Email       : 
## Description : Compile all verilog files inside the design folder 
##             : using modelsim
###################################################################
set text "###################################################################"
set text "##                Start Compilation Script "
set text "###################################################################"
 
###################################################################
##---- Specify variables
set text "###################################################################"
set text "##---- Specify variables"
 
##-- Project path variables
 
 
set path0       [pwd]
set path        [pwd]/verilog
set uart        $path0/../../jtag_uart/pronoc_jtag_uart.v
#set jtag       $path0/../../jtag_wb/xilinx_jtag_wb.v   
 
set comp_path                   $::env(PRONOC_WORK)/simulation
set work_path                   $comp_path/work
 
puts "work path is : $work_path"
 
 
##-- change directory
file mkdir $comp_path
 
cd $comp_path
exec rm -Rf *
proc r  {} {uplevel #0 source compile.tcl}
proc rr {} {global last_compile_time
            set last_compile_time 0
            r                            }
proc q  {} {quit -force                  }
 
proc sleep {N} {
    after [expr {int($N * 1000)}]
}
 
 
#Does this installation support Tk?
set tk_ok 1
if [catch {package require Tk}] {set tk_ok 0}
 
###################################################################
##---- 1. Creating working library
set text "###################################################################"
set text "##---- 1. Creating working library"
 
##-- Create work lib
vlib $work_path
 
##-- Mapping work lib
vmap work $work_path
 
 
 
###################################################################
##---- 3. Compile the Design
set text "###################################################################"
set text "##---- 3. Compile the Design"
 
 
# Compile out of date files
set time_now [clock seconds]
 
if {[file isfile start_time.txt] != 0} {
        set fp [open start_time.txt r]
        set line [gets $fp]
        close $fp
        regexp {\d+} $line last_compile_time
        puts "last compiled time is  $last_compile_time"
} else {
        set last_compile_time 0
}
 
 
 
 
 
foreach a [list $path]  {
      puts "$a "
      set lib_file_list [glob -directory $a *.v *.sv]
        foreach f $lib_file_list {
 
                if { $last_compile_time < [file mtime $f] } {
                        vlog  -work  $work_path  +acc=rn +incdir+$a+$path0  $f
 
                         set last_compile_time 0
                } else {
                         puts "$f is uptodate"
                }
        }
  }
vlog  -work  $work_path  +acc=rn +incdir+$a+$path0  $uart
#vlog  -work  $work_path  +acc=rn +incdir+$a+$path0  $jtag                      
 
 
 
 
set last_compile_time $time_now
 
 
 
set text "###################################################################"
set text "##                       END OF COMPILATION"
set text "###################################################################"
 
 
#vsim -t ps -L altera_mf_ver work.testbench_router
vsim   -t ps  work.testbench
 
#do "$comp_path/wave.do"
 
run 100 ms
 
quit
 
 
#####################################################################################
 

Line No.	Rev	Author	Line
1	48	alirezamon	`#!/usr/bin/tclsh`
2
3			`###################################################################`
4			`## Author : Alireza Monemi`
5			`## Email :`
6			`## Description : Compile all verilog files inside the design folder`
7			`## : using modelsim`
8			`###################################################################`
9			`set text "###################################################################"`
10			`set text "## Start Compilation Script "`
11			`set text "###################################################################"`
12
13			`###################################################################`
14			`##---- Specify variables`
15			`set text "###################################################################"`
16			`set text "##---- Specify variables"`
17
18			`##-- Project path variables`
19
20
21			`set path0 [pwd]`
22			`set path [pwd]/verilog`
23			`set uart $path0/../../jtag_uart/pronoc_jtag_uart.v`
24			`#set jtag $path0/../../jtag_wb/xilinx_jtag_wb.v`
25
26			`set comp_path $::env(PRONOC_WORK)/simulation`
27			`set work_path $comp_path/work`
28
29			`puts "work path is : $work_path"`
30
31
32			`##-- change directory`
33			`file mkdir $comp_path`
34
35			`cd $comp_path`
36			`exec rm -Rf *`
37			`proc r {} {uplevel #0 source compile.tcl}`
38			`proc rr {} {global last_compile_time`
39			`set last_compile_time 0`
40			`r }`
41			`proc q {} {quit -force }`
42
43			`proc sleep {N} {`
44			`after [expr {int($N * 1000)}]`
45			`}`
46
47
48			`#Does this installation support Tk?`
49			`set tk_ok 1`
50			`if [catch {package require Tk}] {set tk_ok 0}`
51
52			`###################################################################`
53			`##---- 1. Creating working library`
54			`set text "###################################################################"`
55			`set text "##---- 1. Creating working library"`
56
57			`##-- Create work lib`
58			`vlib $work_path`
59
60			`##-- Mapping work lib`
61			`vmap work $work_path`
62
63
64
65			`###################################################################`
66			`##---- 3. Compile the Design`
67			`set text "###################################################################"`
68			`set text "##---- 3. Compile the Design"`
69
70
71			`# Compile out of date files`
72			`set time_now [clock seconds]`
73
74			`if {[file isfile start_time.txt] != 0} {`
75			`set fp [open start_time.txt r]`
76			`set line [gets $fp]`
77			`close $fp`
78			`regexp {\d+} $line last_compile_time`
79			`puts "last compiled time is $last_compile_time"`
80			`} else {`
81			`set last_compile_time 0`
82			`}`
83
84
85
86
87
88			`foreach a [list $path] {`
89			`puts "$a "`
90			`set lib_file_list [glob -directory $a .v .sv]`
91			`foreach f $lib_file_list {`
92
93			`if { $last_compile_time < [file mtime $f] } {`
94			`vlog -work $work_path +acc=rn +incdir+$a+$path0 $f`
95
96			`set last_compile_time 0`
97			`} else {`
98			`puts "$f is uptodate"`
99			`}`
100			`}`
101			`}`
102			`vlog -work $work_path +acc=rn +incdir+$a+$path0 $uart`
103			`#vlog -work $work_path +acc=rn +incdir+$a+$path0 $jtag`
104
105
106
107
108			`set last_compile_time $time_now`
109
110
111
112			`set text "###################################################################"`
113			`set text "## END OF COMPILATION"`
114			`set text "###################################################################"`
115
116
117			`#vsim -t ps -L altera_mf_ver work.testbench_router`
118			`vsim -t ps work.testbench`
119
120			`#do "$comp_path/wave.do"`
121
122			`run 100 ms`
123
124			`quit`
125
126
127			`#####################################################################################`
128

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [pronoc_uart/] [model.tcl] - Blame information for rev 48