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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_simulation/] [pronoc_uart/] [verilog/] [uart_jtag_testbench.v] - Blame information for rev 48

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1 48 alirezamon 
/**************************************
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* Module: uart_jtag_testbench
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* Date:2020-04-14
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* Author: alireza
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*
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* Description:
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***************************************/
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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module  uart_jtag_testbench #(
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     parameter JTAG_INDEX =  126,
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     parameter JAw = 32,
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     parameter JDw=32,
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     parameter JINDEXw = 8,
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     parameter JSTATUSw = 8
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)(
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   wb_to_jtag,
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   jtag_to_wb
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);
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    localparam
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        J2WBw= 1+1+JDw+JAw,
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        WB2Jw=1+JSTATUSw+JINDEXw+1+JDw;
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     //jtag
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    input   [WB2Jw-1  : 0] wb_to_jtag;
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    output  [J2WBw-1 : 0] jtag_to_wb;
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    wire [JSTATUSw-1 : 0] wb_to_jtag_status;
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    wire [JINDEXw-1 : 0] wb_to_jtag_index;
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    reg [JDw-1 : 0] jtag_to_wb_dat;
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    reg [JAw-1 : 0] jtag_to_wb_addr;
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    reg jtag_to_wb_stb;
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    reg jtag_to_wb_we;
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    wire [JDw-1 : 0] wb_to_jtag_dat;
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    wire wb_to_jtag_ack;
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    reg [15 : 0] jtag_wspace;
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    assign  {wb_to_jtag_status,wb_to_jtag_ack,wb_to_jtag_dat,wb_to_jtag_index,clk}=wb_to_jtag;
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    assign  jtag_to_wb= {jtag_to_wb_addr,jtag_to_wb_stb,jtag_to_wb_we,jtag_to_wb_dat};
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    reg jtag_clk;
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    initial begin
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        jtag_clk=1'b0;
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        forever jtag_clk = #33 ~jtag_clk;
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    end
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    reg  capture_jtag_dat_o;
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    reg [JDw-1 : 0] captured_jtag_dat;
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    always @(posedge jtag_clk)begin
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        if(capture_jtag_dat_o) captured_jtag_dat= wb_to_jtag_dat;
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    end
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    task jtag_wr_wb_reg;
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    input reg addr;
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    input integer dat_in;
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    begin
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       jtag_to_wb_addr= addr;
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       jtag_to_wb_dat= dat_in;
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       jtag_to_wb_stb= 1'b1;
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       // wb_cyc_i= 1'b1;
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       jtag_to_wb_we =1'b1;
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       @(posedge wb_to_jtag_ack)#1
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        capture_jtag_dat_o=1'b1;
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       @(posedge jtag_clk)#1;
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       capture_jtag_dat_o=1'b0;
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       jtag_to_wb_stb= 1'b0;
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       //wb_cyc_i= 1'b0;
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     // $display(" jtag_wr_wb_reg (%d,%d);",addr,dat_in);
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    end
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    endtask
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     //always @(*)begin         captured_jtag_dat= wb_to_jtag_dat;    end
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    task jtag_rd_wb_reg;
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    input reg addr;
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    begin
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       jtag_to_wb_addr= addr;
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       jtag_to_wb_stb= 1'b1;
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       //wb_cyc_i= 1'b1;
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       jtag_to_wb_we =1'b0;
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       @(posedge wb_to_jtag_ack)#1
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       capture_jtag_dat_o=1'b1;
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       @(posedge jtag_clk)#1;
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       capture_jtag_dat_o=1'b0;
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      // $display("%d",captured_jtag_dat);
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       jtag_to_wb_stb= 1'b0;
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       //wb_cyc_i= 1'b0;
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    end
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    endtask
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    integer   char_idx;       // character_loop index
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    reg [0: 7] character;
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    task  jtag_capture;
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    input [0:7] data;
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    begin
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        jtag_wr_wb_reg(0,data);
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        if(captured_jtag_dat[7:0]!=0) $display("%tjtag read %s",$time,captured_jtag_dat[7:0]);
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        jtag_wspace = captured_jtag_dat[23:8];
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        #1021;
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    end
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    endtask
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    task capture_until_send_chanel_ready;
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    begin
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        while (jtag_wspace ==0)begin
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            jtag_capture(0);
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        end
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    end
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    endtask
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    task  jtag_putc;
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    input [0:7] data;
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    begin
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        capture_until_send_chanel_ready();
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        jtag_capture(data);
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    end
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    endtask
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    task  jtag_puts;
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    input [0:1023] data;
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    begin
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        character=1;
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        for(char_idx = 0;char_idx <=1023 ;char_idx = char_idx + 8)
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        begin : character_loop
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            character[0]  = data[char_idx];
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            character[1]  = data[char_idx+1];
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            character[2]  = data[char_idx+2];
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            character[3]  = data[char_idx+3];
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            character[4]  = data[char_idx+4];
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            character[5]  = data[char_idx+5];
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            character[6]  = data[char_idx+6];
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            character[7]  = data[char_idx+7];
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            if (character!=0) jtag_putc(character);
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        end//for
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    end
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    endtask
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    initial begin
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       jtag_to_wb_addr= 0;
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       jtag_to_wb_dat= 0;
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       jtag_to_wb_stb= 1'b0;
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       jtag_to_wb_we =1'b0;
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       capture_jtag_dat_o=1'b0;
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       jtag_wspace=2;
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       #300000
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       repeat(15) begin
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            jtag_capture(0);
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       end
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      jtag_puts("XYZXYZ");
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       repeat(1500) begin
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            jtag_capture(0);
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       end
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    end
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endmodule
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