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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_uart/] [altera_jtag_uart.v] - Blame information for rev 48

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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
 
module altera_jtag_uart #(
    parameter SIM_BUFFER_SIZE   =100,
    parameter SIM_WAIT_COUNT    =1000
 
 
)(
    reset,
    clk,
    irq,
    s_dat_i,
    s_sel_i,
    s_addr_i,
    s_cti_i,
    s_stb_i,
    s_cyc_i,
    s_we_i,
    s_dat_o,
    s_ack_o,
    RxD_din_sim,
    RxD_wr_sim,
    RxD_ready_sim
 
 
);
 
        localparam
                Dw            =   32,
                M_Aw          =   32,
                TAGw          =   3,
                SELw          =   4;
 
 
 
    input reset,clk;
//wishbone slave interface signals
    input   [Dw-1       :   0]      s_dat_i;
    input   [SELw-1     :   0]      s_sel_i;
    input                           s_addr_i;
    input   [TAGw-1     :   0]      s_cti_i;
    input                           s_stb_i;
    input                           s_cyc_i;
    input                           s_we_i;
    output irq;
    output  [Dw-1       :   0]  s_dat_o;
    output                     s_ack_o;
 
 
 
 
    input [7:0 ] RxD_din_sim;
    input RxD_wr_sim;
    output RxD_ready_sim;
 
 
    `ifdef MODEL_TECH
        `define RUN_SIM
    `endif
    `ifdef VERILATOR
        `define RUN_SIM
    `endif
 
 
 
`ifdef RUN_SIM
 
        // code for simulation with verilator/mpdelsim
    // synthesis translate_off
        altera_uart_simulator #(
                .BUFFER_SIZE(SIM_BUFFER_SIZE),
                .WAIT_COUNT(SIM_WAIT_COUNT)
        )
        Suart
        (
                .reset(reset),
                .clk(clk),
                .s_dat_i(s_dat_i),
                .s_sel_i(s_sel_i),
                .s_addr_i(s_addr_i),
                .s_cti_i(s_cti_i),
                .s_stb_i(s_stb_i),
                .s_cyc_i(s_cyc_i),
                .s_we_i(s_we_i),
                .s_dat_o(s_dat_o),
                .s_ack_o(s_ack_o),
                .RxD_din(RxD_din_sim),
                .RxD_wr(RxD_wr_sim),
                .RxD_ready(RxD_ready_sim)
 
 
        );
        // synthesis translate_on
`else
 `
// code for synthesis
 
        altera_jtag_uart_wb_hw Juart(
                .clk(clk),
                .rst(reset),
                .wb_irq(irq),
                .dat_o(s_dat_o),
                .ack_o(s_ack_o),
                .adr_i(s_addr_i),
                .stb_i(s_stb_i),
                .cyc_i(s_cyc_i),
                .we_i(s_we_i),
                .dat_i(s_dat_i),
                .dataavailable(),
                .readyfordata()
        );
 
        assign  RxD_ready_sim = 1'bX;
 
 
`endif
 
 
endmodule
 
 
 
 
 
module altera_jtag_uart_wb_hw(
  input                                 clk,rst,
  output           wb_irq,
  output  [ 31: 0] dat_o,
  output           ack_o,
  input            adr_i,
  input            stb_i,
  input            cyc_i,
  input            we_i,
  input   [ 31: 0] dat_i,
  output           dataavailable,
  output           readyfordata
);
        wire av_waitrequest;
        assign ack_o=~av_waitrequest;
 
        qsys_jtag_uart_0 jtag_uart_0 (
                .clk            (clk),
                .rst_n          (~rst),
                .av_chipselect  (stb_i),
                .av_address     (adr_i),
                .av_read_n      (~(cyc_i&~we_i)),
                .av_readdata    (dat_o),
                .av_write_n     (~(cyc_i&we_i)),
                .av_writedata   (dat_i),
                .av_waitrequest (av_waitrequest),
                .av_irq         (wb_irq),
                .dataavailable  (dataavailable),
                .readyfordata   (readyfordata)
        );
 
endmodule
 
 
 
 
 
 
//Legal Notice: (C)2015 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
 
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module qsys_jtag_uart_0_sim_scfifo_w (
                                       // inputs:
                                        clk,
                                        fifo_wdata,
                                        fifo_wr,
 
                                       // outputs:
                                        fifo_FF,
                                        r_dat,
                                        wfifo_empty,
                                        wfifo_used
                                     )
;
 
  output           fifo_FF;
  output  [  7: 0] r_dat;
  output           wfifo_empty;
  output  [  5: 0] wfifo_used;
  input            clk;
  input   [  7: 0] fifo_wdata;
  input            fifo_wr;
 
  wire             fifo_FF;
  wire    [  7: 0] r_dat;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  always @(posedge clk)
    begin
      if (fifo_wr)
          $write("%c", fifo_wdata);
    end
 
 
  assign wfifo_used = {6{1'b0}};
  assign r_dat = {8{1'b0}};
  assign fifo_FF = 1'b0;
  assign wfifo_empty = 1'b1;
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module qsys_jtag_uart_0_scfifo_w (
                                   // inputs:
                                    clk,
                                    fifo_clear,
                                    fifo_wdata,
                                    fifo_wr,
                                    rd_wfifo,
 
                                   // outputs:
                                    fifo_FF,
                                    r_dat,
                                    wfifo_empty,
                                    wfifo_used
                                 )
;
 
  output           fifo_FF;
  output  [  7: 0] r_dat;
  output           wfifo_empty;
  output  [  5: 0] wfifo_used;
  input            clk;
  input            fifo_clear;
  input   [  7: 0] fifo_wdata;
  input            fifo_wr;
  input            rd_wfifo;
 
  wire             fifo_FF;
  wire    [  7: 0] r_dat;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  qsys_jtag_uart_0_sim_scfifo_w the_qsys_jtag_uart_0_sim_scfifo_w
    (
      .clk         (clk),
      .fifo_FF     (fifo_FF),
      .fifo_wdata  (fifo_wdata),
      .fifo_wr     (fifo_wr),
      .r_dat       (r_dat),
      .wfifo_empty (wfifo_empty),
      .wfifo_used  (wfifo_used)
    );
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  scfifo wfifo
//    (
//      .aclr (fifo_clear),
//      .clock (clk),
//      .data (fifo_wdata),
//      .empty (wfifo_empty),
//      .full (fifo_FF),
//      .q (r_dat),
//      .rdreq (rd_wfifo),
//      .usedw (wfifo_used),
//      .wrreq (fifo_wr)
//    );
//
//  defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
//           wfifo.lpm_numwords = 64,
//           wfifo.lpm_showahead = "OFF",
//           wfifo.lpm_type = "scfifo",
//           wfifo.lpm_width = 8,
//           wfifo.lpm_widthu = 6,
//           wfifo.overflow_checking = "OFF",
//           wfifo.underflow_checking = "OFF",
//           wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module qsys_jtag_uart_0_sim_scfifo_r (
                                       // inputs:
                                        clk,
                                        fifo_rd,
                                        rst_n,
 
                                       // outputs:
                                        fifo_EF,
                                        fifo_rdata,
                                        rfifo_full,
                                        rfifo_used
                                     )
;
 
  output           fifo_EF;
  output  [  7: 0] fifo_rdata;
  output           rfifo_full;
  output  [  5: 0] rfifo_used;
  input            clk;
  input            fifo_rd;
  input            rst_n;
 
  reg     [ 31: 0] bytes_left;
  wire             fifo_EF;
  reg              fifo_rd_d;
  wire    [  7: 0] fifo_rdata;
  wire             new_rom;
  wire    [ 31: 0] num_bytes;
  wire    [  6: 0] rfifo_entries;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  // Generate rfifo_entries for simulation
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          bytes_left <= 32'h0;
          fifo_rd_d <= 1'b0;
        end
      else
        begin
          fifo_rd_d <= fifo_rd;
          // decrement on read
          if (fifo_rd_d)
              bytes_left <= bytes_left - 1'b1;
          // catch new contents
          if (new_rom)
              bytes_left <= num_bytes;
        end
    end
 
 
  assign fifo_EF = bytes_left == 32'b0;
  assign rfifo_full = bytes_left > 7'h40;
  assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
  assign rfifo_used = rfifo_entries[5 : 0];
  assign new_rom = 1'b0;
  assign num_bytes = 32'b0;
  assign fifo_rdata = 8'b0;
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module qsys_jtag_uart_0_scfifo_r (
                                   // inputs:
                                    clk,
                                    fifo_clear,
                                    fifo_rd,
                                    rst_n,
                                    t_dat,
                                    wr_rfifo,
 
                                   // outputs:
                                    fifo_EF,
                                    fifo_rdata,
                                    rfifo_full,
                                    rfifo_used
                                 )
;
 
  output           fifo_EF;
  output  [  7: 0] fifo_rdata;
  output           rfifo_full;
  output  [  5: 0] rfifo_used;
  input            clk;
  input            fifo_clear;
  input            fifo_rd;
  input            rst_n;
  input   [  7: 0] t_dat;
  input            wr_rfifo;
 
  wire             fifo_EF;
  wire    [  7: 0] fifo_rdata;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  qsys_jtag_uart_0_sim_scfifo_r the_qsys_jtag_uart_0_sim_scfifo_r
    (
      .clk        (clk),
      .fifo_EF    (fifo_EF),
      .fifo_rd    (fifo_rd),
      .fifo_rdata (fifo_rdata),
      .rfifo_full (rfifo_full),
      .rfifo_used (rfifo_used),
      .rst_n      (rst_n)
    );
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  scfifo rfifo
//    (
//      .aclr (fifo_clear),
//      .clock (clk),
//      .data (t_dat),
//      .empty (fifo_EF),
//      .full (rfifo_full),
//      .q (fifo_rdata),
//      .rdreq (fifo_rd),
//      .usedw (rfifo_used),
//      .wrreq (wr_rfifo)
//    );
//
//  defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
//           rfifo.lpm_numwords = 64,
//           rfifo.lpm_showahead = "OFF",
//           rfifo.lpm_type = "scfifo",
//           rfifo.lpm_width = 8,
//           rfifo.lpm_widthu = 6,
//           rfifo.overflow_checking = "OFF",
//           rfifo.underflow_checking = "OFF",
//           rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module qsys_jtag_uart_0 (
                          // inputs:
                           av_address,
                           av_chipselect,
                           av_read_n,
                           av_write_n,
                           av_writedata,
                           clk,
                           rst_n,
 
                          // outputs:
                           av_irq,
                           av_readdata,
                           av_waitrequest,
                           dataavailable,
                           readyfordata
                        )
  /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
 
  output           av_irq;
  output  [ 31: 0] av_readdata;
  output           av_waitrequest;
  output           dataavailable;
  output           readyfordata;
  input            av_address;
  input            av_chipselect;
  input            av_read_n;
  input            av_write_n;
  input   [ 31: 0] av_writedata;
  input            clk;
  input            rst_n;
 
  reg              ac;
  wire             activity;
  wire             av_irq;
  wire    [ 31: 0] av_readdata;
  reg              av_waitrequest;
  reg              dataavailable;
  reg              fifo_AE;
  reg              fifo_AF;
  wire             fifo_EF;
  wire             fifo_FF;
  wire             fifo_clear;
  wire             fifo_rd;
  wire    [  7: 0] fifo_rdata;
  wire    [  7: 0] fifo_wdata;
  reg              fifo_wr;
  reg              ien_AE;
  reg              ien_AF;
  wire             ipen_AE;
  wire             ipen_AF;
  reg              pause_irq;
  wire    [  7: 0] r_dat;
  wire             r_ena;
  reg              r_val;
  wire             rd_wfifo;
  reg              read_0;
  reg              readyfordata;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
  reg              rvalid;
  reg              sim_r_ena;
  reg              sim_t_dat;
  reg              sim_t_ena;
  reg              sim_t_pause;
  wire    [  7: 0] t_dat;
  reg              t_dav;
  wire             t_ena;
  wire             t_pause;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
  reg              woverflow;
  wire             wr_rfifo;
  //avalon_jtag_slave, which is an e_avalon_slave
  assign rd_wfifo = r_ena & ~wfifo_empty;
  assign wr_rfifo = t_ena & ~rfifo_full;
  assign fifo_clear = ~rst_n;
  qsys_jtag_uart_0_scfifo_w the_qsys_jtag_uart_0_scfifo_w
    (
      .clk         (clk),
      .fifo_FF     (fifo_FF),
      .fifo_clear  (fifo_clear),
      .fifo_wdata  (fifo_wdata),
      .fifo_wr     (fifo_wr),
      .r_dat       (r_dat),
      .rd_wfifo    (rd_wfifo),
      .wfifo_empty (wfifo_empty),
      .wfifo_used  (wfifo_used)
    );
 
  qsys_jtag_uart_0_scfifo_r the_qsys_jtag_uart_0_scfifo_r
    (
      .clk        (clk),
      .fifo_EF    (fifo_EF),
      .fifo_clear (fifo_clear),
      .fifo_rd    (fifo_rd),
      .fifo_rdata (fifo_rdata),
      .rfifo_full (rfifo_full),
      .rfifo_used (rfifo_used),
      .rst_n      (rst_n),
      .t_dat      (t_dat),
      .wr_rfifo   (wr_rfifo)
    );
 
  assign ipen_AE = ien_AE & fifo_AE;
  assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
  assign av_irq = ipen_AE | ipen_AF;
  assign activity = t_pause | t_ena;
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
          pause_irq <= 1'b0;
      else // only if fifo is not empty...
      if (t_pause & ~fifo_EF)
          pause_irq <= 1'b1;
      else if (read_0)
          pause_irq <= 1'b0;
    end
 
 
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          r_val <= 1'b0;
          t_dav <= 1'b1;
        end
      else
        begin
          r_val <= r_ena & ~wfifo_empty;
          t_dav <= ~rfifo_full;
        end
    end
 
 
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          fifo_AE <= 1'b0;
          fifo_AF <= 1'b0;
          fifo_wr <= 1'b0;
          rvalid <= 1'b0;
          read_0 <= 1'b0;
          ien_AE <= 1'b0;
          ien_AF <= 1'b0;
          ac <= 1'b0;
          woverflow <= 1'b0;
          av_waitrequest <= 1'b1;
        end
      else
        begin
          fifo_AE <= {fifo_FF,wfifo_used} <= 8;
          fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
          fifo_wr <= 1'b0;
          read_0 <= 1'b0;
          av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
          if (activity)
              ac <= 1'b1;
          // write
          if (av_chipselect & ~av_write_n & av_waitrequest)
              // addr 1 is control; addr 0 is data
              if (av_address)
                begin
                  ien_AF <= av_writedata[0];
                  ien_AE <= av_writedata[1];
                  if (av_writedata[10] & ~activity)
                      ac <= 1'b0;
                end
              else
                begin
                  fifo_wr <= ~fifo_FF;
                  woverflow <= fifo_FF;
                end
          // read
          if (av_chipselect & ~av_read_n & av_waitrequest)
            begin
              // addr 1 is interrupt; addr 0 is data
              if (~av_address)
                  rvalid <= ~fifo_EF;
              read_0 <= ~av_address;
            end
        end
    end
 
 
  assign fifo_wdata = av_writedata[7 : 0];
  assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
  assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
          readyfordata <= 0;
      else
        readyfordata <= ~fifo_FF;
    end
 
 
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  // Tie off Atlantic Interface signals not used for simulation
  always @(posedge clk)
    begin
      sim_t_pause <= 1'b0;
      sim_t_ena <= 1'b0;
      sim_t_dat <= t_dav ? r_dat : {8{r_val}};
      sim_r_ena <= 1'b0;
    end
 
 
  assign r_ena = sim_r_ena;
  assign t_ena = sim_t_ena;
  assign t_dat = sim_t_dat;
  assign t_pause = sim_t_pause;
  always @(fifo_EF)
    begin
      dataavailable = ~fifo_EF;
    end
 
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  alt_jtag_atlantic qsys_jtag_uart_0_alt_jtag_atlantic
//    (
//      .clk (clk),
//      .r_dat (r_dat),
//      .r_ena (r_ena),
//      .r_val (r_val),
//      .rst_n (rst_n),
//      .t_dat (t_dat),
//      .t_dav (t_dav),
//      .t_ena (t_ena),
//      .t_pause (t_pause)
//    );
//
//  defparam qsys_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
//           qsys_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
//           qsys_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
//           qsys_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
//  always @(posedge clk or negedge rst_n)
//    begin
//      if (rst_n == 0)
//          dataavailable <= 0;
//      else 
//        dataavailable <= ~fifo_EF;
//    end
//
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_uart/] [altera_jtag_uart.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`// synthesis translate_off`
2			`timescale 1ns / 1ps
3			`// synthesis translate_on`
4
5
6			`module altera_jtag_uart #(`
7			`parameter SIM_BUFFER_SIZE =100,`
8			`parameter SIM_WAIT_COUNT =1000`
9
10
11			`)(`
12			`reset,`
13			`clk,`
14			`irq,`
15			`s_dat_i,`
16			`s_sel_i,`
17			`s_addr_i,`
18			`s_cti_i,`
19			`s_stb_i,`
20			`s_cyc_i,`
21			`s_we_i,`
22			`s_dat_o,`
23			`s_ack_o,`
24			`RxD_din_sim,`
25			`RxD_wr_sim,`
26			`RxD_ready_sim`
27
28
29			`);`
30
31			`localparam`
32			`Dw = 32,`
33			`M_Aw = 32,`
34			`TAGw = 3,`
35			`SELw = 4;`
36
37
38
39			`input reset,clk;`
40			`//wishbone slave interface signals`
41			`input [Dw-1 : 0] s_dat_i;`
42			`input [SELw-1 : 0] s_sel_i;`
43			`input s_addr_i;`
44			`input [TAGw-1 : 0] s_cti_i;`
45			`input s_stb_i;`
46			`input s_cyc_i;`
47			`input s_we_i;`
48			`output irq;`
49			`output [Dw-1 : 0] s_dat_o;`
50			`output s_ack_o;`
51
52
53
54
55			`input [7:0 ] RxD_din_sim;`
56			`input RxD_wr_sim;`
57			`output RxD_ready_sim;`
58
59
60			`ifdef MODEL_TECH
61			`define RUN_SIM
62			`endif
63			`ifdef VERILATOR
64			`define RUN_SIM
65			`endif
66
67
68
69			`ifdef RUN_SIM
70
71			`// code for simulation with verilator/mpdelsim`
72			`// synthesis translate_off`
73			`altera_uart_simulator #(`
74			`.BUFFER_SIZE(SIM_BUFFER_SIZE),`
75			`.WAIT_COUNT(SIM_WAIT_COUNT)`
76			`)`
77			`Suart`
78			`(`
79			`.reset(reset),`
80			`.clk(clk),`
81			`.s_dat_i(s_dat_i),`
82			`.s_sel_i(s_sel_i),`
83			`.s_addr_i(s_addr_i),`
84			`.s_cti_i(s_cti_i),`
85			`.s_stb_i(s_stb_i),`
86			`.s_cyc_i(s_cyc_i),`
87			`.s_we_i(s_we_i),`
88			`.s_dat_o(s_dat_o),`
89			`.s_ack_o(s_ack_o),`
90			`.RxD_din(RxD_din_sim),`
91			`.RxD_wr(RxD_wr_sim),`
92			`.RxD_ready(RxD_ready_sim)`
93
94
95			`);`
96			`// synthesis translate_on`
97			`else
98			`
99			`// code for synthesis`
100
101			`altera_jtag_uart_wb_hw Juart(`
102			`.clk(clk),`
103			`.rst(reset),`
104			`.wb_irq(irq),`
105			`.dat_o(s_dat_o),`
106			`.ack_o(s_ack_o),`
107			`.adr_i(s_addr_i),`
108			`.stb_i(s_stb_i),`
109			`.cyc_i(s_cyc_i),`
110			`.we_i(s_we_i),`
111			`.dat_i(s_dat_i),`
112			`.dataavailable(),`
113			`.readyfordata()`
114			`);`
115
116			`assign RxD_ready_sim = 1'bX;`
117
118
119			`endif
120
121
122			`endmodule`
123
124
125
126
127
128			`module altera_jtag_uart_wb_hw(`
129			`input clk,rst,`
130			`output wb_irq,`
131			`output [ 31: 0] dat_o,`
132			`output ack_o,`
133			`input adr_i,`
134			`input stb_i,`
135			`input cyc_i,`
136			`input we_i,`
137			`input [ 31: 0] dat_i,`
138			`output dataavailable,`
139			`output readyfordata`
140			`);`
141			`wire av_waitrequest;`
142			`assign ack_o=~av_waitrequest;`
143
144			`qsys_jtag_uart_0 jtag_uart_0 (`
145			`.clk (clk),`
146			`.rst_n (~rst),`
147			`.av_chipselect (stb_i),`
148			`.av_address (adr_i),`
149			`.av_read_n (~(cyc_i&~we_i)),`
150			`.av_readdata (dat_o),`
151			`.av_write_n (~(cyc_i&we_i)),`
152			`.av_writedata (dat_i),`
153			`.av_waitrequest (av_waitrequest),`
154			`.av_irq (wb_irq),`
155			`.dataavailable (dataavailable),`
156			`.readyfordata (readyfordata)`
157			`);`
158
159			`endmodule`
160
161
162
163
164
165
166			`//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your`
167			`//use of Altera Corporation's design tools, logic functions and other`
168			`//software and tools, and its AMPP partner logic functions, and any`
169			`//output files any of the foregoing (including device programming or`
170			`//simulation files), and any associated documentation or information are`
171			`//expressly subject to the terms and conditions of the Altera Program`
172			`//License Subscription Agreement or other applicable license agreement,`
173			`//including, without limitation, that your use is for the sole purpose`
174			`//of programming logic devices manufactured by Altera and sold by Altera`
175			`//or its authorized distributors. Please refer to the applicable`
176			`//agreement for further details.`
177
178
179
180			`// turn off superfluous verilog processor warnings`
181			`// altera message_level Level1`
182			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
183
184			`module qsys_jtag_uart_0_sim_scfifo_w (`
185			`// inputs:`
186			`clk,`
187			`fifo_wdata,`
188			`fifo_wr,`
189
190			`// outputs:`
191			`fifo_FF,`
192			`r_dat,`
193			`wfifo_empty,`
194			`wfifo_used`
195			`)`
196			`;`
197
198			`output fifo_FF;`
199			`output [ 7: 0] r_dat;`
200			`output wfifo_empty;`
201			`output [ 5: 0] wfifo_used;`
202			`input clk;`
203			`input [ 7: 0] fifo_wdata;`
204			`input fifo_wr;`
205
206			`wire fifo_FF;`
207			`wire [ 7: 0] r_dat;`
208			`wire wfifo_empty;`
209			`wire [ 5: 0] wfifo_used;`
210
211			`//synthesis translate_off`
212			`//////////////// SIMULATION-ONLY CONTENTS`
213			`always @(posedge clk)`
214			`begin`
215			`if (fifo_wr)`
216			`$write("%c", fifo_wdata);`
217			`end`
218
219
220			`assign wfifo_used = {6{1'b0}};`
221			`assign r_dat = {8{1'b0}};`
222			`assign fifo_FF = 1'b0;`
223			`assign wfifo_empty = 1'b1;`
224
225			`//////////////// END SIMULATION-ONLY CONTENTS`
226
227			`//synthesis translate_on`
228
229			`endmodule`
230
231
232			`// synthesis translate_off`
233			`timescale 1ns / 1ps
234			`// synthesis translate_on`
235
236			`// turn off superfluous verilog processor warnings`
237			`// altera message_level Level1`
238			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
239
240			`module qsys_jtag_uart_0_scfifo_w (`
241			`// inputs:`
242			`clk,`
243			`fifo_clear,`
244			`fifo_wdata,`
245			`fifo_wr,`
246			`rd_wfifo,`
247
248			`// outputs:`
249			`fifo_FF,`
250			`r_dat,`
251			`wfifo_empty,`
252			`wfifo_used`
253			`)`
254			`;`
255
256			`output fifo_FF;`
257			`output [ 7: 0] r_dat;`
258			`output wfifo_empty;`
259			`output [ 5: 0] wfifo_used;`
260			`input clk;`
261			`input fifo_clear;`
262			`input [ 7: 0] fifo_wdata;`
263			`input fifo_wr;`
264			`input rd_wfifo;`
265
266			`wire fifo_FF;`
267			`wire [ 7: 0] r_dat;`
268			`wire wfifo_empty;`
269			`wire [ 5: 0] wfifo_used;`
270
271			`//synthesis translate_off`
272			`//////////////// SIMULATION-ONLY CONTENTS`
273			`qsys_jtag_uart_0_sim_scfifo_w the_qsys_jtag_uart_0_sim_scfifo_w`
274			`(`
275			`.clk (clk),`
276			`.fifo_FF (fifo_FF),`
277			`.fifo_wdata (fifo_wdata),`
278			`.fifo_wr (fifo_wr),`
279			`.r_dat (r_dat),`
280			`.wfifo_empty (wfifo_empty),`
281			`.wfifo_used (wfifo_used)`
282			`);`
283
284
285			`//////////////// END SIMULATION-ONLY CONTENTS`
286
287			`//synthesis translate_on`
288			`//synthesis read_comments_as_HDL on`
289			`// scfifo wfifo`
290			`// (`
291			`// .aclr (fifo_clear),`
292			`// .clock (clk),`
293			`// .data (fifo_wdata),`
294			`// .empty (wfifo_empty),`
295			`// .full (fifo_FF),`
296			`// .q (r_dat),`
297			`// .rdreq (rd_wfifo),`
298			`// .usedw (wfifo_used),`
299			`// .wrreq (fifo_wr)`
300			`// );`
301			`//`
302			`// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",`
303			`// wfifo.lpm_numwords = 64,`
304			`// wfifo.lpm_showahead = "OFF",`
305			`// wfifo.lpm_type = "scfifo",`
306			`// wfifo.lpm_width = 8,`
307			`// wfifo.lpm_widthu = 6,`
308			`// wfifo.overflow_checking = "OFF",`
309			`// wfifo.underflow_checking = "OFF",`
310			`// wfifo.use_eab = "ON";`
311			`//`
312			`//synthesis read_comments_as_HDL off`
313
314			`endmodule`
315
316
317			`// synthesis translate_off`
318			`timescale 1ns / 1ps
319			`// synthesis translate_on`
320
321			`// turn off superfluous verilog processor warnings`
322			`// altera message_level Level1`
323			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
324
325			`module qsys_jtag_uart_0_sim_scfifo_r (`
326			`// inputs:`
327			`clk,`
328			`fifo_rd,`
329			`rst_n,`
330
331			`// outputs:`
332			`fifo_EF,`
333			`fifo_rdata,`
334			`rfifo_full,`
335			`rfifo_used`
336			`)`
337			`;`
338
339			`output fifo_EF;`
340			`output [ 7: 0] fifo_rdata;`
341			`output rfifo_full;`
342			`output [ 5: 0] rfifo_used;`
343			`input clk;`
344			`input fifo_rd;`
345			`input rst_n;`
346
347			`reg [ 31: 0] bytes_left;`
348			`wire fifo_EF;`
349			`reg fifo_rd_d;`
350			`wire [ 7: 0] fifo_rdata;`
351			`wire new_rom;`
352			`wire [ 31: 0] num_bytes;`
353			`wire [ 6: 0] rfifo_entries;`
354			`wire rfifo_full;`
355			`wire [ 5: 0] rfifo_used;`
356
357			`//synthesis translate_off`
358			`//////////////// SIMULATION-ONLY CONTENTS`
359			`// Generate rfifo_entries for simulation`
360			`always @(posedge clk or negedge rst_n)`
361			`begin`
362			`if (rst_n == 0)`
363			`begin`
364			`bytes_left <= 32'h0;`
365			`fifo_rd_d <= 1'b0;`
366			`end`
367			`else`
368			`begin`
369			`fifo_rd_d <= fifo_rd;`
370			`// decrement on read`
371			`if (fifo_rd_d)`
372			`bytes_left <= bytes_left - 1'b1;`
373			`// catch new contents`
374			`if (new_rom)`
375			`bytes_left <= num_bytes;`
376			`end`
377			`end`
378
379
380			`assign fifo_EF = bytes_left == 32'b0;`
381			`assign rfifo_full = bytes_left > 7'h40;`
382			`assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;`
383			`assign rfifo_used = rfifo_entries[5 : 0];`
384			`assign new_rom = 1'b0;`
385			`assign num_bytes = 32'b0;`
386			`assign fifo_rdata = 8'b0;`
387
388			`//////////////// END SIMULATION-ONLY CONTENTS`
389
390			`//synthesis translate_on`
391
392			`endmodule`
393
394
395			`// synthesis translate_off`
396			`timescale 1ns / 1ps
397			`// synthesis translate_on`
398
399			`// turn off superfluous verilog processor warnings`
400			`// altera message_level Level1`
401			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
402
403			`module qsys_jtag_uart_0_scfifo_r (`
404			`// inputs:`
405			`clk,`
406			`fifo_clear,`
407			`fifo_rd,`
408			`rst_n,`
409			`t_dat,`
410			`wr_rfifo,`
411
412			`// outputs:`
413			`fifo_EF,`
414			`fifo_rdata,`
415			`rfifo_full,`
416			`rfifo_used`
417			`)`
418			`;`
419
420			`output fifo_EF;`
421			`output [ 7: 0] fifo_rdata;`
422			`output rfifo_full;`
423			`output [ 5: 0] rfifo_used;`
424			`input clk;`
425			`input fifo_clear;`
426			`input fifo_rd;`
427			`input rst_n;`
428			`input [ 7: 0] t_dat;`
429			`input wr_rfifo;`
430
431			`wire fifo_EF;`
432			`wire [ 7: 0] fifo_rdata;`
433			`wire rfifo_full;`
434			`wire [ 5: 0] rfifo_used;`
435
436			`//synthesis translate_off`
437			`//////////////// SIMULATION-ONLY CONTENTS`
438			`qsys_jtag_uart_0_sim_scfifo_r the_qsys_jtag_uart_0_sim_scfifo_r`
439			`(`
440			`.clk (clk),`
441			`.fifo_EF (fifo_EF),`
442			`.fifo_rd (fifo_rd),`
443			`.fifo_rdata (fifo_rdata),`
444			`.rfifo_full (rfifo_full),`
445			`.rfifo_used (rfifo_used),`
446			`.rst_n (rst_n)`
447			`);`
448
449
450			`//////////////// END SIMULATION-ONLY CONTENTS`
451
452			`//synthesis translate_on`
453			`//synthesis read_comments_as_HDL on`
454			`// scfifo rfifo`
455			`// (`
456			`// .aclr (fifo_clear),`
457			`// .clock (clk),`
458			`// .data (t_dat),`
459			`// .empty (fifo_EF),`
460			`// .full (rfifo_full),`
461			`// .q (fifo_rdata),`
462			`// .rdreq (fifo_rd),`
463			`// .usedw (rfifo_used),`
464			`// .wrreq (wr_rfifo)`
465			`// );`
466			`//`
467			`// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",`
468			`// rfifo.lpm_numwords = 64,`
469			`// rfifo.lpm_showahead = "OFF",`
470			`// rfifo.lpm_type = "scfifo",`
471			`// rfifo.lpm_width = 8,`
472			`// rfifo.lpm_widthu = 6,`
473			`// rfifo.overflow_checking = "OFF",`
474			`// rfifo.underflow_checking = "OFF",`
475			`// rfifo.use_eab = "ON";`
476			`//`
477			`//synthesis read_comments_as_HDL off`
478
479			`endmodule`
480
481
482			`// synthesis translate_off`
483			`timescale 1ns / 1ps
484			`// synthesis translate_on`
485
486			`// turn off superfluous verilog processor warnings`
487			`// altera message_level Level1`
488			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
489
490			`module qsys_jtag_uart_0 (`
491			`// inputs:`
492			`av_address,`
493			`av_chipselect,`
494			`av_read_n,`
495			`av_write_n,`
496			`av_writedata,`
497			`clk,`
498			`rst_n,`
499
500			`// outputs:`
501			`av_irq,`
502			`av_readdata,`
503			`av_waitrequest,`
504			`dataavailable,`
505			`readyfordata`
506			`)`
507			`/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;`
508
509			`output av_irq;`
510			`output [ 31: 0] av_readdata;`
511			`output av_waitrequest;`
512			`output dataavailable;`
513			`output readyfordata;`
514			`input av_address;`
515			`input av_chipselect;`
516			`input av_read_n;`
517			`input av_write_n;`
518			`input [ 31: 0] av_writedata;`
519			`input clk;`
520			`input rst_n;`
521
522			`reg ac;`
523			`wire activity;`
524			`wire av_irq;`
525			`wire [ 31: 0] av_readdata;`
526			`reg av_waitrequest;`
527			`reg dataavailable;`
528			`reg fifo_AE;`
529			`reg fifo_AF;`
530			`wire fifo_EF;`
531			`wire fifo_FF;`
532			`wire fifo_clear;`
533			`wire fifo_rd;`
534			`wire [ 7: 0] fifo_rdata;`
535			`wire [ 7: 0] fifo_wdata;`
536			`reg fifo_wr;`
537			`reg ien_AE;`
538			`reg ien_AF;`
539			`wire ipen_AE;`
540			`wire ipen_AF;`
541			`reg pause_irq;`
542			`wire [ 7: 0] r_dat;`
543			`wire r_ena;`
544			`reg r_val;`
545			`wire rd_wfifo;`
546			`reg read_0;`
547			`reg readyfordata;`
548			`wire rfifo_full;`
549			`wire [ 5: 0] rfifo_used;`
550			`reg rvalid;`
551			`reg sim_r_ena;`
552			`reg sim_t_dat;`
553			`reg sim_t_ena;`
554			`reg sim_t_pause;`
555			`wire [ 7: 0] t_dat;`
556			`reg t_dav;`
557			`wire t_ena;`
558			`wire t_pause;`
559			`wire wfifo_empty;`
560			`wire [ 5: 0] wfifo_used;`
561			`reg woverflow;`
562			`wire wr_rfifo;`
563			`//avalon_jtag_slave, which is an e_avalon_slave`
564			`assign rd_wfifo = r_ena & ~wfifo_empty;`
565			`assign wr_rfifo = t_ena & ~rfifo_full;`
566			`assign fifo_clear = ~rst_n;`
567			`qsys_jtag_uart_0_scfifo_w the_qsys_jtag_uart_0_scfifo_w`
568			`(`
569			`.clk (clk),`
570			`.fifo_FF (fifo_FF),`
571			`.fifo_clear (fifo_clear),`
572			`.fifo_wdata (fifo_wdata),`
573			`.fifo_wr (fifo_wr),`
574			`.r_dat (r_dat),`
575			`.rd_wfifo (rd_wfifo),`
576			`.wfifo_empty (wfifo_empty),`
577			`.wfifo_used (wfifo_used)`
578			`);`
579
580			`qsys_jtag_uart_0_scfifo_r the_qsys_jtag_uart_0_scfifo_r`
581			`(`
582			`.clk (clk),`
583			`.fifo_EF (fifo_EF),`
584			`.fifo_clear (fifo_clear),`
585			`.fifo_rd (fifo_rd),`
586			`.fifo_rdata (fifo_rdata),`
587			`.rfifo_full (rfifo_full),`
588			`.rfifo_used (rfifo_used),`
589			`.rst_n (rst_n),`
590			`.t_dat (t_dat),`
591			`.wr_rfifo (wr_rfifo)`
592			`);`
593
594			`assign ipen_AE = ien_AE & fifo_AE;`
595			`assign ipen_AF = ien_AF & (pause_irq \| fifo_AF);`
596			`assign av_irq = ipen_AE \| ipen_AF;`
597			`assign activity = t_pause \| t_ena;`
598			`always @(posedge clk or negedge rst_n)`
599			`begin`
600			`if (rst_n == 0)`
601			`pause_irq <= 1'b0;`
602			`else // only if fifo is not empty...`
603			`if (t_pause & ~fifo_EF)`
604			`pause_irq <= 1'b1;`
605			`else if (read_0)`
606			`pause_irq <= 1'b0;`
607			`end`
608
609
610			`always @(posedge clk or negedge rst_n)`
611			`begin`
612			`if (rst_n == 0)`
613			`begin`
614			`r_val <= 1'b0;`
615			`t_dav <= 1'b1;`
616			`end`
617			`else`
618			`begin`
619			`r_val <= r_ena & ~wfifo_empty;`
620			`t_dav <= ~rfifo_full;`
621			`end`
622			`end`
623
624
625			`always @(posedge clk or negedge rst_n)`
626			`begin`
627			`if (rst_n == 0)`
628			`begin`
629			`fifo_AE <= 1'b0;`
630			`fifo_AF <= 1'b0;`
631			`fifo_wr <= 1'b0;`
632			`rvalid <= 1'b0;`
633			`read_0 <= 1'b0;`
634			`ien_AE <= 1'b0;`
635			`ien_AF <= 1'b0;`
636			`ac <= 1'b0;`
637			`woverflow <= 1'b0;`
638			`av_waitrequest <= 1'b1;`
639			`end`
640			`else`
641			`begin`
642			`fifo_AE <= {fifo_FF,wfifo_used} <= 8;`
643			`fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;`
644			`fifo_wr <= 1'b0;`
645			`read_0 <= 1'b0;`
646			`av_waitrequest <= ~(av_chipselect & (~av_write_n \| ~av_read_n) & av_waitrequest);`
647			`if (activity)`
648			`ac <= 1'b1;`
649			`// write`
650			`if (av_chipselect & ~av_write_n & av_waitrequest)`
651			`// addr 1 is control; addr 0 is data`
652			`if (av_address)`
653			`begin`
654			`ien_AF <= av_writedata[0];`
655			`ien_AE <= av_writedata[1];`
656			`if (av_writedata[10] & ~activity)`
657			`ac <= 1'b0;`
658			`end`
659			`else`
660			`begin`
661			`fifo_wr <= ~fifo_FF;`
662			`woverflow <= fifo_FF;`
663			`end`
664			`// read`
665			`if (av_chipselect & ~av_read_n & av_waitrequest)`
666			`begin`
667			`// addr 1 is interrupt; addr 0 is data`
668			`if (~av_address)`
669			`rvalid <= ~fifo_EF;`
670			`read_0 <= ~av_address;`
671			`end`
672			`end`
673			`end`
674
675
676			`assign fifo_wdata = av_writedata[7 : 0];`
677			`assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;`
678			`assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };`
679			`always @(posedge clk or negedge rst_n)`
680			`begin`
681			`if (rst_n == 0)`
682			`readyfordata <= 0;`
683			`else`
684			`readyfordata <= ~fifo_FF;`
685			`end`
686
687
688
689			`//synthesis translate_off`
690			`//////////////// SIMULATION-ONLY CONTENTS`
691			`// Tie off Atlantic Interface signals not used for simulation`
692			`always @(posedge clk)`
693			`begin`
694			`sim_t_pause <= 1'b0;`
695			`sim_t_ena <= 1'b0;`
696			`sim_t_dat <= t_dav ? r_dat : {8{r_val}};`
697			`sim_r_ena <= 1'b0;`
698			`end`
699
700
701			`assign r_ena = sim_r_ena;`
702			`assign t_ena = sim_t_ena;`
703			`assign t_dat = sim_t_dat;`
704			`assign t_pause = sim_t_pause;`
705			`always @(fifo_EF)`
706			`begin`
707			`dataavailable = ~fifo_EF;`
708			`end`
709
710
711
712			`//////////////// END SIMULATION-ONLY CONTENTS`
713
714			`//synthesis translate_on`
715			`//synthesis read_comments_as_HDL on`
716			`// alt_jtag_atlantic qsys_jtag_uart_0_alt_jtag_atlantic`
717			`// (`
718			`// .clk (clk),`
719			`// .r_dat (r_dat),`
720			`// .r_ena (r_ena),`
721			`// .r_val (r_val),`
722			`// .rst_n (rst_n),`
723			`// .t_dat (t_dat),`
724			`// .t_dav (t_dav),`
725			`// .t_ena (t_ena),`
726			`// .t_pause (t_pause)`
727			`// );`
728			`//`
729			`// defparam qsys_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,`
730			`// qsys_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,`
731			`// qsys_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,`
732			`// qsys_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";`
733			`//`
734			`// always @(posedge clk or negedge rst_n)`
735			`// begin`
736			`// if (rst_n == 0)`
737			`// dataavailable <= 0;`
738			`// else`
739			`// dataavailable <= ~fifo_EF;`
740			`// end`
741			`//`
742			`//`
743			`//synthesis read_comments_as_HDL off`
744
745			`endmodule`
746
747