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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_uart/] [pronoc_jtag_uart.old] - Blame information for rev 48

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/**************************************
* Module: pronoc_jtag_uart
* Date:2020-04-11
* Author: alireza
*
* Description:
***************************************/
`define DONT_CHECK_SIM
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
 
 
module  pronoc_jtag_uart #(
    //wb parameter
    parameter Aw           =   1,
    parameter SELw         =   4,
    parameter TAGw         =   3,
    parameter Dw           =   32,
    //uart parameter
    parameter BUFF_Aw      =   6,//max is 16
    //uart simulator param
    parameter SIM_BUFFER_SIZE=100,
    parameter SIM_WAIT_COUNT    =10000,
    //jtag parameter
    parameter JTAG_CONNECT= "XILINX_JTAG_WB",//"ALTERA_JTAG_WB" ,"XILINX_JTAG_WB"
    parameter JTAG_INDEX= 126,
    parameter JDw = 32,
    parameter JAw=32,
    parameter JINDEXw=8,
    parameter JSTATUSw=8,
    parameter J2WBw = (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1,
    parameter WB2Jw= (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw  : 1
 
)(
 //wb
  clk,
  reset,
 // wb_irq,
  wb_dat_o,
  wb_ack_o,
  wb_adr_i,
  wb_stb_i,
  wb_cyc_i,
  wb_we_i,
  wb_dat_i,
 
  //jtag
  wb_to_jtag,
  jtag_to_wb
);
 
    //wb
    input            clk;
    input            reset;
  //  output           wb_irq;
    output  [ Dw-1: 0] wb_dat_o;
    output           wb_ack_o;
    input            wb_adr_i;
    input            wb_stb_i;
    input            wb_cyc_i;
    input            wb_we_i;
    input   [ Dw-1: 0] wb_dat_i;
 
 
    //jtag
    output [WB2Jw-1  : 0] wb_to_jtag;
    input  [J2WBw-1 : 0] jtag_to_wb;
`ifndef DONT_CHECK_SIM
`ifdef MODEL_TECH
    `define RUN_SIM
`endif
`ifdef VERILATOR
    `define RUN_SIM
`endif
`endif
 
`ifdef  RUN_SIM
 
    altera_simulator_UART #(
        .BUFFER_SIZE(SIM_BUFFER_SIZE),
        .WAIT_COUNT(SIM_WAIT_COUNT)
    )
    Suart
    (
        .reset(reset),
        .clk(clk),
        .s_dat_i(wb_dat_i),
        .s_sel_i(4'b1111),
        .s_addr_i(wb_adr_i),
        .s_cti_i( ),
        .s_stb_i(wb_stb_i),
        .s_cyc_i(wb_cyc_i),
        .s_we_i(wb_we_i),
        .s_dat_o(wb_dat_o),
        .s_ack_o(wb_ack_o),
        .RxD_din(8'd0),
        .RxD_wr(8'd0),
        .RxD_ready( )
    );
 
 
`else
    pronoc_jtag_uart_hw #(
        .Aw(Aw),
        .SELw(SELw),
        .TAGw(TAGw),
        .Dw(Dw),
        .BUFF_Aw(BUFF_Aw),
        .JTAG_CONNECT(JTAG_CONNECT),
        .JTAG_INDEX(JTAG_INDEX),
        .JDw(JDw),
        .JAw(JAw),
        .JINDEXw(JINDEXw),
        .JSTATUSw(JSTATUSw),
        .J2WBw(J2WBw),
        .WB2Jw(WB2Jw)
    )
    uart_hw
    (
        .clk(clk),
        .reset(reset),
        .wb_dat_o(wb_dat_o),
        .wb_ack_o(wb_ack_o),
        .wb_adr_i(wb_adr_i),
        .wb_stb_i(wb_stb_i),
        .wb_cyc_i(wb_cyc_i),
        .wb_we_i(wb_we_i),
        .wb_dat_i(wb_dat_i),
        .wb_to_jtag(wb_to_jtag),
        .jtag_to_wb(jtag_to_wb)
    );
 
`endif
 
 
endmodule
 
 
 
 
 
 
 
 
module  pronoc_jtag_uart_hw #(
    //wb parameter
    parameter Aw           =   1,
    parameter SELw         =   4,
    parameter TAGw         =   3,
    parameter Dw           =   32,
    //uart parameter
    parameter BUFF_Aw      =   6,//max is 16
    //jtag parameter
    parameter JTAG_CONNECT= "XILINX_JTAG_WB",//"ALTERA_JTAG_WB" ,"XILINX_JTAG_WB"
    parameter JTAG_INDEX= 126,
    parameter JDw = 32,
    parameter JAw=32,
    parameter JINDEXw=8,
    parameter JSTATUSw=8,
    parameter J2WBw = (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1,
    parameter WB2Jw= (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw  : 1
 
)(
 //wb
  clk,
  reset,
 // wb_irq,
  wb_dat_o,
  wb_ack_o,
  wb_adr_i,
  wb_stb_i,
  wb_cyc_i,
  wb_we_i,
  wb_dat_i,
 
  //jtag
  wb_to_jtag,
  jtag_to_wb
 
 
);
 
    function integer log2;
      input integer number; begin
         log2=(number <=1) ? 1: 0;
         while(2**log2
            log2=log2+1;
         end
      end
    endfunction // log2
 
 
     //wb interface
    localparam
        DATA_REG = 1'b0,
        CONTROL_REG  = 1'b1 ,
        CONTROL_WSPACE_MSK = 32'hFFFF0000,
        DATA_RVALID_MSK = 32'h00008000,
        DATA_DATA_MSK = 32'h000000FF,
        B = 2 ** (BUFF_Aw-1),
        B_1 = B-1,
        Bw = log2(B),
        DEPTHw=log2(B+1);
 
 
    localparam  [Bw-1   :   0] Bint =   B_1[Bw-1    :   0];
 
    //wb
    input            clk;
    input            reset;
  //  output           wb_irq;
    output  reg[ Dw-1: 0] wb_dat_o;
    output    reg       wb_ack_o;
    input            wb_adr_i;
    input            wb_stb_i;
    input            wb_cyc_i;
    input            wb_we_i;
    input   [ Dw-1: 0] wb_dat_i;
 
 
    //jtag
    output [WB2Jw-1  : 0] wb_to_jtag;
    input  [J2WBw-1 : 0] jtag_to_wb;
 
 
 
 
    //control reg
    wire [31 : 0] ctrl_reg;
    reg  [15 : 0] wspace;    // The number of spaces available in the write FIFO.
    reg  [15 : 0] jtag_wspace;    // The number of spaces available in the jtag write FIFO.
 
    assign ctrl_reg [31 :16] = wspace;
 
    wire [7:0]  wb_to_fifo_dat,fifo_to_wb_dat,jtag_to_fifo_dat,fifo_to_jtag_dat;
    wire [BUFF_Aw-1: 0] wb_to_fifo_addr,jtag_to_fifo_addr;
 
 
    //wb_wr_jtag_rd
    reg [BUFF_Aw- 2      :   0] jtag_rd_ptr;
    reg [BUFF_Aw- 2      :   0] wb_wr_ptr;
    reg [BUFF_Aw -1      :   0] wb_to_jtag_depth;
    reg wb_to_fifo_we,fifo_to_wb_re;
    wire wb_fifo_full, wb_fifo_nearly_full, wb_fifo_empty;
 
    //jtag_wr_wb_rd
    reg [BUFF_Aw- 2      :   0] wb_rd_ptr;
    reg [BUFF_Aw- 2      :   0] jtag_wr_ptr;
    reg [BUFF_Aw -1      :   0] jtag_to_wb_depth;
    reg jtag_to_fifo_we,fifo_to_jtag_re;
    wire jtag_fifo_full, jtag_fifo_nearly_full, jtag_fifo_empty;
 
 
 
    wire [JSTATUSw-1 : 0] jtag_status_o;
    wire [JINDEXw-1 : 0] jtag_index_o;
    wire jtag_stb_i,jtag_we_i;
    wire [JDw-1 : 0] jtag_dat_i;
    wire [JDw-1 : 0] jtag_dat_o;
    wire [JAw-1 : 0] jtag_addr_i;
    reg jtag_ack_o;
    reg jtag_rdat_valid,wb_rdat_valid;
 
 
    reg wb_ack_o_next,jtag_ack_o_next;
 
 
    always @ (*) begin
        wb_ack_o_next =1'b0;
        wb_to_fifo_we =1'b0;
        fifo_to_jtag_re=1'b0;
        wb_dat_o[7:0]=fifo_to_wb_dat;
        wb_dat_o[15] = wb_rdat_valid;
        if(wb_stb_i & wb_we_i ) begin
                case(wb_adr_i)
                DATA_REG:begin
                    if(~wb_fifo_full)begin
                        wb_to_fifo_we=1'b1;
                        wb_ack_o_next =1'b1;
                    end
                end
                CONTROL_REG:begin
                    // set the bits of control reg. //TODO add intrrupt control registers
                    wb_ack_o_next =1'b1;
                end
                endcase
        end //sa_stb_i && sa_we_i
        if(wb_stb_i & ~wb_we_i ) begin
                case(wb_adr_i)
                DATA_REG:begin
                    wb_dat_o[7:0]=fifo_to_wb_dat;
                    wb_dat_o[15] = wb_rdat_valid;
                    wb_ack_o_next =1'b1;
                    if(~jtag_fifo_empty)begin
                        fifo_to_jtag_re=1'b1;
                    end
                end
                CONTROL_REG:begin
                    // read control reg
                     wb_dat_o = ctrl_reg;
                     wb_ack_o_next =1'b1;
                end
                endcase
        end
    end//always
 
    reg jtag_to_fifo_we_next;
 
    reg stb1,stb2;
    wire jtag_stb_valid = stb1 & ~stb2;// fix jtag clock diffrence
 
    always @(*) begin
        jtag_to_fifo_we_next=1'b0;
        jtag_ack_o_next =1'b0;
        fifo_to_wb_re=1'b0;
        if(jtag_stb_valid) begin
            if(~wb_fifo_empty) fifo_to_wb_re=1'b1;//make one cycle delay for wr enable
             jtag_ack_o_next =1'b1;
            if( ~jtag_fifo_full && jtag_to_fifo_dat[7:0]!=0) jtag_to_fifo_we_next=1'b1;
        end
 
    end
 
 
 
    always @ (posedge clk or posedge reset)begin
        if (reset) begin
            wb_ack_o<=1'b0;
            jtag_ack_o<=1'b0;
            jtag_to_fifo_we<=1'b0;
            stb1<=1'b0;
            stb2<=1'b0;
            jtag_rdat_valid<=1'b0;
        end else begin
            wb_ack_o<= wb_ack_o_next;
            jtag_ack_o<=jtag_ack_o_next;
            jtag_to_fifo_we<=jtag_to_fifo_we_next;
            stb1<=jtag_stb_i;
            stb2<=stb1;
 
            if(~wb_fifo_empty) jtag_rdat_valid<=1'b1;
            else if(jtag_ack_o ) jtag_rdat_valid<=1'b0;
 
            if(~jtag_fifo_empty) wb_rdat_valid<=1'b1;
            else if(wb_ack_o ) wb_rdat_valid<=1'b0;
 
        end
    end
 
 
 
    assign wb_to_fifo_dat = wb_dat_i [7:0];
 
    uart_dual_port_ram #(
        .Dw(8),
        .Aw(BUFF_Aw)
    )
    uart_ram
    (
        //wb_to_jtag
        .data_a(wb_to_fifo_dat),
        .addr_a(wb_to_fifo_addr),
        .we_a  (wb_to_fifo_we),
        .q_a   (fifo_to_wb_dat),
 
        //jtag_to_wb
        .data_b(jtag_to_fifo_dat),
        .addr_b(jtag_to_fifo_addr),
        .we_b  (jtag_to_fifo_we),
        .q_b   (fifo_to_jtag_dat),
 
        .clk   (clk)
    );
 
 
   generate
   if(JTAG_CONNECT == "XILINX_JTAG_WB")begin: xilinx_jwb
        assign wb_to_jtag = {jtag_status_o,jtag_ack_o,jtag_dat_o,jtag_index_o,clk};
        assign {jtag_addr_i,jtag_stb_i,jtag_we_i,jtag_dat_i} = jtag_to_wb;
   end else  if(JTAG_CONNECT == "AlTERA_JTAG_WB")begin: altera_jwb
 
        vjtag_wb #(
            .VJTAG_INDEX(JTAG_INDEX),
            .DW(JDw),
            .AW(JAw),
            .SW(JSTATUSw),
 
            //wishbone port parameters
            .M_Aw(Aw),
            .TAGw(TAGw)
        )
        vjtag_inst
        (
            .clk(clk),
            .reset(reset),
            .status_i(jtag_status_o),
             //wishbone master interface signals
            .m_sel_o(),
            .m_dat_o(jtag_dat_i),
            .m_addr_o(jtag_addr_i),
            .m_cti_o(),
            .m_stb_o(jtag_stb_i),
            .m_cyc_o(),
            .m_we_o(jtag_we_i),
            .m_dat_i(jtag_dat_o),
            .m_ack_i(jtag_ack_o)
 
        );
 
 
        assign wb_to_jtag[0] = clk;
   end
   endgenerate
 
    assign wb_to_fifo_addr = (wb_to_fifo_we) ? {1'b0,wb_wr_ptr} : {1'b1,wb_rd_ptr};
    assign jtag_to_fifo_addr = (jtag_to_fifo_we) ? {1'b1,jtag_wr_ptr} : {1'b0,jtag_rd_ptr};
    assign jtag_status_o=0;
    assign jtag_index_o = JTAG_INDEX;
    assign jtag_to_fifo_dat = jtag_dat_i[7:0];
    reg [7:0] jtag_rd_dat;
    always @(posedge clk)begin
        if(reset)begin
            jtag_rd_dat<=8'd0;
        end else if(fifo_to_wb_re & ~jtag_to_fifo_we)begin
            jtag_rd_dat<=fifo_to_jtag_dat;
        end
    end
    assign jtag_dat_o[23 : 0] = (jtag_rdat_valid)? {jtag_wspace,jtag_rd_dat} : {jtag_wspace,8'd0};
 
 
 
 
    /*************
     * FIFO pointers
     * ***********/
 
    //pointers update wb_wr_jtag_rd
    always @(posedge clk)
    begin
       if (reset) begin
          jtag_rd_ptr <= {Bw{1'b0}};
          wb_wr_ptr <= 0;
          wb_to_jtag_depth  <= {DEPTHw{1'b0}};
       end
       else begin
          if (wb_to_fifo_we) wb_wr_ptr <= (wb_wr_ptr==Bint)?   {Bw{1'b0}} : wb_wr_ptr + 1'b1;
          if (fifo_to_wb_re ) jtag_rd_ptr <= (jtag_rd_ptr==Bint)?   {Bw{1'b0}} : jtag_rd_ptr + 1'b1;
          if (wb_to_fifo_we & ~(fifo_to_wb_re )) wb_to_jtag_depth <=  wb_to_jtag_depth + 1'b1;
          else if (~wb_to_fifo_we & ( fifo_to_wb_re)) wb_to_jtag_depth <=    wb_to_jtag_depth - 1'b1;
       end
    end
 
    assign wb_fifo_full = wb_to_jtag_depth == B;
    assign wb_fifo_nearly_full = wb_to_jtag_depth >= B-1;
    assign wb_fifo_empty = wb_to_jtag_depth == {DEPTHw{1'b0}};
 
 
 
 
    //pointers update wb_rd_jtag_wr
    always @(posedge clk)
    begin
       if (reset) begin
          wb_rd_ptr <= {Bw{1'b0}};
          jtag_wr_ptr <= 0;
          jtag_to_wb_depth  <= {DEPTHw{1'b0}};
       end
       else begin
          if (jtag_to_fifo_we ) jtag_wr_ptr <= (jtag_wr_ptr==Bint)?   {Bw{1'b0}} : jtag_wr_ptr + 1'b1;
          if (fifo_to_jtag_re) wb_rd_ptr <= (wb_rd_ptr==Bint)?   {Bw{1'b0}} : wb_rd_ptr + 1'b1;
          if (jtag_to_fifo_we  & ~fifo_to_jtag_re) jtag_to_wb_depth <=  jtag_to_wb_depth + 1'b1;
          else if (~(jtag_to_fifo_we ) & fifo_to_jtag_re) jtag_to_wb_depth <=    jtag_to_wb_depth - 1'b1;
       end
    end
 
    assign jtag_fifo_full = jtag_to_wb_depth == B;
    assign jtag_fifo_nearly_full = jtag_to_wb_depth >= B-1;
    assign jtag_fifo_empty = jtag_to_wb_depth == {DEPTHw{1'b0}};
 
 
    wire  [BUFF_Aw -1      :   0] remain = B- wb_to_jtag_depth;
    wire  [BUFF_Aw -1      :   0] jtag_remain = B- jtag_to_wb_depth;
    always @(*)begin
        wspace = 16'd0;
        jtag_wspace=16'd0;
        wspace[BUFF_Aw-1 : 0] = remain;
        jtag_wspace[BUFF_Aw-1 : 0] = jtag_remain;
    end
 
 
endmodule
 
 
 
 
// Quartus II Verilog Template
// True Dual Port RAM with single clock
 
 
module uart_dual_port_ram
#(
    parameter Dw=8,
    parameter Aw=6
)
(
   data_a,
   data_b,
   addr_a,
   addr_b,
   we_a,
   we_b,
   clk,
   q_a,
   q_b
);
 
 
    input [(Dw-1):0] data_a, data_b;
    input [(Aw-1):0] addr_a, addr_b;
    input we_a, we_b, clk;
    output  reg [(Dw-1):0] q_a, q_b;
 
    // Declare the RAM variable
    reg [Dw-1:0] ram[2**Aw-1:0];
 
       // Port A
    always @ (posedge clk)
    begin
        if (we_a)
        begin
            ram[addr_a] <= data_a;
            q_a <= data_a;
        end
        else
        begin
            q_a <= ram[addr_a];
        end
    end
 
    // Port B
    always @ (posedge clk)
    begin
        if (we_b)
        begin
            ram[addr_b] <= data_b;
            q_b <= data_b;
        end
        else
        begin
            q_b <= ram[addr_b];
        end
    end
 
    // synthesis translate_off
 
 
    integer i;
    initial begin
       for (i=0; i<(2**Aw);i=i+1 ) ram[i] ="*";
    end
// synthesis translate_on
 
 
endmodule
 
 
 
 
 
 
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_uart/] [pronoc_jtag_uart.old] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`/**************************************`
2			`* Module: pronoc_jtag_uart`
3			`* Date:2020-04-11`
4			`* Author: alireza`
5			`*`
6			`* Description:`
7			`***************************************/`
8			`define DONT_CHECK_SIM
9
10			`// synthesis translate_off`
11			`timescale 1ns / 1ps
12			`// synthesis translate_on`
13
14
15
16			`module pronoc_jtag_uart #(`
17			`//wb parameter`
18			`parameter Aw = 1,`
19			`parameter SELw = 4,`
20			`parameter TAGw = 3,`
21			`parameter Dw = 32,`
22			`//uart parameter`
23			`parameter BUFF_Aw = 6,//max is 16`
24			`//uart simulator param`
25			`parameter SIM_BUFFER_SIZE=100,`
26			`parameter SIM_WAIT_COUNT =10000,`
27			`//jtag parameter`
28			`parameter JTAG_CONNECT= "XILINX_JTAG_WB",//"ALTERA_JTAG_WB" ,"XILINX_JTAG_WB"`
29			`parameter JTAG_INDEX= 126,`
30			`parameter JDw = 32,`
31			`parameter JAw=32,`
32			`parameter JINDEXw=8,`
33			`parameter JSTATUSw=8,`
34			`parameter J2WBw = (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1,`
35			`parameter WB2Jw= (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1`
36
37			`)(`
38			`//wb`
39			`clk,`
40			`reset,`
41			`// wb_irq,`
42			`wb_dat_o,`
43			`wb_ack_o,`
44			`wb_adr_i,`
45			`wb_stb_i,`
46			`wb_cyc_i,`
47			`wb_we_i,`
48			`wb_dat_i,`
49
50			`//jtag`
51			`wb_to_jtag,`
52			`jtag_to_wb`
53			`);`
54
55			`//wb`
56			`input clk;`
57			`input reset;`
58			`// output wb_irq;`
59			`output [ Dw-1: 0] wb_dat_o;`
60			`output wb_ack_o;`
61			`input wb_adr_i;`
62			`input wb_stb_i;`
63			`input wb_cyc_i;`
64			`input wb_we_i;`
65			`input [ Dw-1: 0] wb_dat_i;`
66
67
68			`//jtag`
69			`output [WB2Jw-1 : 0] wb_to_jtag;`
70			`input [J2WBw-1 : 0] jtag_to_wb;`
71			`ifndef DONT_CHECK_SIM
72			`ifdef MODEL_TECH
73			`define RUN_SIM
74			`endif
75			`ifdef VERILATOR
76			`define RUN_SIM
77			`endif
78			`endif
79
80			`ifdef RUN_SIM
81
82			`altera_simulator_UART #(`
83			`.BUFFER_SIZE(SIM_BUFFER_SIZE),`
84			`.WAIT_COUNT(SIM_WAIT_COUNT)`
85			`)`
86			`Suart`
87			`(`
88			`.reset(reset),`
89			`.clk(clk),`
90			`.s_dat_i(wb_dat_i),`
91			`.s_sel_i(4'b1111),`
92			`.s_addr_i(wb_adr_i),`
93			`.s_cti_i( ),`
94			`.s_stb_i(wb_stb_i),`
95			`.s_cyc_i(wb_cyc_i),`
96			`.s_we_i(wb_we_i),`
97			`.s_dat_o(wb_dat_o),`
98			`.s_ack_o(wb_ack_o),`
99			`.RxD_din(8'd0),`
100			`.RxD_wr(8'd0),`
101			`.RxD_ready( )`
102			`);`
103
104
105			`else
106			`pronoc_jtag_uart_hw #(`
107			`.Aw(Aw),`
108			`.SELw(SELw),`
109			`.TAGw(TAGw),`
110			`.Dw(Dw),`
111			`.BUFF_Aw(BUFF_Aw),`
112			`.JTAG_CONNECT(JTAG_CONNECT),`
113			`.JTAG_INDEX(JTAG_INDEX),`
114			`.JDw(JDw),`
115			`.JAw(JAw),`
116			`.JINDEXw(JINDEXw),`
117			`.JSTATUSw(JSTATUSw),`
118			`.J2WBw(J2WBw),`
119			`.WB2Jw(WB2Jw)`
120			`)`
121			`uart_hw`
122			`(`
123			`.clk(clk),`
124			`.reset(reset),`
125			`.wb_dat_o(wb_dat_o),`
126			`.wb_ack_o(wb_ack_o),`
127			`.wb_adr_i(wb_adr_i),`
128			`.wb_stb_i(wb_stb_i),`
129			`.wb_cyc_i(wb_cyc_i),`
130			`.wb_we_i(wb_we_i),`
131			`.wb_dat_i(wb_dat_i),`
132			`.wb_to_jtag(wb_to_jtag),`
133			`.jtag_to_wb(jtag_to_wb)`
134			`);`
135
136			`endif
137
138
139			`endmodule`
140
141
142
143
144
145
146
147
148			`module pronoc_jtag_uart_hw #(`
149			`//wb parameter`
150			`parameter Aw = 1,`
151			`parameter SELw = 4,`
152			`parameter TAGw = 3,`
153			`parameter Dw = 32,`
154			`//uart parameter`
155			`parameter BUFF_Aw = 6,//max is 16`
156			`//jtag parameter`
157			`parameter JTAG_CONNECT= "XILINX_JTAG_WB",//"ALTERA_JTAG_WB" ,"XILINX_JTAG_WB"`
158			`parameter JTAG_INDEX= 126,`
159			`parameter JDw = 32,`
160			`parameter JAw=32,`
161			`parameter JINDEXw=8,`
162			`parameter JSTATUSw=8,`
163			`parameter J2WBw = (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1,`
164			`parameter WB2Jw= (JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1`
165
166			`)(`
167			`//wb`
168			`clk,`
169			`reset,`
170			`// wb_irq,`
171			`wb_dat_o,`
172			`wb_ack_o,`
173			`wb_adr_i,`
174			`wb_stb_i,`
175			`wb_cyc_i,`
176			`wb_we_i,`
177			`wb_dat_i,`
178
179			`//jtag`
180			`wb_to_jtag,`
181			`jtag_to_wb`
182
183
184			`);`
185
186			`function integer log2;`
187			`input integer number; begin`
188			`log2=(number <=1) ? 1: 0;`
189			`while(2**log2`
190			`log2=log2+1;`
191			`end`
192			`end`
193			`endfunction // log2`
194
195
196			`//wb interface`
197			`localparam`
198			`DATA_REG = 1'b0,`
199			`CONTROL_REG = 1'b1 ,`
200			`CONTROL_WSPACE_MSK = 32'hFFFF0000,`
201			`DATA_RVALID_MSK = 32'h00008000,`
202			`DATA_DATA_MSK = 32'h000000FF,`
203			`B = 2 ** (BUFF_Aw-1),`
204			`B_1 = B-1,`
205			`Bw = log2(B),`
206			`DEPTHw=log2(B+1);`
207
208
209			`localparam [Bw-1 : 0] Bint = B_1[Bw-1 : 0];`
210
211			`//wb`
212			`input clk;`
213			`input reset;`
214			`// output wb_irq;`
215			`output reg[ Dw-1: 0] wb_dat_o;`
216			`output reg wb_ack_o;`
217			`input wb_adr_i;`
218			`input wb_stb_i;`
219			`input wb_cyc_i;`
220			`input wb_we_i;`
221			`input [ Dw-1: 0] wb_dat_i;`
222
223
224			`//jtag`
225			`output [WB2Jw-1 : 0] wb_to_jtag;`
226			`input [J2WBw-1 : 0] jtag_to_wb;`
227
228
229
230
231			`//control reg`
232			`wire [31 : 0] ctrl_reg;`
233			`reg [15 : 0] wspace; // The number of spaces available in the write FIFO.`
234			`reg [15 : 0] jtag_wspace; // The number of spaces available in the jtag write FIFO.`
235
236			`assign ctrl_reg [31 :16] = wspace;`
237
238			`wire [7:0] wb_to_fifo_dat,fifo_to_wb_dat,jtag_to_fifo_dat,fifo_to_jtag_dat;`
239			`wire [BUFF_Aw-1: 0] wb_to_fifo_addr,jtag_to_fifo_addr;`
240
241
242			`//wb_wr_jtag_rd`
243			`reg [BUFF_Aw- 2 : 0] jtag_rd_ptr;`
244			`reg [BUFF_Aw- 2 : 0] wb_wr_ptr;`
245			`reg [BUFF_Aw -1 : 0] wb_to_jtag_depth;`
246			`reg wb_to_fifo_we,fifo_to_wb_re;`
247			`wire wb_fifo_full, wb_fifo_nearly_full, wb_fifo_empty;`
248
249			`//jtag_wr_wb_rd`
250			`reg [BUFF_Aw- 2 : 0] wb_rd_ptr;`
251			`reg [BUFF_Aw- 2 : 0] jtag_wr_ptr;`
252			`reg [BUFF_Aw -1 : 0] jtag_to_wb_depth;`
253			`reg jtag_to_fifo_we,fifo_to_jtag_re;`
254			`wire jtag_fifo_full, jtag_fifo_nearly_full, jtag_fifo_empty;`
255
256
257
258			`wire [JSTATUSw-1 : 0] jtag_status_o;`
259			`wire [JINDEXw-1 : 0] jtag_index_o;`
260			`wire jtag_stb_i,jtag_we_i;`
261			`wire [JDw-1 : 0] jtag_dat_i;`
262			`wire [JDw-1 : 0] jtag_dat_o;`
263			`wire [JAw-1 : 0] jtag_addr_i;`
264			`reg jtag_ack_o;`
265			`reg jtag_rdat_valid,wb_rdat_valid;`
266
267
268			`reg wb_ack_o_next,jtag_ack_o_next;`
269
270
271			`always @ (*) begin`
272			`wb_ack_o_next =1'b0;`
273			`wb_to_fifo_we =1'b0;`
274			`fifo_to_jtag_re=1'b0;`
275			`wb_dat_o[7:0]=fifo_to_wb_dat;`
276			`wb_dat_o[15] = wb_rdat_valid;`
277			`if(wb_stb_i & wb_we_i ) begin`
278			`case(wb_adr_i)`
279			`DATA_REG:begin`
280			`if(~wb_fifo_full)begin`
281			`wb_to_fifo_we=1'b1;`
282			`wb_ack_o_next =1'b1;`
283			`end`
284			`end`
285			`CONTROL_REG:begin`
286			`// set the bits of control reg. //TODO add intrrupt control registers`
287			`wb_ack_o_next =1'b1;`
288			`end`
289			`endcase`
290			`end //sa_stb_i && sa_we_i`
291			`if(wb_stb_i & ~wb_we_i ) begin`
292			`case(wb_adr_i)`
293			`DATA_REG:begin`
294			`wb_dat_o[7:0]=fifo_to_wb_dat;`
295			`wb_dat_o[15] = wb_rdat_valid;`
296			`wb_ack_o_next =1'b1;`
297			`if(~jtag_fifo_empty)begin`
298			`fifo_to_jtag_re=1'b1;`
299			`end`
300			`end`
301			`CONTROL_REG:begin`
302			`// read control reg`
303			`wb_dat_o = ctrl_reg;`
304			`wb_ack_o_next =1'b1;`
305			`end`
306			`endcase`
307			`end`
308			`end//always`
309
310			`reg jtag_to_fifo_we_next;`
311
312			`reg stb1,stb2;`
313			`wire jtag_stb_valid = stb1 & ~stb2;// fix jtag clock diffrence`
314
315			`always @(*) begin`
316			`jtag_to_fifo_we_next=1'b0;`
317			`jtag_ack_o_next =1'b0;`
318			`fifo_to_wb_re=1'b0;`
319			`if(jtag_stb_valid) begin`
320			`if(~wb_fifo_empty) fifo_to_wb_re=1'b1;//make one cycle delay for wr enable`
321			`jtag_ack_o_next =1'b1;`
322			`if( ~jtag_fifo_full && jtag_to_fifo_dat[7:0]!=0) jtag_to_fifo_we_next=1'b1;`
323			`end`
324
325			`end`
326
327
328
329			`always @ (posedge clk or posedge reset)begin`
330			`if (reset) begin`
331			`wb_ack_o<=1'b0;`
332			`jtag_ack_o<=1'b0;`
333			`jtag_to_fifo_we<=1'b0;`
334			`stb1<=1'b0;`
335			`stb2<=1'b0;`
336			`jtag_rdat_valid<=1'b0;`
337			`end else begin`
338			`wb_ack_o<= wb_ack_o_next;`
339			`jtag_ack_o<=jtag_ack_o_next;`
340			`jtag_to_fifo_we<=jtag_to_fifo_we_next;`
341			`stb1<=jtag_stb_i;`
342			`stb2<=stb1;`
343
344			`if(~wb_fifo_empty) jtag_rdat_valid<=1'b1;`
345			`else if(jtag_ack_o ) jtag_rdat_valid<=1'b0;`
346
347			`if(~jtag_fifo_empty) wb_rdat_valid<=1'b1;`
348			`else if(wb_ack_o ) wb_rdat_valid<=1'b0;`
349
350			`end`
351			`end`
352
353
354
355			`assign wb_to_fifo_dat = wb_dat_i [7:0];`
356
357			`uart_dual_port_ram #(`
358			`.Dw(8),`
359			`.Aw(BUFF_Aw)`
360			`)`
361			`uart_ram`
362			`(`
363			`//wb_to_jtag`
364			`.data_a(wb_to_fifo_dat),`
365			`.addr_a(wb_to_fifo_addr),`
366			`.we_a (wb_to_fifo_we),`
367			`.q_a (fifo_to_wb_dat),`
368
369			`//jtag_to_wb`
370			`.data_b(jtag_to_fifo_dat),`
371			`.addr_b(jtag_to_fifo_addr),`
372			`.we_b (jtag_to_fifo_we),`
373			`.q_b (fifo_to_jtag_dat),`
374
375			`.clk (clk)`
376			`);`
377
378
379			`generate`
380			`if(JTAG_CONNECT == "XILINX_JTAG_WB")begin: xilinx_jwb`
381			`assign wb_to_jtag = {jtag_status_o,jtag_ack_o,jtag_dat_o,jtag_index_o,clk};`
382			`assign {jtag_addr_i,jtag_stb_i,jtag_we_i,jtag_dat_i} = jtag_to_wb;`
383			`end else if(JTAG_CONNECT == "AlTERA_JTAG_WB")begin: altera_jwb`
384
385			`vjtag_wb #(`
386			`.VJTAG_INDEX(JTAG_INDEX),`
387			`.DW(JDw),`
388			`.AW(JAw),`
389			`.SW(JSTATUSw),`
390
391			`//wishbone port parameters`
392			`.M_Aw(Aw),`
393			`.TAGw(TAGw)`
394			`)`
395			`vjtag_inst`
396			`(`
397			`.clk(clk),`
398			`.reset(reset),`
399			`.status_i(jtag_status_o),`
400			`//wishbone master interface signals`
401			`.m_sel_o(),`
402			`.m_dat_o(jtag_dat_i),`
403			`.m_addr_o(jtag_addr_i),`
404			`.m_cti_o(),`
405			`.m_stb_o(jtag_stb_i),`
406			`.m_cyc_o(),`
407			`.m_we_o(jtag_we_i),`
408			`.m_dat_i(jtag_dat_o),`
409			`.m_ack_i(jtag_ack_o)`
410
411			`);`
412
413
414			`assign wb_to_jtag[0] = clk;`
415			`end`
416			`endgenerate`
417
418			`assign wb_to_fifo_addr = (wb_to_fifo_we) ? {1'b0,wb_wr_ptr} : {1'b1,wb_rd_ptr};`
419			`assign jtag_to_fifo_addr = (jtag_to_fifo_we) ? {1'b1,jtag_wr_ptr} : {1'b0,jtag_rd_ptr};`
420			`assign jtag_status_o=0;`
421			`assign jtag_index_o = JTAG_INDEX;`
422			`assign jtag_to_fifo_dat = jtag_dat_i[7:0];`
423			`reg [7:0] jtag_rd_dat;`
424			`always @(posedge clk)begin`
425			`if(reset)begin`
426			`jtag_rd_dat<=8'd0;`
427			`end else if(fifo_to_wb_re & ~jtag_to_fifo_we)begin`
428			`jtag_rd_dat<=fifo_to_jtag_dat;`
429			`end`
430			`end`
431			`assign jtag_dat_o[23 : 0] = (jtag_rdat_valid)? {jtag_wspace,jtag_rd_dat} : {jtag_wspace,8'd0};`
432
433
434
435
436			`/*************`
437			`* FIFO pointers`
438			`* ***********/`
439
440			`//pointers update wb_wr_jtag_rd`
441			`always @(posedge clk)`
442			`begin`
443			`if (reset) begin`
444			`jtag_rd_ptr <= {Bw{1'b0}};`
445			`wb_wr_ptr <= 0;`
446			`wb_to_jtag_depth <= {DEPTHw{1'b0}};`
447			`end`
448			`else begin`
449			`if (wb_to_fifo_we) wb_wr_ptr <= (wb_wr_ptr==Bint)? {Bw{1'b0}} : wb_wr_ptr + 1'b1;`
450			`if (fifo_to_wb_re ) jtag_rd_ptr <= (jtag_rd_ptr==Bint)? {Bw{1'b0}} : jtag_rd_ptr + 1'b1;`
451			`if (wb_to_fifo_we & ~(fifo_to_wb_re )) wb_to_jtag_depth <= wb_to_jtag_depth + 1'b1;`
452			`else if (~wb_to_fifo_we & ( fifo_to_wb_re)) wb_to_jtag_depth <= wb_to_jtag_depth - 1'b1;`
453			`end`
454			`end`
455
456			`assign wb_fifo_full = wb_to_jtag_depth == B;`
457			`assign wb_fifo_nearly_full = wb_to_jtag_depth >= B-1;`
458			`assign wb_fifo_empty = wb_to_jtag_depth == {DEPTHw{1'b0}};`
459
460
461
462
463			`//pointers update wb_rd_jtag_wr`
464			`always @(posedge clk)`
465			`begin`
466			`if (reset) begin`
467			`wb_rd_ptr <= {Bw{1'b0}};`
468			`jtag_wr_ptr <= 0;`
469			`jtag_to_wb_depth <= {DEPTHw{1'b0}};`
470			`end`
471			`else begin`
472			`if (jtag_to_fifo_we ) jtag_wr_ptr <= (jtag_wr_ptr==Bint)? {Bw{1'b0}} : jtag_wr_ptr + 1'b1;`
473			`if (fifo_to_jtag_re) wb_rd_ptr <= (wb_rd_ptr==Bint)? {Bw{1'b0}} : wb_rd_ptr + 1'b1;`
474			`if (jtag_to_fifo_we & ~fifo_to_jtag_re) jtag_to_wb_depth <= jtag_to_wb_depth + 1'b1;`
475			`else if (~(jtag_to_fifo_we ) & fifo_to_jtag_re) jtag_to_wb_depth <= jtag_to_wb_depth - 1'b1;`
476			`end`
477			`end`
478
479			`assign jtag_fifo_full = jtag_to_wb_depth == B;`
480			`assign jtag_fifo_nearly_full = jtag_to_wb_depth >= B-1;`
481			`assign jtag_fifo_empty = jtag_to_wb_depth == {DEPTHw{1'b0}};`
482
483
484			`wire [BUFF_Aw -1 : 0] remain = B- wb_to_jtag_depth;`
485			`wire [BUFF_Aw -1 : 0] jtag_remain = B- jtag_to_wb_depth;`
486			`always @(*)begin`
487			`wspace = 16'd0;`
488			`jtag_wspace=16'd0;`
489			`wspace[BUFF_Aw-1 : 0] = remain;`
490			`jtag_wspace[BUFF_Aw-1 : 0] = jtag_remain;`
491			`end`
492
493
494			`endmodule`
495
496
497
498
499			`// Quartus II Verilog Template`
500			`// True Dual Port RAM with single clock`
501
502
503			`module uart_dual_port_ram`
504			`#(`
505			`parameter Dw=8,`
506			`parameter Aw=6`
507			`)`
508			`(`
509			`data_a,`
510			`data_b,`
511			`addr_a,`
512			`addr_b,`
513			`we_a,`
514			`we_b,`
515			`clk,`
516			`q_a,`
517			`q_b`
518			`);`
519
520
521			`input [(Dw-1):0] data_a, data_b;`
522			`input [(Aw-1):0] addr_a, addr_b;`
523			`input we_a, we_b, clk;`
524			`output reg [(Dw-1):0] q_a, q_b;`
525
526			`// Declare the RAM variable`
527			`reg [Dw-1:0] ram[2**Aw-1:0];`
528
529			`// Port A`
530			`always @ (posedge clk)`
531			`begin`
532			`if (we_a)`
533			`begin`
534			`ram[addr_a] <= data_a;`
535			`q_a <= data_a;`
536			`end`
537			`else`
538			`begin`
539			`q_a <= ram[addr_a];`
540			`end`
541			`end`
542
543			`// Port B`
544			`always @ (posedge clk)`
545			`begin`
546			`if (we_b)`
547			`begin`
548			`ram[addr_b] <= data_b;`
549			`q_b <= data_b;`
550			`end`
551			`else`
552			`begin`
553			`q_b <= ram[addr_b];`
554			`end`
555			`end`
556
557			`// synthesis translate_off`
558
559
560			`integer i;`
561			`initial begin`
562			`for (i=0; i<(2*Aw);i=i+1 ) ram[i] ="";`
563			`end`
564			`// synthesis translate_on`
565
566
567			`endmodule`
568
569
570
571
572
573
574