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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_wb/] [jtag_source_probe.v] - Blame information for rev 48

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1 48 alirezamon 
 
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/**********************************************************************
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**      File:  jtag_source_probe.v
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**
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**
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**      Copyright (C) 2014-2017  Alireza Monemi
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**
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**      This file is part of ProNoC
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**
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**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
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**      you can redistribute it and/or modify it under the terms of the GNU
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**      Lesser General Public License as published by the Free Software Foundation,
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**      either version 2 of the License, or (at your option) any later version.
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**
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**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
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**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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**      Public License for more details.
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**
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**      You should have received a copy of the GNU Lesser General Public
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**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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**
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**
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**      Description:
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**      Jtag source probe which can be read/write using host PC
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**      C-based software located in src_c/jtag
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**              .
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**
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*******************************************************************/
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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module jtag_source_probe #(
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        parameter VJTAG_INDEX=127,
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         parameter Dw=2 //probe/probe width in bits
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)(
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        source,
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        probe
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);
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        input           [Dw-1   :0]  probe;
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        output  reg [Dw-1       :0]  source;
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        //vjtag vjtag signals declaration
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        wire    [2:0]  ir_out ,  ir_in;
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        wire      tdo, tck,       tdi;
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        wire      cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
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        vjtag   #(
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         .VJTAG_INDEX(VJTAG_INDEX)
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        )
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        vjtag_inst (
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        .ir_out ( ir_out ),
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        .tdo ( tdo ),
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        .ir_in ( ir_in ),
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        .tck ( tck ),
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        .tdi ( tdi ),
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        .virtual_state_cdr      ( cdr ),
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        .virtual_state_cir      ( cir ),
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        .virtual_state_e1dr     ( e1dr ),
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        .virtual_state_e2dr     ( e2dr ),
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        .virtual_state_pdr      ( pdr ),
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        .virtual_state_sdr      ( sdr ),
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        .virtual_state_udr      ( udr ),
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        .virtual_state_uir      ( uir )
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        );
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        // IR states
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        reg [2:0] ir;
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        reg bypass_reg;
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        reg [Dw-1       :       0] shift_buffer,shift_buffer_next;
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        reg cdr_delayed,sdr_delayed;
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        reg [Dw-1       :       0] source_next;//,status_next;
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        localparam BYPAS_ST= 3'b000,
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                                  SOURCE_ST=3'b001,
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                                  PROBE_ST =3'b010;
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        assign ir_out = ir_in;  // Just pass the IR out
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        assign tdo = (ir == BYPAS_ST) ? bypass_reg : shift_buffer[0];
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        always @(posedge tck )
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        begin
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                        if( uir ) ir <= ir_in; // Capture the instruction provided
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                        bypass_reg <= tdi;
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                        shift_buffer<=shift_buffer_next;
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                        source<=source_next;
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        end
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generate
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        if(Dw==1)begin :DW1
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                always @ (*)begin
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                        shift_buffer_next=shift_buffer;
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                        source_next = source;
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                        if( sdr ) shift_buffer_next= tdi; //,shift_buffer[DW-1:1]};// shift buffer
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                        case(ir)
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                        SOURCE_ST:begin
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                                if (cdr ) shift_buffer_next  = source;
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                                if (udr ) source_next = shift_buffer;
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                        end
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                        PROBE_ST:begin
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                                if (cdr ) shift_buffer_next  = probe;
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                        end
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                        default begin
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                                shift_buffer_next=shift_buffer;
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                                source_next = source;
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                        end
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                        endcase
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                end
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        end
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        else begin :DWB
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                always @ (*)begin
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                        shift_buffer_next=shift_buffer;
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                        source_next = source;
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                        if( sdr ) shift_buffer_next= {tdi, shift_buffer[Dw-1:1]};// shift buffer
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                        case(ir)
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                        SOURCE_ST:begin
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                                if (cdr ) shift_buffer_next  = source;
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                                if (udr ) source_next = shift_buffer ;
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                        end
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                        PROBE_ST:begin
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                                if (cdr ) shift_buffer_next  = probe;
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                        end
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                        default begin
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                                shift_buffer_next=shift_buffer;
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                                source_next = source;
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                        end
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                        endcase
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                end
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        end
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endgenerate
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endmodule
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