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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_wb/] [vjtag.v] - Blame information for rev 48

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1 48 alirezamon 
// megafunction wizard: %Virtual JTAG%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: sld_virtual_jtag
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// ============================================================
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// File Name: vjtag.v
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// Megafunction Name(s):
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//                      sld_virtual_jtag
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//
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// Simulation Library Files(s):
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//                      altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.0.0 Build 156 04/24/2013 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors.  Please refer to the
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//applicable agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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module vjtag #(
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        parameter  VJTAG_INDEX=126
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)(
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        ir_out,
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        tdo,
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        ir_in,
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        tck,
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        tdi,
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        virtual_state_cdr,
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        virtual_state_cir,
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        virtual_state_e1dr,
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        virtual_state_e2dr,
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        virtual_state_pdr,
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        virtual_state_sdr,
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        virtual_state_udr,
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        virtual_state_uir);
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        input   [2:0]  ir_out;
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        input     tdo;
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        output  [2:0]  ir_in;
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        output    tck;
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        output    tdi;
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        output    virtual_state_cdr;
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        output    virtual_state_cir;
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        output    virtual_state_e1dr;
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        output    virtual_state_e2dr;
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        output    virtual_state_pdr;
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        output    virtual_state_sdr;
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        output    virtual_state_udr;
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        output    virtual_state_uir;
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        wire  sub_wire0;
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        wire  sub_wire1;
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        wire [2:0] sub_wire2;
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        wire  sub_wire3;
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        wire  sub_wire4;
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        wire  sub_wire5;
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        wire  sub_wire6;
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        wire  sub_wire7;
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        wire  sub_wire8;
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        wire  sub_wire9;
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        wire  sub_wire10;
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        wire  virtual_state_cir = sub_wire0;
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        wire  virtual_state_pdr = sub_wire1;
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        wire [2:0] ir_in = sub_wire2[2:0];
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        wire  tdi = sub_wire3;
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        wire  virtual_state_udr = sub_wire4;
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        wire  tck = sub_wire5;
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        wire  virtual_state_e1dr = sub_wire6;
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        wire  virtual_state_uir = sub_wire7;
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        wire  virtual_state_cdr = sub_wire8;
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        wire  virtual_state_e2dr = sub_wire9;
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        wire  virtual_state_sdr = sub_wire10;
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`ifndef VERILATOR
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`ifndef MODEL_TECH
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        sld_virtual_jtag        sld_virtual_jtag_component (
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                                .ir_out (ir_out),
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                                .tdo (tdo),
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                                .virtual_state_cir (sub_wire0),
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                                .virtual_state_pdr (sub_wire1),
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                                .ir_in (sub_wire2),
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                                .tdi (sub_wire3),
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                                .virtual_state_udr (sub_wire4),
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                                .tck (sub_wire5),
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                                .virtual_state_e1dr (sub_wire6),
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                                .virtual_state_uir (sub_wire7),
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                                .virtual_state_cdr (sub_wire8),
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                                .virtual_state_e2dr (sub_wire9),
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                                .virtual_state_sdr (sub_wire10)
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                                // synopsys translate_off
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                                ,
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                                .jtag_state_cdr (),
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                                .jtag_state_cir (),
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                                .jtag_state_e1dr (),
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                                .jtag_state_e1ir (),
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                                .jtag_state_e2dr (),
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                                .jtag_state_e2ir (),
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                                .jtag_state_pdr (),
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                                .jtag_state_pir (),
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                                .jtag_state_rti (),
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                                .jtag_state_sdr (),
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                                .jtag_state_sdrs (),
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                                .jtag_state_sir (),
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                                .jtag_state_sirs (),
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                                .jtag_state_tlr (),
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                                .jtag_state_udr (),
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                                .jtag_state_uir (),
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                                .tms ()
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                                // synopsys translate_on
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                                );
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        defparam
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                sld_virtual_jtag_component.sld_auto_instance_index = "NO",
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                sld_virtual_jtag_component.sld_instance_index = VJTAG_INDEX,
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                sld_virtual_jtag_component.sld_ir_width = 3,
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                sld_virtual_jtag_component.sld_sim_action = "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))",
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                sld_virtual_jtag_component.sld_sim_n_scan = 8,
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                sld_virtual_jtag_component.sld_sim_total_length = 198;
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`endif //MODEL_TECH
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`endif //VERILATOR
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: show_jtag_state STRING "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
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// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "126"
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// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "3"
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// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "((0,1,7,3),(0,2,ff,20),(0,1,6,3),(0,2,ffffffff,20),(0,2,1,20),(0,2,2,20),(0,2,3,20),(0,2,4,20))"
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// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "8"
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// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "198"
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// Retrieval info: USED_PORT: ir_in 0 0 3 0 OUTPUT NODEFVAL "ir_in[2..0]"
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// Retrieval info: USED_PORT: ir_out 0 0 3 0 INPUT NODEFVAL "ir_out[2..0]"
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// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
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// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
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// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
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// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
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// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
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// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
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// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
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// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
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// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
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// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
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// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
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// Retrieval info: CONNECT: @ir_out 0 0 3 0 ir_out 0 0 3 0
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// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
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// Retrieval info: CONNECT: ir_in 0 0 3 0 @ir_in 0 0 3 0
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// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
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// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
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// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_bb.v TRUE
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// Retrieval info: LIB_FILE: altera_mf

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