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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_wb/] [vjtag_wb.v] - Blame information for rev 48

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Line No. Rev Author Line
1 48 alirezamon 
 
2 
// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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6 
 
7 
module vjtag_wb #(
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        parameter VJTAG_INDEX=126,
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        parameter DW=32,
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        parameter AW=32,
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        parameter SW=32,
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        //wishbone port parameters
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    parameter S_Aw          =   7,
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    parameter M_Aw          =   32,
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    parameter TAGw          =   3,
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    parameter SELw          =   4
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19 
 
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)(
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        clk,
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        reset,
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        status_i,
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         //wishbone master interface signals
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        m_sel_o,
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        m_dat_o,
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        m_addr_o,
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        m_cti_o,
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        m_stb_o,
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        m_cyc_o,
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        m_we_o,
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        m_dat_i,
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        m_ack_i
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);
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        //IO declaration
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        input reset,clk;
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        input [SW-1     :       0]       status_i;
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42 
        //wishbone master interface signals
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        output  [SELw-1          :   0] m_sel_o;
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        output  [DW-1            :   0] m_dat_o;
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        output  [M_Aw-1          :   0] m_addr_o;
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        output  [TAGw-1          :   0] m_cti_o;
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        output                          m_stb_o;
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        output                          m_cyc_o;
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        output                          m_we_o;
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        input   [DW-1           :  0]   m_dat_i;
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        input                           m_ack_i;
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53 
 
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        localparam STATE_NUM=3,
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                                  IDEAL =1,
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                                  WB_WR_DATA=2,
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                                  WB_RD_DATA=4;
58 
 
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        reg [STATE_NUM-1        :       0] ps,ns;
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        wire [DW-1      :0] data_out,  data_in;
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        wire  wb_wr_addr_en,  wb_wr_data_en,    wb_rd_data_en;
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        reg wr_mem_en,  rd_mem_en,  wb_cap_rd;
64 
 
65 
        reg [AW-1       :       0]       wb_addr,wb_addr_next;
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        reg [DW-1       :       0]       wb_wr_data,wb_rd_data;
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        reg wb_addr_inc;
68 
 
69 
 
70 
        assign  m_cti_o         =    3'b000;
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        assign  m_sel_o         =   4'b1111;
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        assign  m_cyc_o                         =       m_stb_o;
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        assign  m_stb_o                 = wr_mem_en |  rd_mem_en;
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        assign  m_we_o                          = wr_mem_en;
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        assign  m_dat_o                 = wb_wr_data;
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        assign  m_addr_o                        = wb_addr;
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        assign  data_in                         = wb_rd_data;
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//vjtag vjtag signals declaration
79 
 
80 
 
81 
localparam VJ_DW= (DW > AW)? DW : AW;
82 
 
83 
 
84 
        vjtag_ctrl #(
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                .DW(VJ_DW),
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                .VJTAG_INDEX(VJTAG_INDEX),
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                .STW(SW)
88 
        )
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        vjtag_ctrl_inst
90 
        (
91 
                .clk(clk),
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                .reset(reset),
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                .data_out(data_out),
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                .data_in(data_in),
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                .wb_wr_addr_en(wb_wr_addr_en),
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                .wb_wr_data_en(wb_wr_data_en),
97 
                .wb_rd_data_en(wb_rd_data_en),
98 
                .status_i(status_i)
99 
        );
100 
 
101 
 
102 
 
103 
`ifdef SYNC_RESET_MODE
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    always @ (posedge clk )begin
105 
`else
106 
    always @ (posedge clk or posedge reset)begin
107 
`endif
108 
                if(reset) begin
109 
                        wb_addr <= {AW{1'b0}};
110 
                        wb_wr_data  <= {DW{1'b0}};
111 
                        ps <= IDEAL;
112 
                end else begin
113 
                        wb_addr <= wb_addr_next;
114 
                        ps <= ns;
115 
                        if(wb_wr_data_en) wb_wr_data  <= data_out;
116 
                        if(wb_cap_rd) wb_rd_data <= m_dat_i;
117 
                end
118 
        end
119 
 
120 
 
121 
        always @(*)begin
122 
                wb_addr_next= wb_addr;
123 
                if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 :       0];
124 
                else if (wb_addr_inc)  wb_addr_next = wb_addr +1'b1;
125 
        end
126 
 
127 
 
128 
 
129 
        always @(*)begin
130 
                ns=ps;
131 
                wr_mem_en =1'b0;
132 
                rd_mem_en =1'b0;
133 
                wb_addr_inc=1'b0;
134 
                wb_cap_rd=1'b0;
135 
                case(ps)
136 
                IDEAL : begin
137 
                        if(wb_wr_data_en) ns= WB_WR_DATA;
138 
                        if(wb_rd_data_en) ns= WB_RD_DATA;
139 
                end
140 
                WB_WR_DATA: begin
141 
                        wr_mem_en =1'b1;
142 
                        if(m_ack_i) begin
143 
                                ns=IDEAL;
144 
                                wb_addr_inc=1'b1;
145 
                        end
146 
                end
147 
                WB_RD_DATA: begin
148 
                        rd_mem_en =1'b1;
149 
                        if(m_ack_i) begin
150 
                                wb_cap_rd=1'b1;
151 
                                ns=IDEAL;
152 
                                //wb_addr_inc=1'b1;
153 
                        end
154 
                end
155 
                endcase
156 
        end
157 
 
158 
        //assign led={wb_addr[7:0], wb_wr_data[7:0]};
159 
 
160 
endmodule
161 
 
162 
 
163 
 
164 
 
165 
module vjtag_ctrl #(
166 
        parameter DW=32,
167 
        parameter STW=2, // status width <= DW
168 
        parameter VJTAG_INDEX=126
169 
 
170 
)(
171 
        clk,
172 
        reset,
173 
        data_out,
174 
        data_in,
175 
        status_i,
176 
        wb_wr_addr_en,
177 
        wb_wr_data_en,
178 
        wb_rd_data_en
179 
);
180 
 
181 
//IO declaration
182 
        input reset,clk;
183 
        output [DW-1    :0] data_out;
184 
        input [DW-1     :0] data_in;
185 
        input [STW-1    :0] status_i;
186 
        output wb_wr_addr_en, wb_wr_data_en,    wb_rd_data_en;
187 
 
188 
 
189 
//vjtag vjtag signals declaration
190 
        wire    [2:0]  ir_out ,  ir_in;
191 
        wire      tdo, tck,       tdi;
192 
        wire      cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
193 
 
194 
 
195 
        vjtag   #(
196 
         .VJTAG_INDEX(VJTAG_INDEX)
197 
        )
198 
        vjtag_inst (
199 
        .ir_out ( ir_out ),
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        .tdo ( tdo ),
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        .ir_in ( ir_in ),
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        .tck ( tck ),
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        .tdi ( tdi ),
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        .virtual_state_cdr      ( cdr ),
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        .virtual_state_cir      ( cir ),
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        .virtual_state_e1dr     ( e1dr ),
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        .virtual_state_e2dr     ( e2dr ),
208 
        .virtual_state_pdr      ( pdr ),
209 
        .virtual_state_sdr      ( sdr ),
210 
        .virtual_state_udr      ( udr ),
211 
        .virtual_state_uir      ( uir )
212 
        );
213 
 
214 
 
215 
        // IR states
216 
        localparam [2:0]                           UPDATE_WB_ADDR  = 3'b111,
217 
                                                  UPDATE_WB_WR_DATA  = 3'b110,
218 
                                                  UPDATE_WB_RD_DATA  = 3'b101,
219 
                                                  RD_STATUS          =3'b100,
220 
                                                  BYPASS = 3'b000;
221 
 
222 
 
223 
        // internal registers
224 
        reg [2:0] ir;
225 
        reg bypass_reg;
226 
        reg [DW-1       :       0] shift_buffer,shift_buffer_next;
227 
        reg cdr_delayed,sdr_delayed;
228 
 
229 
 
230 
 
231 
        /*
232 
        always @(negedge tck)
233 
        begin
234 
                //  Delay the CDR signal by one half clock cycle
235 
                cdr_delayed = cdr;
236 
                sdr_delayed = sdr;
237 
        end
238 
        */
239 
 
240 
        assign ir_out = ir_in;  // Just pass the IR out
241 
        assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];
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        assign data_out = shift_buffer;
243 
 
244 
 
245 
`ifdef SYNC_RESET_MODE
246 
    always @ (posedge tck )begin
247 
`else
248 
    always @ (posedge tck or posedge reset)begin
249 
`endif
250 
 
251 
                if (reset)begin
252 
                        ir <= 3'b000;
253 
                        bypass_reg<=1'b0;
254 
                        shift_buffer<={DW{1'b0}};
255 
 
256 
                end else begin
257 
                        if( uir ) ir <= ir_in; // Capture the instruction provided
258 
                        bypass_reg <= tdi;
259 
                        shift_buffer<=shift_buffer_next;
260 
 
261 
                end
262 
        end
263 
 
264 
 
265 
 
266 
        always @ (*)begin
267 
                shift_buffer_next=shift_buffer;
268 
 
269 
                if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer
270 
                case(ir)
271 
                        RD_STATUS:begin
272 
                                if( cdr ) shift_buffer_next[STW-1       :       0] = status_i;
273 
                        end
274 
                        default: begin
275 
                                if( cdr ) shift_buffer_next = data_in;
276 
                        end
277 
                endcase
278 
        end
279 
 
280 
 
281 
 
282 
        reg wb_wr_addr1,        wb_wr_data1,    wb_rd_data1;
283 
        //always @(posedge tck or posedge reset)
284 
        always @(*)
285 
        begin
286 
                //if( reset )   begin
287 
                //      wb_wr_addr1<=1'b0;
288 
                //      wb_wr_data1<=1'b0;
289 
                //end else begin
290 
                        wb_wr_addr1=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) &  udr;
291 
                        wb_wr_data1=(ir== UPDATE_WB_WR_DATA &&  udr );
292 
                        wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr);
293 
                //end
294 
        end
295 
 
296 
        reg wb_wr_addr2,        wb_wr_data2,    wb_rd_data2;
297 
        reg wb_wr_addr3,        wb_wr_data3,    wb_rd_data3;
298 
 
299 
`ifdef SYNC_RESET_MODE
300 
    always @ (posedge clk )begin
301 
`else
302 
    always @ (posedge clk or posedge reset)begin
303 
`endif
304 
                if( reset )     begin
305 
                        wb_wr_addr2<=1'b0;
306 
                        wb_wr_data2<=1'b0;
307 
                        wb_wr_addr3<=1'b0;
308 
                        wb_wr_data3<=1'b0;
309 
                        wb_rd_data2<=1'b0;
310 
                        wb_rd_data3<=1'b0;
311 
                end else begin
312 
                        wb_wr_addr2<=wb_wr_addr1;
313 
                        wb_wr_data2<=wb_wr_data1;
314 
                        wb_wr_addr3<=wb_wr_addr2;
315 
                        wb_wr_data3<=wb_wr_data2;
316 
                        wb_rd_data2<=wb_rd_data1;
317 
                        wb_rd_data3<=wb_rd_data2;
318 
                end
319 
        end
320 
 
321 
        assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3);
322 
        assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3);
323 
        assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3);
324 
endmodule
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