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/**********************************************************************
**  File:  xilinx_jtag_wb.v
**
**
**  Copyright (C) 2020  Alireza Monemi
**
**  This file is part of ProNoC
**
**  ProNoC ( stands for Prototype Network-on-chip)  is free software:
**  you can redistribute it and/or modify it under the terms of the GNU
**  Lesser General Public License as published by the Free Software Foundation,
**  either version 2 of the License, or (at your option) any later version.
**
**  ProNoC is distributed in the hope that it will be useful, but WITHOUT
**  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**  Public License for more details.
**
**  You should have received a copy of the GNU Lesser General Public
**  License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**  Description:
**  xilinx bscan chain to wishbon bus interface. It prvide simple read/write on
**  whishbone bus. Does not support burst transaction.
**
*******************************************************************/
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
module xilinx_jtag_wb #(
    parameter JTAG_CHAIN=4, // Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4
    parameter JWB_NUM=1,
    parameter JDw=32,
    parameter JAw=32,
    parameter JINDEXw=8,
    parameter JSTATUSw=8,
    parameter CTRL_REG_INDEX =127
 
)(
   // clk, get the clock from wb interface
    reset,
    cpu_en,
    system_reset,
    wb_to_jtag_all,
    jtag_to_wb_all
);
 
     function integer log2;
      input integer number; begin
         log2=(number <=1) ? 1: 0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
    endfunction // log2 
 
    localparam  J2WBw= 1+1+JDw+JAw;
    localparam  WB2Jw=1+JSTATUSw+JINDEXw+1+JDw;
 
    input reset;//,clk;
    output reg cpu_en, system_reset;
 
   // output [7: 0 ] out;
 
    input [JWB_NUM*WB2Jw-1  : 0] wb_to_jtag_all;
    output[JWB_NUM*J2WBw-1 : 0] jtag_to_wb_all;
 
    wire  [J2WBw-1  : 0] jtag_to_wb [JWB_NUM-1 : 0];
    wire  [WB2Jw-1  : 0] wb_to_jtag [JWB_NUM-1 : 0];
    wire  [JINDEXw-1 : 0] wb_to_jtag_index_all[JWB_NUM-1 : 0];
    //wire  [JDw-1 : 0] wb_to_jtag_dat_all [JWB_NUM-1 : 0];
    wire  [JDw*JWB_NUM-1 : 0] wb_to_jtag_dat_all;
    wire  [JDw*JWB_NUM-1 : 0] wb_to_jtag_dat_all_latched;
    wire  [JWB_NUM-1 : 0] wb_to_jtag_ack_all;
    wire  [JWB_NUM-1 : 0] wb_to_jtag_ack_all_latched;
    wire  [JSTATUSw-1 : 0] wb_to_jtag_status_all [JWB_NUM-1 : 0];
 
    wire  [JINDEXw-1 : 0] jtag_to_wb_index;
    wire  [JWB_NUM-1: 0] jtag_sel_onehot;
    wire  [WB2Jw-1  : 0] wb_to_jtag_mux;
    wire  [JWB_NUM-1: 0] stb_all;
 
    wire [JSTATUSw-1    : 0] wb_to_jtag_status;
    wire [JDw-1 : 0] wb_to_jtag_dat;
    wire wb_to_jtag_ack;
 
    wire [JDw-1 : 0] jtag_to_wb_dat;
    wire [JAw-1 : 0] jtag_to_wb_addr;
    reg  [JAw-1 : 0] jtag_to_wb_addr_reg;
    wire jtag_to_wb_stb;
    wire jtag_to_wb_we;
    wire [JWB_NUM-1 : 0] wb_to_jtag_clk;
 
    wire tclk;//jtag clk
    wire clk = wb_to_jtag_clk[0];
 
    wire [JWB_NUM-1 : 0] stb_masked_all;
 
    reg  [JDw-1 : 0] jtag_dat_in_reg  [JWB_NUM-1: 0];
 
    reg jtag_to_wb_stb_reg;
    reg [JWB_NUM-1: 0] jtag_sel_onehot_reg;
    reg jtag_to_wb_we_reg;
 
    genvar i;
    generate
        for (i = 0; i < JWB_NUM ; i = i + 1) begin : block
 
            assign  wb_to_jtag[i]  = wb_to_jtag_all [(i+1)*WB2Jw-1 : i*WB2Jw];
            assign  {wb_to_jtag_status_all[i],wb_to_jtag_ack_all[i],wb_to_jtag_dat_all[(i+1)*JDw-1 : i*JDw],wb_to_jtag_index_all [i],wb_to_jtag_clk[i]}  = wb_to_jtag[i];
            assign  jtag_sel_onehot[i] = (wb_to_jtag_index_all [i] == jtag_to_wb_index);
            assign  stb_all[i] = jtag_to_wb_stb_reg & jtag_sel_onehot_reg[i];
            assign  jtag_to_wb_all[(i+1)*J2WBw-1 : i*J2WBw] =jtag_to_wb[i];
            assign  stb_masked_all[i] = stb_all[i] ; // & ~wb_to_jtag_ack_all_latched[i];
            assign  jtag_to_wb[i] = {jtag_to_wb_addr_reg,stb_masked_all[i],jtag_to_wb_we_reg,jtag_to_wb_dat};
 
            always @ (posedge clk)begin
                if ( wb_to_jtag_ack_all[i] & jtag_sel_onehot_reg[i] & ~jtag_to_wb_we) jtag_dat_in_reg[i] <= wb_to_jtag_dat_all[(i+1)*JDw-1 : i*JDw];
            end
            assign wb_to_jtag_dat_all_latched [(i+1)*JDw-1 : i*JDw] = jtag_dat_in_reg[i];
 
            wb_to_jtag_latch ack_latch
                (
                .clk(clk),
                .jtag_clk(tclk),
                .in(wb_to_jtag_ack_all[i]),
                .out(wb_to_jtag_ack_all_latched[i])
            );
 
 
 
 
 
 
        end
    endgenerate
 
    reg [1:0]ctrl_reg;
 
    always @(posedge clk )begin
        jtag_to_wb_stb_reg<= jtag_to_wb_stb ;
        jtag_sel_onehot_reg<=jtag_sel_onehot;
        jtag_to_wb_we_reg<=jtag_to_wb_we;
        jtag_to_wb_addr_reg <=jtag_to_wb_addr;
        system_reset <=   ctrl_reg[0];
        cpu_en       <= ~ ctrl_reg[1];
    end
 
 
 
 
 
 
    localparam BIN_WIDTH     =  (JWB_NUM>1)? log2(JWB_NUM):1;
    wire [BIN_WIDTH-1 : 0] jtag_sel_bin;
 
 
    jtag_one_hot_to_bin #(
        .ONE_HOT_WIDTH(JWB_NUM),
        .BIN_WIDTH(BIN_WIDTH)
    )
    convert
    (
        .one_hot_code(jtag_sel_onehot),
        .bin_code(jtag_sel_bin)
    );
 
 
 
     assign wb_to_jtag_status=wb_to_jtag_status_all[jtag_sel_bin];
     assign wb_to_jtag_ack =wb_to_jtag_ack_all_latched[jtag_sel_bin];
    // assign wb_to_jtag_dat=wb_to_jtag_dat_all   [jtag_sel_bin];
   //use one-hot mux if index doesnt match the read data is zero
     jtag_one_hot_mux #(
        .IN_WIDTH(JDw*JWB_NUM),
        .SEL_WIDTH(JWB_NUM),
        .OUT_WIDTH(JDw)
     )
     one_hot_mux
     (
        .mux_in(wb_to_jtag_dat_all_latched),
        .mux_out(wb_to_jtag_dat),
        .sel(jtag_sel_onehot_reg)
     );
 
 
    //assign {wb_to_jtag_status,wb_to_jtag_ack,wb_to_jtag_dat}
 
 
 
    wire mem_ctrl_jtag_ack;
 
 
 
 
 
 
    xilinx_jtag_mem_ctrl #(
        .JTAG_CHAIN(JTAG_CHAIN),
        .Dw(JDw),
        .Aw(JAw),
        .INDEXw(JINDEXw)
    )
    mem_ctrl
    (
      //  .ps(),
      //  .clk(clk),
        .tclk   (tclk    ),
        .wb_to_jtag_status(wb_to_jtag_status ),
        .wb_to_jtag_dat   (wb_to_jtag_dat    ),
        .wb_to_jtag_ack   (mem_ctrl_jtag_ack    ),
 
        .jtag_to_wb_ir    (  ),
        .jtag_to_wb_index (jtag_to_wb_index  ),
        .jtag_to_wb_dat   (jtag_to_wb_dat    ),
        .jtag_to_wb_addr  (jtag_to_wb_addr   ),
        .jtag_to_wb_stb   (jtag_to_wb_stb    ),
        .jtag_to_wb_we    (jtag_to_wb_we     ),
 
        .reset (reset)
 
 
   );
 
 
    reg rst_ctrl_ack;
`ifdef SYNC_RESET_MODE
    always @ (posedge tclk )begin
`else
    always @ (posedge tclk or posedge reset)begin
`endif
 
       if(reset) begin
        ctrl_reg <=2'b00;
 
       end
       else if(jtag_to_wb_index ==   CTRL_REG_INDEX)begin
 
            if(jtag_to_wb_we & jtag_to_wb_stb) begin
                ctrl_reg <= jtag_to_wb_dat[1:0];
 
            end
       end
    end
`ifdef SYNC_RESET_MODE
    always @ (posedge tclk )begin
`else
    always @ (posedge tclk or posedge reset)begin
`endif
 
        if(reset) begin
            rst_ctrl_ack<=1'b0;
 
       end
       else begin
            rst_ctrl_ack <= jtag_to_wb_stb;
 
       end
    end
 
 
 
 
 
    assign  mem_ctrl_jtag_ack = ((jtag_to_wb_index ==   CTRL_REG_INDEX) ||  jtag_sel_onehot == {JWB_NUM{1'b0}} ) ? rst_ctrl_ack : wb_to_jtag_ack;
endmodule
 
 
 
 
 
 
module wb_to_jtag_latch  (
    clk,
    jtag_clk,
    in,
    out
);
 
   input clk,jtag_clk,in;
   output out;
 
   reg out_latch,reset_out;
 
 
    always @ (posedge clk) begin
        if(in) out_latch<=1'b1;
        else if(reset_out) out_latch<=1'b0;
    end
 
   always @(posedge jtag_clk)begin
        if(out_latch | in) reset_out<=1'b1;
        else reset_out<=1'b0;
 
   end
 
 
 
    assign out =  reset_out ;
 
 
endmodule
 
 
/**************
 *  xilinx_jtag_mem_ctrl
 * ************/
 
 
 
module  xilinx_jtag_mem_ctrl #(
    parameter JTAG_CHAIN=4,
    parameter Dw=32,
    parameter Aw=32,
    parameter INDEXw=8,
    parameter STATUSw=8
)(
 
   // ps,
    wb_to_jtag_status,
    wb_to_jtag_dat,
    wb_to_jtag_ack,
 
    jtag_to_wb_ir,
    jtag_to_wb_index,
    jtag_to_wb_dat,
    jtag_to_wb_addr,
    jtag_to_wb_stb,
    jtag_to_wb_we,
  //  clk,    
    reset,
    tclk
);
 
  localparam Iw=3;
 
    input [STATUSw-1    : 0] wb_to_jtag_status;
    input [Dw-1 : 0] wb_to_jtag_dat;
    input wb_to_jtag_ack;
 
    output [INDEXw-1  : 0] jtag_to_wb_index;
 
    output [Iw-1 : 0] jtag_to_wb_ir;
    output [Dw-1 : 0] jtag_to_wb_dat;
    output [Aw-1 : 0] jtag_to_wb_addr;
    output jtag_to_wb_stb;
    output jtag_to_wb_we;
 
    //input clk;
    input reset;
    output tclk;
 
     localparam
        STATE_NUM=3,
        IDEAL =1,
        WB_WR_DATA=2,
        WB_RD_DATA=4;
 
 
 
    reg [STATE_NUM-1    :   0] ns, ps;
    wire reset_ps=1'b0;
 
 
    wire  wb_wr_addr_en,  wb_wr_data_en,    wb_rd_data_en;
    reg wr_mem_en,  rd_mem_en;//  wb_cap_rd;
 
    reg [Aw-1   :   0]  wb_addr,wb_addr_next;
   // reg [Dw-1   :   0]  wb_rd_data;
    wire [Dw-1   :   0]  wb_wr_data;
    reg wb_addr_inc;
 
 
    assign  jtag_to_wb_stb    = (wr_mem_en |  rd_mem_en) & ~reset_ps;
    assign  jtag_to_wb_we     = wr_mem_en;
    assign  jtag_to_wb_dat    = wb_wr_data;
    assign  jtag_to_wb_addr   = wb_addr;
 
 
    localparam
        JDw= (Dw > Aw)? Dw : Aw;
 
    wire [JDw-1  :0] data_out;
    wire [JDw-1   :0] data_in;
 
    //assign  data_in    = wb_rd_data;
   assign  data_in = wb_to_jtag_dat;
 
    wire ir_updated;
 
    xilinx_jtag_ctrl #(
        .JTAG_CHAIN(JTAG_CHAIN),
        .Dw(JDw),
        .INDEXw(INDEXw),
        .STw(STATUSw)
    )
    vjtag_ctrl_inst
    (
  //      .clk(clk),
        .ir(jtag_to_wb_ir  ),
        .status_i(wb_to_jtag_status),
        .index(jtag_to_wb_index),
        .tck(tclk),
        .reset(reset),
        .data_out(data_out),
        .data_in(data_in),
        .wb_wr_addr_en(wb_wr_addr_en),
        .wb_wr_data_en(wb_wr_data_en),
        .wb_rd_data_en(wb_rd_data_en),
        .ir_updated(ir_updated)
    );
 
`ifdef SYNC_RESET_MODE
    always @ (posedge tclk )begin
`else
    always @ (posedge tclk or posedge reset)begin
`endif
        if(reset) begin
            wb_addr <= {Aw{1'b0}};
           // wb_wr_data  <= {Dw{1'b0}};  
           // wb_rd_data  <= {Dw{1'b0}};
            ps <= IDEAL;
        end else begin
            wb_addr <= wb_addr_next;
              if(reset_ps)   ps <= IDEAL;
              else ps <= ns;
           // if(wb_wr_data_en) wb_wr_data  <= data_out;  
           // if(wb_cap_rd | ir_updated ) wb_rd_data <= wb_to_jtag_dat;
        end
    end
 
    assign wb_wr_data = data_out;
 
    always @(*)begin
        wb_addr_next= wb_addr;
        if(wb_wr_addr_en) wb_addr_next = data_out [Aw-1 :   0];
        else if (wb_addr_inc)  wb_addr_next = wb_addr +1'b1;
    end
 
 
 
    always @(*)begin
        ns=ps;
        wr_mem_en =1'b0;
        rd_mem_en =1'b0;
        wb_addr_inc=1'b0;
       // wb_cap_rd=1'b0;
 
 
        case(ps)
        IDEAL : begin
            if(wb_wr_data_en) ns= WB_WR_DATA;
            if(wb_rd_data_en) begin
                ns= WB_RD_DATA;
               // wb_cap_rd=1'b1;
             end
        end
        WB_WR_DATA: begin
            wr_mem_en =1'b1;
            if(wb_to_jtag_ack) begin
                wr_mem_en =1'b0;
                ns=IDEAL;
                wb_addr_inc=1'b1;
            end
        end
        WB_RD_DATA: begin
            rd_mem_en =1'b1;
            //wb_cap_rd=1'b1;
            if(wb_to_jtag_ack) begin
                 rd_mem_en =1'b0;
                // wb_cap_rd=1'b0;
                ns=IDEAL;
                //wb_addr_inc=1'b1;         
            end
        end
        default begin
            ns=IDEAL;
        end
        endcase
    end
 
endmodule
 
 
 
/****************
 *  xilinx_jtag_ctrl
 * *************/
module xilinx_jtag_ctrl #(
    parameter JTAG_CHAIN=4,
    parameter Dw=32,
    parameter INDEXw=8,
    parameter STw=8
)(
  //  clk,
    tck,
    reset,
    ir_updated,
    status_i,
    data_out,
    data_in,
    wb_wr_addr_en,
    wb_wr_data_en,
    wb_rd_data_en,
    ir,
    index
);
 
 
 
    localparam
        Iw=3,
        M1 = (Dw>Iw)? Dw :Iw,
        M2 = (M1>INDEXw)? M1 :INDEXw,
        BUFFw= M1+4;
 
     // IR states
     localparam [Iw-1:0]
        UPDATE_WB_ADDR  = 3'b111,
        UPDATE_WB_WR_DATA  = 3'b110,
        UPDATE_WB_RD_DATA  = 3'b101,
        RD_STATUS      =3'b100,
        UPDATE_CTRL =3'b001,
        BYPASS = 3'b000;//not used
 
 
 
//IO declaration
  //  input clk;
    input reset;
    output tck;
    input [STw-1 :0] status_i;
    input [Dw-1 :0] data_in;
    output reg wb_wr_addr_en, wb_wr_data_en,    wb_rd_data_en;
 
    output  reg [Iw-1:0] ir;
    output  reg [INDEXw-1:0] index;
    output   reg [Dw-1    :0] data_out;
    output reg ir_updated;
 
 
    wire      tdo, tck,   tdi;
    wire      cdr ,sdr,udr;
    wire tlr;
 
    xilinx_jtag_bscan #(
        .JTAG_CHAIN(JTAG_CHAIN)
    )
    vjtag_inst
    (
        .tdo ( tdo ),
        .tck ( tck ),
        .tdi ( tdi ),
 
        .tlr ( tlr ),
        .cdr ( cdr ),
        .sdr ( sdr ),
        .udr ( udr )
     );
 
    // internal registers 
   (* KEEP = "TRUE" *)  reg [BUFFw-1   :   0] jtag_shift_buffer,jtag_shift_buffer_next;
 
    assign tdo =  jtag_shift_buffer[0];
 
    always @ (*)begin
        jtag_shift_buffer_next=jtag_shift_buffer;
        if( sdr ) jtag_shift_buffer_next={tdi,jtag_shift_buffer[BUFFw-1:1]};// shift buffer
        else if( cdr )begin
            case(ir)
            RD_STATUS:begin
                jtag_shift_buffer_next[STw-1  :   0] = status_i;
            end
            UPDATE_WB_RD_DATA: begin
                jtag_shift_buffer_next[Dw-1 : 0] = data_in;
                //synthesis translate_off 
                 if(data_in[7:0]!=7'd0 && index==126)  $write("%c",data_in[7:0]);
                //synthesis translate_on
            end
            default :begin
                jtag_shift_buffer_next=jtag_shift_buffer;
            end
            endcase
        end
    end
 
    localparam
        UPDATE_INDEX =0,
        UPDATE_IR=1,
        UPDATE_DAT=2;
 
    wire update_index_flag = jtag_shift_buffer[M1+UPDATE_INDEX];
    wire update_ir_flag    = jtag_shift_buffer[M1+UPDATE_IR];
    wire update_dat_flag   = jtag_shift_buffer[M1+UPDATE_DAT];
 
    always @(posedge tck )    begin
         jtag_shift_buffer<=jtag_shift_buffer_next;
    end
 
      reg mask;
 
      always @(posedge tck )    begin
            if( udr)begin
                if(update_index_flag) begin
                    index <= jtag_shift_buffer[INDEXw-1 : 0];
                    ir<={Iw{1'b0}};
                    mask<=1'b1;
 
 
                end else if(update_ir_flag   )begin
                    ir    <= jtag_shift_buffer[Iw-1 : 0];
 
                    mask<=1'b1;
                end
                if(update_dat_flag  )begin
                    data_out <= jtag_shift_buffer[Dw-1 : 0];
                    mask<=1'b0;
 
                end
            end
    end
 
 
 
    always @( posedge tck )    begin
            if( udr && update_ir_flag   ) ir_updated<=1'b1;
            else ir_updated<=1'b0;
    end
   // assign data_out = jtag_shift_buffer[Dw-1 : 0];
 
   /*
    always @(posedge tck ) begin
           if( sdr ) jtag_shift_buffer<={tdi,jtag_shift_buffer[BUFFw-1:1]};// shift buffer
           if( cdr ) jtag_shift_buffer<={data_in,ir};
           if( udr ) ir <= jtag_shift_buffer_next[Iw-1:0];
    end
    */
 
 
 
    //always @(posedge tck or posedge reset)
    always @(posedge tck)
    begin
        //if( reset )   begin
        //  wb_wr_addr1<=1'b0;
        //  wb_wr_data1<=1'b0;
        //end else begin
            wb_wr_addr_en<=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) &  udr & update_dat_flag;
            wb_wr_data_en<=((ir== UPDATE_WB_WR_DATA|| ir==UPDATE_CTRL) &  udr & update_dat_flag);
            wb_rd_data_en<=((ir== UPDATE_WB_RD_DATA) &  cdr  & ~mask);
        //end   
    end
 
 
 
 
endmodule
 
/**************
 *  xilinx_jtag_bscan
 * ************/
 
module xilinx_jtag_bscan #(
    // Only used for Virtex 4/5 devices
    parameter JTAG_CHAIN = 4  // May be 1, 2, 3, or 4
)
(
    tck,
    tdo,
    tdi,
 
    tlr,
    sdr,
    cdr,
    udr
);
 
 
 
input  tdo;
output tck;
output tdi;
 
output tlr;
output sdr;
output cdr;
output udr;
 
wire tck_i;
 
wire sel;
wire shift,update,capture;
assign sdr = shift & sel;
assign udr = update & sel;
assign cdr = capture & sel;
 
`ifdef MODEL_TECH
    `define RUN_SIM
`endif
`ifdef VERILATOR
    `define RUN_SIM
`endif
 
`ifdef  RUN_SIM
 
    BSCANE2_sim #(
        .JTAG_CHAIN(JTAG_CHAIN) // Value for USER command.
    )
    bse2_inst
    (
        .CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.
        .DRCK(), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.
        .RESET(tlr), // 1-bit output: Reset output for TAP controller.
        .RUNTEST(), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
        .SEL(sel), // 1-bit output: USER instruction active output.
        .SHIFT(shift), // 1-bit output: SHIFT output from TAP controller.
        .TCK(tck), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
        .TDI(tdi), // 1-bit output: Test Data Input (TDI) output from TAP controller.
        .TMS( ), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
        .UPDATE(update), // 1-bit output: UPDATE output from TAP controller
        .TDO(tdo) // 1-bit input: Test Data Output (TDO) input for USER function.
    );
 
 
 
`else
 
 
 
    BSCANE2 #(
        .JTAG_CHAIN(JTAG_CHAIN) // Value for USER command.
    )
    bse2_inst
    (
        .CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.
        .DRCK( ), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.
        .RESET(tlr), // 1-bit output: Reset output for TAP controller.
        .RUNTEST(), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
        .SEL(sel), // 1-bit output: USER instruction active output.
        .SHIFT(shift), // 1-bit output: SHIFT output from TAP controller.
        .TCK(tck), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
        .TDI(tdi), // 1-bit output: Test Data Input (TDI) output from TAP controller.
        .TMS( ), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
        .UPDATE(update), // 1-bit output: UPDATE output from TAP controller
        .TDO(tdo) // 1-bit input: Test Data Output (TDO) input for USER function.
    );
 
 //     BUFG clk_buf(tck, tck_i);
 
`endif
 
endmodule
 
 
 
module jtag_one_hot_to_bin #(
    parameter ONE_HOT_WIDTH =   4,
    parameter BIN_WIDTH     =  (ONE_HOT_WIDTH>1)? log2(ONE_HOT_WIDTH):1
)
(
    input   [ONE_HOT_WIDTH-1        :   0] one_hot_code,
    output  [BIN_WIDTH-1            :   0]  bin_code
 
);
 
 
    function integer log2;
      input integer number; begin
         log2=(number <=1) ? 1: 0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
    endfunction // log2 
 
localparam MUX_IN_WIDTH =   BIN_WIDTH* ONE_HOT_WIDTH;
 
wire [MUX_IN_WIDTH-1        :   0]  bin_temp ;
 
genvar i;
generate
    if(ONE_HOT_WIDTH>1)begin :if1
        for(i=0; i<ONE_HOT_WIDTH; i=i+1) begin :mux_in_gen_loop
            assign bin_temp[(i+1)*BIN_WIDTH-1 : i*BIN_WIDTH] =  i[BIN_WIDTH-1:0];
        end
 
 
        jtag_one_hot_mux #(
            .IN_WIDTH   (MUX_IN_WIDTH),
            .SEL_WIDTH  (ONE_HOT_WIDTH)
 
        )
        one_hot_to_bcd_mux
        (
            .mux_in     (bin_temp),
            .mux_out        (bin_code),
            .sel            (one_hot_code)
 
        );
     end else begin :els
        assign  bin_code = 1'b0;
 
     end
 
endgenerate
 
endmodule
 
 
module jtag_one_hot_mux #(
        parameter   IN_WIDTH      = 20,
        parameter   SEL_WIDTH =   5,
        parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
 
    )
    (
        input [IN_WIDTH-1       :0] mux_in,
        output[OUT_WIDTH-1  :0] mux_out,
        input[SEL_WIDTH-1   :0] sel
 
    );
 
    wire [IN_WIDTH-1    :0] mask;
    wire [IN_WIDTH-1    :0] masked_mux_in;
    wire [SEL_WIDTH-1:0]    mux_out_gen [OUT_WIDTH-1:0];
 
    genvar i,j;
 
    //first selector masking
    generate    // first_mask = {sel[0],sel[0],sel[0],....,sel[n],sel[n],sel[n]}
        for(i=0; i<SEL_WIDTH; i=i+1) begin : mask_loop
            assign mask[(i+1)*OUT_WIDTH-1 : (i)*OUT_WIDTH]  =   {OUT_WIDTH{sel[i]} };
        end
 
        assign masked_mux_in    = mux_in & mask;
 
        for(i=0; i<OUT_WIDTH; i=i+1) begin : lp1
            for(j=0; j<SEL_WIDTH; j=j+1) begin : lp2
                assign mux_out_gen [i][j]   =   masked_mux_in[i+OUT_WIDTH*j];
            end
            assign mux_out[i] = | mux_out_gen [i];
        end
    endgenerate
 
endmodule
 

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [jtag/] [jtag_wb/] [xilinx_jtag_wb.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`/**********************************************************************`
2			`** File: xilinx_jtag_wb.v`
3			`**`
4			`**`
5			`** Copyright (C) 2020 Alireza Monemi`
6			`**`
7			`** This file is part of ProNoC`
8			`**`
9			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
10			`** you can redistribute it and/or modify it under the terms of the GNU`
11			`** Lesser General Public License as published by the Free Software Foundation,`
12			`** either version 2 of the License, or (at your option) any later version.`
13			`**`
14			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
21			`**`
22			`**`
23			`** Description:`
24			`** xilinx bscan chain to wishbon bus interface. It prvide simple read/write on`
25			`** whishbone bus. Does not support burst transaction.`
26			`**`
27			`*******************************************************************/`
28
29
30			`// synthesis translate_off`
31			`timescale 1ns / 1ps
32			`// synthesis translate_on`
33
34			`module xilinx_jtag_wb #(`
35			`parameter JTAG_CHAIN=4, // Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4`
36			`parameter JWB_NUM=1,`
37			`parameter JDw=32,`
38			`parameter JAw=32,`
39			`parameter JINDEXw=8,`
40			`parameter JSTATUSw=8,`
41			`parameter CTRL_REG_INDEX =127`
42
43			`)(`
44			`// clk, get the clock from wb interface`
45			`reset,`
46			`cpu_en,`
47			`system_reset,`
48			`wb_to_jtag_all,`
49			`jtag_to_wb_all`
50			`);`
51
52			`function integer log2;`
53			`input integer number; begin`
54			`log2=(number <=1) ? 1: 0;`
55			`while(2**log2<number) begin`
56			`log2=log2+1;`
57			`end`
58			`end`
59			`endfunction // log2`
60
61			`localparam J2WBw= 1+1+JDw+JAw;`
62			`localparam WB2Jw=1+JSTATUSw+JINDEXw+1+JDw;`
63
64			`input reset;//,clk;`
65			`output reg cpu_en, system_reset;`
66
67			`// output [7: 0 ] out;`
68
69			`input [JWB_NUM*WB2Jw-1 : 0] wb_to_jtag_all;`
70			`output[JWB_NUM*J2WBw-1 : 0] jtag_to_wb_all;`
71
72			`wire [J2WBw-1 : 0] jtag_to_wb [JWB_NUM-1 : 0];`
73			`wire [WB2Jw-1 : 0] wb_to_jtag [JWB_NUM-1 : 0];`
74			`wire [JINDEXw-1 : 0] wb_to_jtag_index_all[JWB_NUM-1 : 0];`
75			`//wire [JDw-1 : 0] wb_to_jtag_dat_all [JWB_NUM-1 : 0];`
76			`wire [JDw*JWB_NUM-1 : 0] wb_to_jtag_dat_all;`
77			`wire [JDw*JWB_NUM-1 : 0] wb_to_jtag_dat_all_latched;`
78			`wire [JWB_NUM-1 : 0] wb_to_jtag_ack_all;`
79			`wire [JWB_NUM-1 : 0] wb_to_jtag_ack_all_latched;`
80			`wire [JSTATUSw-1 : 0] wb_to_jtag_status_all [JWB_NUM-1 : 0];`
81
82			`wire [JINDEXw-1 : 0] jtag_to_wb_index;`
83			`wire [JWB_NUM-1: 0] jtag_sel_onehot;`
84			`wire [WB2Jw-1 : 0] wb_to_jtag_mux;`
85			`wire [JWB_NUM-1: 0] stb_all;`
86
87			`wire [JSTATUSw-1 : 0] wb_to_jtag_status;`
88			`wire [JDw-1 : 0] wb_to_jtag_dat;`
89			`wire wb_to_jtag_ack;`
90
91			`wire [JDw-1 : 0] jtag_to_wb_dat;`
92			`wire [JAw-1 : 0] jtag_to_wb_addr;`
93			`reg [JAw-1 : 0] jtag_to_wb_addr_reg;`
94			`wire jtag_to_wb_stb;`
95			`wire jtag_to_wb_we;`
96			`wire [JWB_NUM-1 : 0] wb_to_jtag_clk;`
97
98			`wire tclk;//jtag clk`
99			`wire clk = wb_to_jtag_clk[0];`
100
101			`wire [JWB_NUM-1 : 0] stb_masked_all;`
102
103			`reg [JDw-1 : 0] jtag_dat_in_reg [JWB_NUM-1: 0];`
104
105			`reg jtag_to_wb_stb_reg;`
106			`reg [JWB_NUM-1: 0] jtag_sel_onehot_reg;`
107			`reg jtag_to_wb_we_reg;`
108
109			`genvar i;`
110			`generate`
111			`for (i = 0; i < JWB_NUM ; i = i + 1) begin : block`
112
113			`assign wb_to_jtag[i] = wb_to_jtag_all [(i+1)WB2Jw-1 : iWB2Jw];`
114			`assign {wb_to_jtag_status_all[i],wb_to_jtag_ack_all[i],wb_to_jtag_dat_all[(i+1)JDw-1 : iJDw],wb_to_jtag_index_all [i],wb_to_jtag_clk[i]} = wb_to_jtag[i];`
115			`assign jtag_sel_onehot[i] = (wb_to_jtag_index_all [i] == jtag_to_wb_index);`
116			`assign stb_all[i] = jtag_to_wb_stb_reg & jtag_sel_onehot_reg[i];`
117			`assign jtag_to_wb_all[(i+1)J2WBw-1 : iJ2WBw] =jtag_to_wb[i];`
118			`assign stb_masked_all[i] = stb_all[i] ; // & ~wb_to_jtag_ack_all_latched[i];`
119			`assign jtag_to_wb[i] = {jtag_to_wb_addr_reg,stb_masked_all[i],jtag_to_wb_we_reg,jtag_to_wb_dat};`
120
121			`always @ (posedge clk)begin`
122			`if ( wb_to_jtag_ack_all[i] & jtag_sel_onehot_reg[i] & ~jtag_to_wb_we) jtag_dat_in_reg[i] <= wb_to_jtag_dat_all[(i+1)JDw-1 : iJDw];`
123			`end`
124			`assign wb_to_jtag_dat_all_latched [(i+1)JDw-1 : iJDw] = jtag_dat_in_reg[i];`
125
126			`wb_to_jtag_latch ack_latch`
127			`(`
128			`.clk(clk),`
129			`.jtag_clk(tclk),`
130			`.in(wb_to_jtag_ack_all[i]),`
131			`.out(wb_to_jtag_ack_all_latched[i])`
132			`);`
133
134
135
136
137
138
139			`end`
140			`endgenerate`
141
142			`reg [1:0]ctrl_reg;`
143
144			`always @(posedge clk )begin`
145			`jtag_to_wb_stb_reg<= jtag_to_wb_stb ;`
146			`jtag_sel_onehot_reg<=jtag_sel_onehot;`
147			`jtag_to_wb_we_reg<=jtag_to_wb_we;`
148			`jtag_to_wb_addr_reg <=jtag_to_wb_addr;`
149			`system_reset <= ctrl_reg[0];`
150			`cpu_en <= ~ ctrl_reg[1];`
151			`end`
152
153
154
155
156
157
158			`localparam BIN_WIDTH = (JWB_NUM>1)? log2(JWB_NUM):1;`
159			`wire [BIN_WIDTH-1 : 0] jtag_sel_bin;`
160
161
162			`jtag_one_hot_to_bin #(`
163			`.ONE_HOT_WIDTH(JWB_NUM),`
164			`.BIN_WIDTH(BIN_WIDTH)`
165			`)`
166			`convert`
167			`(`
168			`.one_hot_code(jtag_sel_onehot),`
169			`.bin_code(jtag_sel_bin)`
170			`);`
171
172
173
174			`assign wb_to_jtag_status=wb_to_jtag_status_all[jtag_sel_bin];`
175			`assign wb_to_jtag_ack =wb_to_jtag_ack_all_latched[jtag_sel_bin];`
176			`// assign wb_to_jtag_dat=wb_to_jtag_dat_all [jtag_sel_bin];`
177			`//use one-hot mux if index doesnt match the read data is zero`
178			`jtag_one_hot_mux #(`
179			`.IN_WIDTH(JDw*JWB_NUM),`
180			`.SEL_WIDTH(JWB_NUM),`
181			`.OUT_WIDTH(JDw)`
182			`)`
183			`one_hot_mux`
184			`(`
185			`.mux_in(wb_to_jtag_dat_all_latched),`
186			`.mux_out(wb_to_jtag_dat),`
187			`.sel(jtag_sel_onehot_reg)`
188			`);`
189
190
191			`//assign {wb_to_jtag_status,wb_to_jtag_ack,wb_to_jtag_dat}`
192
193
194
195			`wire mem_ctrl_jtag_ack;`
196
197
198
199
200
201
202			`xilinx_jtag_mem_ctrl #(`
203			`.JTAG_CHAIN(JTAG_CHAIN),`
204			`.Dw(JDw),`
205			`.Aw(JAw),`
206			`.INDEXw(JINDEXw)`
207			`)`
208			`mem_ctrl`
209			`(`
210			`// .ps(),`
211			`// .clk(clk),`
212			`.tclk (tclk ),`
213			`.wb_to_jtag_status(wb_to_jtag_status ),`
214			`.wb_to_jtag_dat (wb_to_jtag_dat ),`
215			`.wb_to_jtag_ack (mem_ctrl_jtag_ack ),`
216
217			`.jtag_to_wb_ir ( ),`
218			`.jtag_to_wb_index (jtag_to_wb_index ),`
219			`.jtag_to_wb_dat (jtag_to_wb_dat ),`
220			`.jtag_to_wb_addr (jtag_to_wb_addr ),`
221			`.jtag_to_wb_stb (jtag_to_wb_stb ),`
222			`.jtag_to_wb_we (jtag_to_wb_we ),`
223
224			`.reset (reset)`
225
226
227			`);`
228
229
230			`reg rst_ctrl_ack;`
231			`ifdef SYNC_RESET_MODE
232			`always @ (posedge tclk )begin`
233			`else
234			`always @ (posedge tclk or posedge reset)begin`
235			`endif
236
237			`if(reset) begin`
238			`ctrl_reg <=2'b00;`
239
240			`end`
241			`else if(jtag_to_wb_index == CTRL_REG_INDEX)begin`
242
243			`if(jtag_to_wb_we & jtag_to_wb_stb) begin`
244			`ctrl_reg <= jtag_to_wb_dat[1:0];`
245
246			`end`
247			`end`
248			`end`
249			`ifdef SYNC_RESET_MODE
250			`always @ (posedge tclk )begin`
251			`else
252			`always @ (posedge tclk or posedge reset)begin`
253			`endif
254
255			`if(reset) begin`
256			`rst_ctrl_ack<=1'b0;`
257
258			`end`
259			`else begin`
260			`rst_ctrl_ack <= jtag_to_wb_stb;`
261
262			`end`
263			`end`
264
265
266
267
268
269			`assign mem_ctrl_jtag_ack = ((jtag_to_wb_index == CTRL_REG_INDEX) \|\| jtag_sel_onehot == {JWB_NUM{1'b0}} ) ? rst_ctrl_ack : wb_to_jtag_ack;`
270			`endmodule`
271
272
273
274
275
276
277			`module wb_to_jtag_latch (`
278			`clk,`
279			`jtag_clk,`
280			`in,`
281			`out`
282			`);`
283
284			`input clk,jtag_clk,in;`
285			`output out;`
286
287			`reg out_latch,reset_out;`
288
289
290			`always @ (posedge clk) begin`
291			`if(in) out_latch<=1'b1;`
292			`else if(reset_out) out_latch<=1'b0;`
293			`end`
294
295			`always @(posedge jtag_clk)begin`
296			`if(out_latch \| in) reset_out<=1'b1;`
297			`else reset_out<=1'b0;`
298
299			`end`
300
301
302
303			`assign out = reset_out ;`
304
305
306			`endmodule`
307
308
309			`/**************`
310			`* xilinx_jtag_mem_ctrl`
311			`* ************/`
312
313
314
315			`module xilinx_jtag_mem_ctrl #(`
316			`parameter JTAG_CHAIN=4,`
317			`parameter Dw=32,`
318			`parameter Aw=32,`
319			`parameter INDEXw=8,`
320			`parameter STATUSw=8`
321			`)(`
322
323			`// ps,`
324			`wb_to_jtag_status,`
325			`wb_to_jtag_dat,`
326			`wb_to_jtag_ack,`
327
328			`jtag_to_wb_ir,`
329			`jtag_to_wb_index,`
330			`jtag_to_wb_dat,`
331			`jtag_to_wb_addr,`
332			`jtag_to_wb_stb,`
333			`jtag_to_wb_we,`
334			`// clk,`
335			`reset,`
336			`tclk`
337			`);`
338
339			`localparam Iw=3;`
340
341			`input [STATUSw-1 : 0] wb_to_jtag_status;`
342			`input [Dw-1 : 0] wb_to_jtag_dat;`
343			`input wb_to_jtag_ack;`
344
345			`output [INDEXw-1 : 0] jtag_to_wb_index;`
346
347			`output [Iw-1 : 0] jtag_to_wb_ir;`
348			`output [Dw-1 : 0] jtag_to_wb_dat;`
349			`output [Aw-1 : 0] jtag_to_wb_addr;`
350			`output jtag_to_wb_stb;`
351			`output jtag_to_wb_we;`
352
353			`//input clk;`
354			`input reset;`
355			`output tclk;`
356
357			`localparam`
358			`STATE_NUM=3,`
359			`IDEAL =1,`
360			`WB_WR_DATA=2,`
361			`WB_RD_DATA=4;`
362
363
364
365			`reg [STATE_NUM-1 : 0] ns, ps;`
366			`wire reset_ps=1'b0;`
367
368
369			`wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;`
370			`reg wr_mem_en, rd_mem_en;// wb_cap_rd;`
371
372			`reg [Aw-1 : 0] wb_addr,wb_addr_next;`
373			`// reg [Dw-1 : 0] wb_rd_data;`
374			`wire [Dw-1 : 0] wb_wr_data;`
375			`reg wb_addr_inc;`
376
377
378			`assign jtag_to_wb_stb = (wr_mem_en \| rd_mem_en) & ~reset_ps;`
379			`assign jtag_to_wb_we = wr_mem_en;`
380			`assign jtag_to_wb_dat = wb_wr_data;`
381			`assign jtag_to_wb_addr = wb_addr;`
382
383
384			`localparam`
385			`JDw= (Dw > Aw)? Dw : Aw;`
386
387			`wire [JDw-1 :0] data_out;`
388			`wire [JDw-1 :0] data_in;`
389
390			`//assign data_in = wb_rd_data;`
391			`assign data_in = wb_to_jtag_dat;`
392
393			`wire ir_updated;`
394
395			`xilinx_jtag_ctrl #(`
396			`.JTAG_CHAIN(JTAG_CHAIN),`
397			`.Dw(JDw),`
398			`.INDEXw(INDEXw),`
399			`.STw(STATUSw)`
400			`)`
401			`vjtag_ctrl_inst`
402			`(`
403			`// .clk(clk),`
404			`.ir(jtag_to_wb_ir ),`
405			`.status_i(wb_to_jtag_status),`
406			`.index(jtag_to_wb_index),`
407			`.tck(tclk),`
408			`.reset(reset),`
409			`.data_out(data_out),`
410			`.data_in(data_in),`
411			`.wb_wr_addr_en(wb_wr_addr_en),`
412			`.wb_wr_data_en(wb_wr_data_en),`
413			`.wb_rd_data_en(wb_rd_data_en),`
414			`.ir_updated(ir_updated)`
415			`);`
416
417			`ifdef SYNC_RESET_MODE
418			`always @ (posedge tclk )begin`
419			`else
420			`always @ (posedge tclk or posedge reset)begin`
421			`endif
422			`if(reset) begin`
423			`wb_addr <= {Aw{1'b0}};`
424			`// wb_wr_data <= {Dw{1'b0}};`
425			`// wb_rd_data <= {Dw{1'b0}};`
426			`ps <= IDEAL;`
427			`end else begin`
428			`wb_addr <= wb_addr_next;`
429			`if(reset_ps) ps <= IDEAL;`
430			`else ps <= ns;`
431			`// if(wb_wr_data_en) wb_wr_data <= data_out;`
432			`// if(wb_cap_rd \| ir_updated ) wb_rd_data <= wb_to_jtag_dat;`
433			`end`
434			`end`
435
436			`assign wb_wr_data = data_out;`
437
438			`always @(*)begin`
439			`wb_addr_next= wb_addr;`
440			`if(wb_wr_addr_en) wb_addr_next = data_out [Aw-1 : 0];`
441			`else if (wb_addr_inc) wb_addr_next = wb_addr +1'b1;`
442			`end`
443
444
445
446			`always @(*)begin`
447			`ns=ps;`
448			`wr_mem_en =1'b0;`
449			`rd_mem_en =1'b0;`
450			`wb_addr_inc=1'b0;`
451			`// wb_cap_rd=1'b0;`
452
453
454			`case(ps)`
455			`IDEAL : begin`
456			`if(wb_wr_data_en) ns= WB_WR_DATA;`
457			`if(wb_rd_data_en) begin`
458			`ns= WB_RD_DATA;`
459			`// wb_cap_rd=1'b1;`
460			`end`
461			`end`
462			`WB_WR_DATA: begin`
463			`wr_mem_en =1'b1;`
464			`if(wb_to_jtag_ack) begin`
465			`wr_mem_en =1'b0;`
466			`ns=IDEAL;`
467			`wb_addr_inc=1'b1;`
468			`end`
469			`end`
470			`WB_RD_DATA: begin`
471			`rd_mem_en =1'b1;`
472			`//wb_cap_rd=1'b1;`
473			`if(wb_to_jtag_ack) begin`
474			`rd_mem_en =1'b0;`
475			`// wb_cap_rd=1'b0;`
476			`ns=IDEAL;`
477			`//wb_addr_inc=1'b1;`
478			`end`
479			`end`
480			`default begin`
481			`ns=IDEAL;`
482			`end`
483			`endcase`
484			`end`
485
486			`endmodule`
487
488
489
490			`/****************`
491			`* xilinx_jtag_ctrl`
492			`* *************/`
493			`module xilinx_jtag_ctrl #(`
494			`parameter JTAG_CHAIN=4,`
495			`parameter Dw=32,`
496			`parameter INDEXw=8,`
497			`parameter STw=8`
498			`)(`
499			`// clk,`
500			`tck,`
501			`reset,`
502			`ir_updated,`
503			`status_i,`
504			`data_out,`
505			`data_in,`
506			`wb_wr_addr_en,`
507			`wb_wr_data_en,`
508			`wb_rd_data_en,`
509			`ir,`
510			`index`
511			`);`
512
513
514
515			`localparam`
516			`Iw=3,`
517			`M1 = (Dw>Iw)? Dw :Iw,`
518			`M2 = (M1>INDEXw)? M1 :INDEXw,`
519			`BUFFw= M1+4;`
520
521			`// IR states`
522			`localparam [Iw-1:0]`
523			`UPDATE_WB_ADDR = 3'b111,`
524			`UPDATE_WB_WR_DATA = 3'b110,`
525			`UPDATE_WB_RD_DATA = 3'b101,`
526			`RD_STATUS =3'b100,`
527			`UPDATE_CTRL =3'b001,`
528			`BYPASS = 3'b000;//not used`
529
530
531
532			`//IO declaration`
533			`// input clk;`
534			`input reset;`
535			`output tck;`
536			`input [STw-1 :0] status_i;`
537			`input [Dw-1 :0] data_in;`
538			`output reg wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;`
539
540			`output reg [Iw-1:0] ir;`
541			`output reg [INDEXw-1:0] index;`
542			`output reg [Dw-1 :0] data_out;`
543			`output reg ir_updated;`
544
545
546			`wire tdo, tck, tdi;`
547			`wire cdr ,sdr,udr;`
548			`wire tlr;`
549
550			`xilinx_jtag_bscan #(`
551			`.JTAG_CHAIN(JTAG_CHAIN)`
552			`)`
553			`vjtag_inst`
554			`(`
555			`.tdo ( tdo ),`
556			`.tck ( tck ),`
557			`.tdi ( tdi ),`
558
559			`.tlr ( tlr ),`
560			`.cdr ( cdr ),`
561			`.sdr ( sdr ),`
562			`.udr ( udr )`
563			`);`
564
565			`// internal registers`
566			`(* KEEP = "TRUE" *) reg [BUFFw-1 : 0] jtag_shift_buffer,jtag_shift_buffer_next;`
567
568			`assign tdo = jtag_shift_buffer[0];`
569
570			`always @ (*)begin`
571			`jtag_shift_buffer_next=jtag_shift_buffer;`
572			`if( sdr ) jtag_shift_buffer_next={tdi,jtag_shift_buffer[BUFFw-1:1]};// shift buffer`
573			`else if( cdr )begin`
574			`case(ir)`
575			`RD_STATUS:begin`
576			`jtag_shift_buffer_next[STw-1 : 0] = status_i;`
577			`end`
578			`UPDATE_WB_RD_DATA: begin`
579			`jtag_shift_buffer_next[Dw-1 : 0] = data_in;`
580			`//synthesis translate_off`
581			`if(data_in[7:0]!=7'd0 && index==126) $write("%c",data_in[7:0]);`
582			`//synthesis translate_on`
583			`end`
584			`default :begin`
585			`jtag_shift_buffer_next=jtag_shift_buffer;`
586			`end`
587			`endcase`
588			`end`
589			`end`
590
591			`localparam`
592			`UPDATE_INDEX =0,`
593			`UPDATE_IR=1,`
594			`UPDATE_DAT=2;`
595
596			`wire update_index_flag = jtag_shift_buffer[M1+UPDATE_INDEX];`
597			`wire update_ir_flag = jtag_shift_buffer[M1+UPDATE_IR];`
598			`wire update_dat_flag = jtag_shift_buffer[M1+UPDATE_DAT];`
599
600			`always @(posedge tck ) begin`
601			`jtag_shift_buffer<=jtag_shift_buffer_next;`
602			`end`
603
604			`reg mask;`
605
606			`always @(posedge tck ) begin`
607			`if( udr)begin`
608			`if(update_index_flag) begin`
609			`index <= jtag_shift_buffer[INDEXw-1 : 0];`
610			`ir<={Iw{1'b0}};`
611			`mask<=1'b1;`
612
613
614			`end else if(update_ir_flag )begin`
615			`ir <= jtag_shift_buffer[Iw-1 : 0];`
616
617			`mask<=1'b1;`
618			`end`
619			`if(update_dat_flag )begin`
620			`data_out <= jtag_shift_buffer[Dw-1 : 0];`
621			`mask<=1'b0;`
622
623			`end`
624			`end`
625			`end`
626
627
628
629			`always @( posedge tck ) begin`
630			`if( udr && update_ir_flag ) ir_updated<=1'b1;`
631			`else ir_updated<=1'b0;`
632			`end`
633			`// assign data_out = jtag_shift_buffer[Dw-1 : 0];`
634
635			`/*`
636			`always @(posedge tck ) begin`
637			`if( sdr ) jtag_shift_buffer<={tdi,jtag_shift_buffer[BUFFw-1:1]};// shift buffer`
638			`if( cdr ) jtag_shift_buffer<={data_in,ir};`
639			`if( udr ) ir <= jtag_shift_buffer_next[Iw-1:0];`
640			`end`
641			`*/`
642
643
644
645			`//always @(posedge tck or posedge reset)`
646			`always @(posedge tck)`
647			`begin`
648			`//if( reset ) begin`
649			`// wb_wr_addr1<=1'b0;`
650			`// wb_wr_data1<=1'b0;`
651			`//end else begin`
652			`wb_wr_addr_en<=(ir== UPDATE_WB_ADDR \|\| ir== UPDATE_WB_RD_DATA) & udr & update_dat_flag;`
653			`wb_wr_data_en<=((ir== UPDATE_WB_WR_DATA\|\| ir==UPDATE_CTRL) & udr & update_dat_flag);`
654			`wb_rd_data_en<=((ir== UPDATE_WB_RD_DATA) & cdr & ~mask);`
655			`//end`
656			`end`
657
658
659
660
661			`endmodule`
662
663			`/**************`
664			`* xilinx_jtag_bscan`
665			`* ************/`
666
667			`module xilinx_jtag_bscan #(`
668			`// Only used for Virtex 4/5 devices`
669			`parameter JTAG_CHAIN = 4 // May be 1, 2, 3, or 4`
670			`)`
671			`(`
672			`tck,`
673			`tdo,`
674			`tdi,`
675
676			`tlr,`
677			`sdr,`
678			`cdr,`
679			`udr`
680			`);`
681
682
683
684			`input tdo;`
685			`output tck;`
686			`output tdi;`
687
688			`output tlr;`
689			`output sdr;`
690			`output cdr;`
691			`output udr;`
692
693			`wire tck_i;`
694
695			`wire sel;`
696			`wire shift,update,capture;`
697			`assign sdr = shift & sel;`
698			`assign udr = update & sel;`
699			`assign cdr = capture & sel;`
700
701			`ifdef MODEL_TECH
702			`define RUN_SIM
703			`endif
704			`ifdef VERILATOR
705			`define RUN_SIM
706			`endif
707
708			`ifdef RUN_SIM
709
710			`BSCANE2_sim #(`
711			`.JTAG_CHAIN(JTAG_CHAIN) // Value for USER command.`
712			`)`
713			`bse2_inst`
714			`(`
715			`.CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.`
716			`.DRCK(), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.`
717			`.RESET(tlr), // 1-bit output: Reset output for TAP controller.`
718			`.RUNTEST(), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.`
719			`.SEL(sel), // 1-bit output: USER instruction active output.`
720			`.SHIFT(shift), // 1-bit output: SHIFT output from TAP controller.`
721			`.TCK(tck), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.`
722			`.TDI(tdi), // 1-bit output: Test Data Input (TDI) output from TAP controller.`
723			`.TMS( ), // 1-bit output: Test Mode Select output. Fabric connection to TAP.`
724			`.UPDATE(update), // 1-bit output: UPDATE output from TAP controller`
725			`.TDO(tdo) // 1-bit input: Test Data Output (TDO) input for USER function.`
726			`);`
727
728
729
730			`else
731
732
733
734			`BSCANE2 #(`
735			`.JTAG_CHAIN(JTAG_CHAIN) // Value for USER command.`
736			`)`
737			`bse2_inst`
738			`(`
739			`.CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.`
740			`.DRCK( ), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.`
741			`.RESET(tlr), // 1-bit output: Reset output for TAP controller.`
742			`.RUNTEST(), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.`
743			`.SEL(sel), // 1-bit output: USER instruction active output.`
744			`.SHIFT(shift), // 1-bit output: SHIFT output from TAP controller.`
745			`.TCK(tck), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.`
746			`.TDI(tdi), // 1-bit output: Test Data Input (TDI) output from TAP controller.`
747			`.TMS( ), // 1-bit output: Test Mode Select output. Fabric connection to TAP.`
748			`.UPDATE(update), // 1-bit output: UPDATE output from TAP controller`
749			`.TDO(tdo) // 1-bit input: Test Data Output (TDO) input for USER function.`
750			`);`
751
752			`// BUFG clk_buf(tck, tck_i);`
753
754			`endif
755
756			`endmodule`
757
758
759
760			`module jtag_one_hot_to_bin #(`
761			`parameter ONE_HOT_WIDTH = 4,`
762			`parameter BIN_WIDTH = (ONE_HOT_WIDTH>1)? log2(ONE_HOT_WIDTH):1`
763			`)`
764			`(`
765			`input [ONE_HOT_WIDTH-1 : 0] one_hot_code,`
766			`output [BIN_WIDTH-1 : 0] bin_code`
767
768			`);`
769
770
771			`function integer log2;`
772			`input integer number; begin`
773			`log2=(number <=1) ? 1: 0;`
774			`while(2**log2<number) begin`
775			`log2=log2+1;`
776			`end`
777			`end`
778			`endfunction // log2`
779
780			`localparam MUX_IN_WIDTH = BIN_WIDTH* ONE_HOT_WIDTH;`
781
782			`wire [MUX_IN_WIDTH-1 : 0] bin_temp ;`
783
784			`genvar i;`
785			`generate`
786			`if(ONE_HOT_WIDTH>1)begin :if1`
787			`for(i=0; i<ONE_HOT_WIDTH; i=i+1) begin :mux_in_gen_loop`
788			`assign bin_temp[(i+1)BIN_WIDTH-1 : iBIN_WIDTH] = i[BIN_WIDTH-1:0];`
789			`end`
790
791
792			`jtag_one_hot_mux #(`
793			`.IN_WIDTH (MUX_IN_WIDTH),`
794			`.SEL_WIDTH (ONE_HOT_WIDTH)`
795
796			`)`
797			`one_hot_to_bcd_mux`
798			`(`
799			`.mux_in (bin_temp),`
800			`.mux_out (bin_code),`
801			`.sel (one_hot_code)`
802
803			`);`
804			`end else begin :els`
805			`assign bin_code = 1'b0;`
806
807			`end`
808
809			`endgenerate`
810
811			`endmodule`
812
813
814			`module jtag_one_hot_mux #(`
815			`parameter IN_WIDTH = 20,`
816			`parameter SEL_WIDTH = 5,`
817			`parameter OUT_WIDTH = IN_WIDTH/SEL_WIDTH`
818
819			`)`
820			`(`
821			`input [IN_WIDTH-1 :0] mux_in,`
822			`output[OUT_WIDTH-1 :0] mux_out,`
823			`input[SEL_WIDTH-1 :0] sel`
824
825			`);`
826
827			`wire [IN_WIDTH-1 :0] mask;`
828			`wire [IN_WIDTH-1 :0] masked_mux_in;`
829			`wire [SEL_WIDTH-1:0] mux_out_gen [OUT_WIDTH-1:0];`
830
831			`genvar i,j;`
832
833			`//first selector masking`
834			`generate // first_mask = {sel[0],sel[0],sel[0],....,sel[n],sel[n],sel[n]}`
835			`for(i=0; i<SEL_WIDTH; i=i+1) begin : mask_loop`
836			`assign mask[(i+1)OUT_WIDTH-1 : (i)OUT_WIDTH] = {OUT_WIDTH{sel[i]} };`
837			`end`
838
839			`assign masked_mux_in = mux_in & mask;`
840
841			`for(i=0; i<OUT_WIDTH; i=i+1) begin : lp1`
842			`for(j=0; j<SEL_WIDTH; j=j+1) begin : lp2`
843			`assign mux_out_gen [i][j] = masked_mux_in[i+OUT_WIDTH*j];`
844			`end`
845			`assign mux_out[i] = \| mux_out_gen [i];`
846			`end`
847			`endgenerate`
848
849			`endmodule`
850