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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ni/] [ni_slave.v] - Blame information for rev 48

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/**********************************************************************
**      File:  ni_slave.v
**      Date:2017-06-30
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**      Description:
**      NI with internal input/output memory. generated using NI_master
**      connected to two dualport memory
**
**
*******************************************************************/
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
 
module  ni_slave #(
    parameter MAX_TRANSACTION_WIDTH=10, // Maximum transaction size will be 2 power of MAX_DMA_TRANSACTION_WIDTH words 
    parameter INPUT_MEM_Aw = 10, // input memory address width 
    parameter OUTPUT_MEM_Aw = 10, // input memory address width 
    parameter MAX_BURST_SIZE =256, // in words
    parameter DEBUG_EN = 1,
    //NoC parameters
    parameter CLASS_HDR_WIDTH     =8,
    parameter ROUTING_HDR_WIDTH   =8,
    parameter DST_ADR_HDR_WIDTH  =8,
    parameter SRC_ADR_HDR_WIDTH   =8,
    parameter TOPOLOGY =    "MESH",//"MESH","TORUS","RING" 
    parameter ROUTE_NAME    =   "XY",
    parameter NX = 4,   // number of node in x axis
    parameter NY = 4,   // number of node in y axis
    parameter C = 4,    //  number of flit class 
    parameter V=4,
    parameter B = 4,
    parameter Fpay = 32,
    parameter CRC_EN= "NO",// "YES","NO" if CRC is enable then the CRC32 of all packet data is calculated and sent via tail flit. 
    parameter SWA_ARBITER_TYPE = "RRA", // RRA WRRA
    parameter WEIGHTw          = 4, // weight width of WRRA
 
    //wishbone port parameters
    parameter Dw            =   32,
    parameter S_Aw          =   7,
    parameter M_Aw          =   32,
    parameter TAGw          =   3,
    parameter SELw          =   4
 
 
)
(
    // global 
    reset,
    clk,
 
    //noc interface  
    current_x,
    current_y,
    flit_out,
    flit_out_wr,
    credit_in,
    flit_in,
    flit_in_wr,
    credit_out,
 
    //wishbone slave control registers interface 
    ctrl_dat_i,
    ctrl_sel_i,
    ctrl_addr_i,
    ctrl_cti_i,
    ctrl_stb_i,
    ctrl_cyc_i,
    ctrl_we_i,
    ctrl_dat_o,
    ctrl_ack_o,
 
    //wishbone slave input buffer interface 
    in_dat_i,
    in_sel_i,
    in_addr_i,
    in_cti_i,
    in_stb_i,
    in_cyc_i,
    in_we_i,
    in_dat_o,
    in_ack_o,
 
    //wishbone slave output buffer interface 
    out_dat_i,
    out_sel_i,
    out_addr_i,
    out_cti_i,
    out_stb_i,
    out_cyc_i,
    out_we_i,
    out_dat_o,
    out_ack_o,
 
     //intruupt interface
    irq
);
 
 
 
 
    function integer log2;
      input integer number; begin
         log2=(number <=1) ? 1: 0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
    endfunction // log2 
 
     localparam Fw     =    2+V+Fpay, //flit width
                Xw =   log2(NX),
                Yw =   log2(NY);
 
 
    input reset,clk;
    output irq;
 
      // NOC interfaces
    input   [Xw-1   :   0]  current_x;
    input   [Yw-1   :   0]  current_y;
    output  [Fw-1   :   0]  flit_out;
    output                  flit_out_wr;
    input   [V-1    :   0]  credit_in;
    input   [Fw-1   :   0]  flit_in;
    input                   flit_in_wr;
    output  [V-1    :   0]  credit_out;
 
 
    input   [Dw-1       :   0]      ctrl_dat_i;
    input   [SELw-1     :   0]      ctrl_sel_i;
    input   [S_Aw-1     :   0]      ctrl_addr_i;
    input   [TAGw-1     :   0]      ctrl_cti_i;
    input                           ctrl_stb_i;
    input                           ctrl_cyc_i;
    input                           ctrl_we_i;
    output  [Dw-1       :   0]      ctrl_dat_o;
    output                          ctrl_ack_o;
 
 
    input   [Dw-1       :   0]      in_dat_i;
    input   [SELw-1     :   0]      in_sel_i;
    input   [S_Aw-1     :   0]      in_addr_i;
    input   [TAGw-1     :   0]      in_cti_i;
    input                           in_stb_i;
    input                           in_cyc_i;
    input                           in_we_i;
    output  [Dw-1       :   0]      in_dat_o;
    output                          in_ack_o;
 
 
    input   [Dw-1       :   0]      out_dat_i;
    input   [SELw-1     :   0]      out_sel_i;
    input   [S_Aw-1     :   0]      out_addr_i;
    input   [TAGw-1     :   0]      out_cti_i;
    input                           out_stb_i;
    input                           out_cyc_i;
    input                           out_we_i;
    output  [Dw-1       :   0]      out_dat_o;
    output                          out_ack_o;
 
 
 
    //wishbone read master interface signals
    wire  [SELw-1          :   0] m_send_sel_o;
    wire  [M_Aw-1          :   0] m_send_addr_o;
    wire  [TAGw-1          :   0] m_send_cti_o;
    wire                          m_send_stb_o;
    wire                          m_send_cyc_o;
    wire                          m_send_we_o;
    wire   [Dw-1           :  0]  m_send_dat_i;
    wire                          m_send_ack_i;
 
     //wishbone write master interface signals
    wire  [SELw-1          :   0] m_receive_sel_o;
    wire  [Dw-1            :   0] m_receive_dat_o;
    wire  [M_Aw-1          :   0] m_receive_addr_o;
    wire  [TAGw-1          :   0] m_receive_cti_o;
    wire                          m_receive_stb_o;
    wire                          m_receive_cyc_o;
    wire                          m_receive_we_o;
    wire                          m_receive_ack_i;
 
        ni_master #(
                .MAX_TRANSACTION_WIDTH(MAX_TRANSACTION_WIDTH),
                .MAX_BURST_SIZE(MAX_BURST_SIZE),
                .DEBUG_EN(DEBUG_EN),
                .CLASS_HDR_WIDTH(CLASS_HDR_WIDTH),
                .ROUTING_HDR_WIDTH(ROUTING_HDR_WIDTH),
                .DST_ADR_HDR_WIDTH(DST_ADR_HDR_WIDTH),
                .SRC_ADR_HDR_WIDTH(SRC_ADR_HDR_WIDTH),
                .TOPOLOGY(TOPOLOGY),
                .ROUTE_NAME(ROUTE_NAME),
                .NX(NX),
                .NY(NY),
                .C(C),
                .V(V),
                .B(B),
                .Fpay(Fpay),
                .CRC_EN(CRC_EN),
                .Dw(Dw),
                .S_Aw(S_Aw),
                .M_Aw(M_Aw),
                .TAGw(TAGw),
                .SELw(SELw),
                .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
                .WEIGHTw(WEIGHTw)
        )
        ni_master
        (
                .reset(reset),
                .clk(clk),
                .current_x(current_x),
                .current_y(current_y),
                .flit_out(flit_out),
                .flit_out_wr(flit_out_wr),
                .credit_in(credit_in),
                .flit_in(flit_in),
                .flit_in_wr(flit_in_wr),
                .credit_out(credit_out),
                .s_dat_i(ctrl_dat_i),
                .s_sel_i(ctrl_sel_i),
                .s_addr_i(ctrl_addr_i),
                .s_cti_i(ctrl_cti_i),
                .s_stb_i(ctrl_stb_i),
                .s_cyc_i(ctrl_cyc_i),
                .s_we_i(ctrl_we_i),
                .s_dat_o(ctrl_dat_o),
                .s_ack_o(ctrl_ack_o),
                .m_send_sel_o(m_send_sel_o),
                .m_send_addr_o(m_send_addr_o),
                .m_send_cti_o(m_send_cti_o),
                .m_send_stb_o(m_send_stb_o),
                .m_send_cyc_o(m_send_cyc_o),
                .m_send_we_o(m_send_we_o),
                .m_send_dat_i(m_send_dat_i),
                .m_send_ack_i(m_send_ack_i),
                .m_receive_sel_o(m_receive_sel_o),
                .m_receive_dat_o(m_receive_dat_o),
                .m_receive_addr_o(m_receive_addr_o),
                .m_receive_cti_o(m_receive_cti_o),
                .m_receive_stb_o(m_receive_stb_o),
                .m_receive_cyc_o(m_receive_cyc_o),
                .m_receive_we_o(m_receive_we_o),
                .m_receive_ack_i(m_receive_ack_i),
                .irq(irq)
        );
 
 
 
 
wb_dual_port_ram #(
        .INITIAL_EN("NO"),
        .Dw(Dw),
        .Aw(INPUT_MEM_Aw),
        .BYTE_WR_EN("NO"),
        .FPGA_VENDOR("GENERIC"),
        .PORT_A_BURST_MODE("ENABLED"),
        .PORT_B_BURST_MODE("ENABLED"),
        .TAGw(3),
        .SELw(4),
        .CTIw(3),
        .BTEw(2)
)
output_buffer
(
        .clk(clk),
        .reset(reset),
        .sa_dat_i(in_dat_i),
    .sb_dat_i(),
    .sa_sel_i(in_sel_i),
    .sb_sel_i(m_send_sel_o),
    .sa_addr_i(in_addr_i),
    .sb_addr_i(m_send_addr_o),
    .sa_stb_i(in_stb_i),
    .sb_stb_i(m_send_stb_o),
    .sa_cyc_i(in_cyc_i),
    .sb_cyc_i(m_send_cyc_o),
    .sa_we_i(in_we_i),
    .sb_we_i(m_send_we_o),
    .sa_cti_i(in_cti_i),
    .sb_cti_i(m_send_cti_o),
    .sa_bte_i(4'b0000),
    .sb_bte_i(4'b0000),
    .sa_dat_o(in_dat_o),
    .sb_dat_o(m_send_dat_i),
    .sa_ack_o(in_ack_o),
    .sb_ack_o(m_send_ack_i),
    .sa_tag_i(),
    .sb_tag_i(),
    .sa_err_o( ),
    .sb_err_o( ),
    .sa_rty_o( ),
    .sb_rty_o( )
);
 
 
 
wb_dual_port_ram #(
    .INITIAL_EN("NO"),
    .Dw(Dw),
    .Aw(OUTPUT_MEM_Aw),
    .BYTE_WR_EN("NO"),
    .FPGA_VENDOR("GENERIC"),
    .PORT_A_BURST_MODE("ENABLED"),
    .PORT_B_BURST_MODE("ENABLED"),
    .TAGw(3),
    .SELw(4),
    .CTIw(3),
    .BTEw(2)
)
input_buffer
(
    .clk(clk),
    .reset(reset),
    .sa_dat_i(out_dat_i),
    .sb_dat_i(m_receive_dat_o),
    .sa_sel_i(out_sel_i),
    .sb_sel_i(m_receive_sel_o),
    .sa_addr_i(out_addr_i),
    .sb_addr_i(m_receive_addr_o),
    .sa_stb_i(out_stb_i),
    .sb_stb_i(m_receive_stb_o),
    .sa_cyc_i(out_cyc_i),
    .sb_cyc_i(m_receive_cyc_o),
    .sa_we_i(out_we_i),
    .sb_we_i(m_receive_we_o),
    .sa_cti_i(out_cti_i),
    .sb_cti_i(m_receive_cti_o),
    .sa_bte_i( 4'b0000),
    .sb_bte_i( 4'b0000),
    .sa_dat_o(out_dat_o),
    .sb_dat_o(),
    .sa_ack_o(out_ack_o),
    .sb_ack_o(m_receive_ack_i),
    .sa_tag_i( ),
    .sb_tag_i( ),
    .sa_err_o( ),
    .sb_err_o( ),
    .sa_rty_o( ),
    .sb_rty_o( )
 
);
 
 
 
 
endmodule
 

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ni/] [ni_slave.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon
2			`/**********************************************************************`
3			`** File: ni_slave.v`
4			`** Date:2017-06-30`
5			`**`
6			`** Copyright (C) 2014-2017 Alireza Monemi`
7			`**`
8			`** This file is part of ProNoC`
9			`**`
10			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
11			`** you can redistribute it and/or modify it under the terms of the GNU`
12			`** Lesser General Public License as published by the Free Software Foundation,`
13			`** either version 2 of the License, or (at your option) any later version.`
14			`**`
15			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
16			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
17			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
18			`** Public License for more details.`
19			`**`
20			`** You should have received a copy of the GNU Lesser General Public`
21			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
22			`**`
23			`**`
24			`** Description:`
25			`** NI with internal input/output memory. generated using NI_master`
26			`** connected to two dualport memory`
27			`**`
28			`**`
29			`*******************************************************************/`
30
31			`// synthesis translate_off`
32			`timescale 1ns / 1ps
33			`// synthesis translate_on`
34
35
36			`module ni_slave #(`
37			`parameter MAX_TRANSACTION_WIDTH=10, // Maximum transaction size will be 2 power of MAX_DMA_TRANSACTION_WIDTH words`
38			`parameter INPUT_MEM_Aw = 10, // input memory address width`
39			`parameter OUTPUT_MEM_Aw = 10, // input memory address width`
40			`parameter MAX_BURST_SIZE =256, // in words`
41			`parameter DEBUG_EN = 1,`
42			`//NoC parameters`
43			`parameter CLASS_HDR_WIDTH =8,`
44			`parameter ROUTING_HDR_WIDTH =8,`
45			`parameter DST_ADR_HDR_WIDTH =8,`
46			`parameter SRC_ADR_HDR_WIDTH =8,`
47			`parameter TOPOLOGY = "MESH",//"MESH","TORUS","RING"`
48			`parameter ROUTE_NAME = "XY",`
49			`parameter NX = 4, // number of node in x axis`
50			`parameter NY = 4, // number of node in y axis`
51			`parameter C = 4, // number of flit class`
52			`parameter V=4,`
53			`parameter B = 4,`
54			`parameter Fpay = 32,`
55			`parameter CRC_EN= "NO",// "YES","NO" if CRC is enable then the CRC32 of all packet data is calculated and sent via tail flit.`
56			`parameter SWA_ARBITER_TYPE = "RRA", // RRA WRRA`
57			`parameter WEIGHTw = 4, // weight width of WRRA`
58
59			`//wishbone port parameters`
60			`parameter Dw = 32,`
61			`parameter S_Aw = 7,`
62			`parameter M_Aw = 32,`
63			`parameter TAGw = 3,`
64			`parameter SELw = 4`
65
66
67			`)`
68			`(`
69			`// global`
70			`reset,`
71			`clk,`
72
73			`//noc interface`
74			`current_x,`
75			`current_y,`
76			`flit_out,`
77			`flit_out_wr,`
78			`credit_in,`
79			`flit_in,`
80			`flit_in_wr,`
81			`credit_out,`
82
83			`//wishbone slave control registers interface`
84			`ctrl_dat_i,`
85			`ctrl_sel_i,`
86			`ctrl_addr_i,`
87			`ctrl_cti_i,`
88			`ctrl_stb_i,`
89			`ctrl_cyc_i,`
90			`ctrl_we_i,`
91			`ctrl_dat_o,`
92			`ctrl_ack_o,`
93
94			`//wishbone slave input buffer interface`
95			`in_dat_i,`
96			`in_sel_i,`
97			`in_addr_i,`
98			`in_cti_i,`
99			`in_stb_i,`
100			`in_cyc_i,`
101			`in_we_i,`
102			`in_dat_o,`
103			`in_ack_o,`
104
105			`//wishbone slave output buffer interface`
106			`out_dat_i,`
107			`out_sel_i,`
108			`out_addr_i,`
109			`out_cti_i,`
110			`out_stb_i,`
111			`out_cyc_i,`
112			`out_we_i,`
113			`out_dat_o,`
114			`out_ack_o,`
115
116			`//intruupt interface`
117			`irq`
118			`);`
119
120
121
122
123			`function integer log2;`
124			`input integer number; begin`
125			`log2=(number <=1) ? 1: 0;`
126			`while(2**log2<number) begin`
127			`log2=log2+1;`
128			`end`
129			`end`
130			`endfunction // log2`
131
132			`localparam Fw = 2+V+Fpay, //flit width`
133			`Xw = log2(NX),`
134			`Yw = log2(NY);`
135
136
137			`input reset,clk;`
138			`output irq;`
139
140			`// NOC interfaces`
141			`input [Xw-1 : 0] current_x;`
142			`input [Yw-1 : 0] current_y;`
143			`output [Fw-1 : 0] flit_out;`
144			`output flit_out_wr;`
145			`input [V-1 : 0] credit_in;`
146			`input [Fw-1 : 0] flit_in;`
147			`input flit_in_wr;`
148			`output [V-1 : 0] credit_out;`
149
150
151			`input [Dw-1 : 0] ctrl_dat_i;`
152			`input [SELw-1 : 0] ctrl_sel_i;`
153			`input [S_Aw-1 : 0] ctrl_addr_i;`
154			`input [TAGw-1 : 0] ctrl_cti_i;`
155			`input ctrl_stb_i;`
156			`input ctrl_cyc_i;`
157			`input ctrl_we_i;`
158			`output [Dw-1 : 0] ctrl_dat_o;`
159			`output ctrl_ack_o;`
160
161
162			`input [Dw-1 : 0] in_dat_i;`
163			`input [SELw-1 : 0] in_sel_i;`
164			`input [S_Aw-1 : 0] in_addr_i;`
165			`input [TAGw-1 : 0] in_cti_i;`
166			`input in_stb_i;`
167			`input in_cyc_i;`
168			`input in_we_i;`
169			`output [Dw-1 : 0] in_dat_o;`
170			`output in_ack_o;`
171
172
173			`input [Dw-1 : 0] out_dat_i;`
174			`input [SELw-1 : 0] out_sel_i;`
175			`input [S_Aw-1 : 0] out_addr_i;`
176			`input [TAGw-1 : 0] out_cti_i;`
177			`input out_stb_i;`
178			`input out_cyc_i;`
179			`input out_we_i;`
180			`output [Dw-1 : 0] out_dat_o;`
181			`output out_ack_o;`
182
183
184
185			`//wishbone read master interface signals`
186			`wire [SELw-1 : 0] m_send_sel_o;`
187			`wire [M_Aw-1 : 0] m_send_addr_o;`
188			`wire [TAGw-1 : 0] m_send_cti_o;`
189			`wire m_send_stb_o;`
190			`wire m_send_cyc_o;`
191			`wire m_send_we_o;`
192			`wire [Dw-1 : 0] m_send_dat_i;`
193			`wire m_send_ack_i;`
194
195			`//wishbone write master interface signals`
196			`wire [SELw-1 : 0] m_receive_sel_o;`
197			`wire [Dw-1 : 0] m_receive_dat_o;`
198			`wire [M_Aw-1 : 0] m_receive_addr_o;`
199			`wire [TAGw-1 : 0] m_receive_cti_o;`
200			`wire m_receive_stb_o;`
201			`wire m_receive_cyc_o;`
202			`wire m_receive_we_o;`
203			`wire m_receive_ack_i;`
204
205			`ni_master #(`
206			`.MAX_TRANSACTION_WIDTH(MAX_TRANSACTION_WIDTH),`
207			`.MAX_BURST_SIZE(MAX_BURST_SIZE),`
208			`.DEBUG_EN(DEBUG_EN),`
209			`.CLASS_HDR_WIDTH(CLASS_HDR_WIDTH),`
210			`.ROUTING_HDR_WIDTH(ROUTING_HDR_WIDTH),`
211			`.DST_ADR_HDR_WIDTH(DST_ADR_HDR_WIDTH),`
212			`.SRC_ADR_HDR_WIDTH(SRC_ADR_HDR_WIDTH),`
213			`.TOPOLOGY(TOPOLOGY),`
214			`.ROUTE_NAME(ROUTE_NAME),`
215			`.NX(NX),`
216			`.NY(NY),`
217			`.C(C),`
218			`.V(V),`
219			`.B(B),`
220			`.Fpay(Fpay),`
221			`.CRC_EN(CRC_EN),`
222			`.Dw(Dw),`
223			`.S_Aw(S_Aw),`
224			`.M_Aw(M_Aw),`
225			`.TAGw(TAGw),`
226			`.SELw(SELw),`
227			`.SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),`
228			`.WEIGHTw(WEIGHTw)`
229			`)`
230			`ni_master`
231			`(`
232			`.reset(reset),`
233			`.clk(clk),`
234			`.current_x(current_x),`
235			`.current_y(current_y),`
236			`.flit_out(flit_out),`
237			`.flit_out_wr(flit_out_wr),`
238			`.credit_in(credit_in),`
239			`.flit_in(flit_in),`
240			`.flit_in_wr(flit_in_wr),`
241			`.credit_out(credit_out),`
242			`.s_dat_i(ctrl_dat_i),`
243			`.s_sel_i(ctrl_sel_i),`
244			`.s_addr_i(ctrl_addr_i),`
245			`.s_cti_i(ctrl_cti_i),`
246			`.s_stb_i(ctrl_stb_i),`
247			`.s_cyc_i(ctrl_cyc_i),`
248			`.s_we_i(ctrl_we_i),`
249			`.s_dat_o(ctrl_dat_o),`
250			`.s_ack_o(ctrl_ack_o),`
251			`.m_send_sel_o(m_send_sel_o),`
252			`.m_send_addr_o(m_send_addr_o),`
253			`.m_send_cti_o(m_send_cti_o),`
254			`.m_send_stb_o(m_send_stb_o),`
255			`.m_send_cyc_o(m_send_cyc_o),`
256			`.m_send_we_o(m_send_we_o),`
257			`.m_send_dat_i(m_send_dat_i),`
258			`.m_send_ack_i(m_send_ack_i),`
259			`.m_receive_sel_o(m_receive_sel_o),`
260			`.m_receive_dat_o(m_receive_dat_o),`
261			`.m_receive_addr_o(m_receive_addr_o),`
262			`.m_receive_cti_o(m_receive_cti_o),`
263			`.m_receive_stb_o(m_receive_stb_o),`
264			`.m_receive_cyc_o(m_receive_cyc_o),`
265			`.m_receive_we_o(m_receive_we_o),`
266			`.m_receive_ack_i(m_receive_ack_i),`
267			`.irq(irq)`
268			`);`
269
270
271
272
273			`wb_dual_port_ram #(`
274			`.INITIAL_EN("NO"),`
275			`.Dw(Dw),`
276			`.Aw(INPUT_MEM_Aw),`
277			`.BYTE_WR_EN("NO"),`
278			`.FPGA_VENDOR("GENERIC"),`
279			`.PORT_A_BURST_MODE("ENABLED"),`
280			`.PORT_B_BURST_MODE("ENABLED"),`
281			`.TAGw(3),`
282			`.SELw(4),`
283			`.CTIw(3),`
284			`.BTEw(2)`
285			`)`
286			`output_buffer`
287			`(`
288			`.clk(clk),`
289			`.reset(reset),`
290			`.sa_dat_i(in_dat_i),`
291			`.sb_dat_i(),`
292			`.sa_sel_i(in_sel_i),`
293			`.sb_sel_i(m_send_sel_o),`
294			`.sa_addr_i(in_addr_i),`
295			`.sb_addr_i(m_send_addr_o),`
296			`.sa_stb_i(in_stb_i),`
297			`.sb_stb_i(m_send_stb_o),`
298			`.sa_cyc_i(in_cyc_i),`
299			`.sb_cyc_i(m_send_cyc_o),`
300			`.sa_we_i(in_we_i),`
301			`.sb_we_i(m_send_we_o),`
302			`.sa_cti_i(in_cti_i),`
303			`.sb_cti_i(m_send_cti_o),`
304			`.sa_bte_i(4'b0000),`
305			`.sb_bte_i(4'b0000),`
306			`.sa_dat_o(in_dat_o),`
307			`.sb_dat_o(m_send_dat_i),`
308			`.sa_ack_o(in_ack_o),`
309			`.sb_ack_o(m_send_ack_i),`
310			`.sa_tag_i(),`
311			`.sb_tag_i(),`
312			`.sa_err_o( ),`
313			`.sb_err_o( ),`
314			`.sa_rty_o( ),`
315			`.sb_rty_o( )`
316			`);`
317
318
319
320			`wb_dual_port_ram #(`
321			`.INITIAL_EN("NO"),`
322			`.Dw(Dw),`
323			`.Aw(OUTPUT_MEM_Aw),`
324			`.BYTE_WR_EN("NO"),`
325			`.FPGA_VENDOR("GENERIC"),`
326			`.PORT_A_BURST_MODE("ENABLED"),`
327			`.PORT_B_BURST_MODE("ENABLED"),`
328			`.TAGw(3),`
329			`.SELw(4),`
330			`.CTIw(3),`
331			`.BTEw(2)`
332			`)`
333			`input_buffer`
334			`(`
335			`.clk(clk),`
336			`.reset(reset),`
337			`.sa_dat_i(out_dat_i),`
338			`.sb_dat_i(m_receive_dat_o),`
339			`.sa_sel_i(out_sel_i),`
340			`.sb_sel_i(m_receive_sel_o),`
341			`.sa_addr_i(out_addr_i),`
342			`.sb_addr_i(m_receive_addr_o),`
343			`.sa_stb_i(out_stb_i),`
344			`.sb_stb_i(m_receive_stb_o),`
345			`.sa_cyc_i(out_cyc_i),`
346			`.sb_cyc_i(m_receive_cyc_o),`
347			`.sa_we_i(out_we_i),`
348			`.sb_we_i(m_receive_we_o),`
349			`.sa_cti_i(out_cti_i),`
350			`.sb_cti_i(m_receive_cti_o),`
351			`.sa_bte_i( 4'b0000),`
352			`.sb_bte_i( 4'b0000),`
353			`.sa_dat_o(out_dat_o),`
354			`.sb_dat_o(),`
355			`.sa_ack_o(out_ack_o),`
356			`.sb_ack_o(m_receive_ack_i),`
357			`.sa_tag_i( ),`
358			`.sb_tag_i( ),`
359			`.sa_err_o( ),`
360			`.sb_err_o( ),`
361			`.sa_rty_o( ),`
362			`.sb_rty_o( )`
363
364			`);`
365
366
367
368
369			`endmodule`
370