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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ram/] [generic_ram.v] - Blame information for rev 48

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/**********************************************************************
**      File:  generic_ram.v
**
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**      Description:
**      Generic single dual port ram
**
**
*******************************************************************/
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
 
 
/********************
*       generic_dual_port_ram
********************/
 
module generic_dual_port_ram #(
    parameter Dw=8,
    parameter Aw=6,
    parameter BYTE_WR_EN= "YES",//"YES","NO"
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
   data_a,
   data_b,
   addr_a,
   addr_b,
   byteena_a,
   byteena_b,
   we_a,
   we_b,
   clk,
   q_a,
   q_b
);
 
/* verilator lint_off WIDTH */
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
/* verilator lint_on WIDTH */
 
    input [(Dw-1):0] data_a, data_b;
    input [(Aw-1):0] addr_a, addr_b;
    input [BYTE_ENw-1   :       0]       byteena_a, byteena_b;
    input we_a, we_b, clk;
    output  [(Dw-1):0] q_a, q_b;
 
generate
/* verilator lint_off WIDTH */
if   ( BYTE_WR_EN == "NO") begin : no_byten
/* verilator lint_on WIDTH */
 
        dual_port_ram #(
                .Dw (Dw),
                .Aw (Aw),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
        )
        the_ram
        (
                .data_a     (data_a),
                .data_b     (data_b),
                .addr_a     (addr_a),
                .addr_b     (addr_b),
                .we_a           (we_a),
                .we_b           (we_b),
                .clk            (clk),
                .q_a            (q_a),
                .q_b            (q_b)
        );
 
end else begin : byten
 
   byte_enabled_true_dual_port_ram #(
                .BYTE_WIDTH(8),
                .ADDRESS_WIDTH(Aw),
                .BYTES(Dw/8),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
 
        )
        the_ram
        (
                .addr1          (addr_a),
                .addr2          (addr_b),
                .be1            (byteena_a),
                .be2            (byteena_b),
                .data_in1       (data_a),
                .data_in2       (data_b),
                .we1            (we_a),
                .we2            (we_b),
                .clk            (clk),
                .data_out1      (q_a),
                .data_out2      (q_b)
        );
 end
endgenerate
 
endmodule
 
 
 
 
 
 
/********************
*       generic_single_port_ram
********************/
 
 
 
module generic_single_port_ram #(
    parameter Dw=8,
    parameter Aw=6,
    parameter BYTE_WR_EN= "YES",//"YES","NO"
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
   data,
   addr,
   byteen,
   we,
   clk,
   q
 
);
 
    /* verilator lint_off WIDTH */
        localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
    /* verilator lint_on WIDTH */
 
        input [(Dw-1):0] data;
        input [(Aw-1):0] addr;
        input [BYTE_ENw-1       :       0]       byteen;
        input we, clk;
        output  [(Dw-1):0] q;
 
generate
/* verilator lint_off WIDTH */
if   ( BYTE_WR_EN == "NO") begin : no_byten
/* verilator lint_on WIDTH */
 
        single_port_ram #(
                .Dw (Dw),
                .Aw (Aw),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
        )
        the_ram
        (
                .data     (data),
                .addr     (addr),
                .we       (we),
                .clk      (clk),
                .q        (q)
        );
 
end else begin : byten
 
        byte_enabled_single_port_ram #(
                .BYTE_WIDTH(8),
                .ADDRESS_WIDTH(Aw),
                .BYTES(Dw/8),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
 
        )
        the_ram
        (
                .addr   (addr),
                .be     (byteen),
                .data_in(data),
                .we     (we),
                .clk    (clk),
                .data_out(q)
        );
end
endgenerate
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/*******************
 
    dual_port_ram
 
********************/
 
 
// Quartus II Verilog Template
// True Dual Port RAM with single clock
 
 
module dual_port_ram
#(
    parameter Dw=8,
    parameter Aw=6,
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file 
)
(
   data_a,
   data_b,
   addr_a,
   addr_b,
   we_a,
   we_b,
   clk,
   q_a,
   q_b
);
 
 
    input [(Dw-1):0] data_a, data_b;
    input [(Aw-1):0] addr_a, addr_b;
    input we_a, we_b, clk;
    output  reg [(Dw-1):0] q_a, q_b;
 
    // Declare the RAM variable
    reg [Dw-1:0] ram[2**Aw-1:0];
 
        // initial the memory if the file is defined
        generate
            /* verilator lint_off WIDTH */
                if (INITIAL_EN == "YES") begin : init
                /* verilator lint_on WIDTH */
                    initial $readmemh(INIT_FILE,ram);
                end
        endgenerate
 
 
    // Port A 
    always @ (posedge clk)
    begin
        if (we_a)
        begin
            ram[addr_a] <= data_a;
            q_a <= data_a;
        end
        else
        begin
            q_a <= ram[addr_a];
        end
    end
 
    // Port B 
    always @ (posedge clk)
    begin
        if (we_b)
        begin
            ram[addr_b] <= data_b;
            q_b <= data_b;
        end
        else
        begin
            q_b <= ram[addr_b];
        end
    end
 
 
 
endmodule
 
 
 
/****************
*simple_dual_port_ram
*
*****************/
 
 
 
// Quartus II Verilog Template
// Simple Dual Port RAM with separate read/write addresses and
// single read/write clock
 
module simple_dual_port_ram #(
        parameter Dw=8,
        parameter Aw=6,
        parameter INITIAL_EN= "NO",
        parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
        data,
        read_addr,
        write_addr,
        we,
        clk,
        q
);
 
        input   [Dw-1   :0] data;
        input   [Aw-1   :0] read_addr;
        input   [Aw-1   :0] write_addr;
        input we;
        input clk;
        output reg [Dw-1        :0] q;
 
 
        // Declare the RAM variable
        reg [Dw-1:0] ram [2**Aw-1:0];
 
        // initial the memory if the file is defined
        generate
           /* verilator lint_off WIDTH */
                if (INITIAL_EN == "YES") begin : init
           /* verilator lint_on WIDTH */
                    initial $readmemh(INIT_FILE,ram);
                end
        endgenerate
 
        always @ (posedge clk)
        begin
                // Write
                if (we)
                        ram[write_addr] <= data;
 
                // Read (if read_addr == write_addr, return OLD data).  To return
                // NEW data, use = (blocking write) rather than <= (non-blocking write)
                // in the write assignment.      NOTE: NEW data may require extra bypass
                // logic around the RAM.
                q <= ram[read_addr];
        end
 
endmodule
 
 
 
 
 
 
 
/*****************************
 
        single_port_ram
 
 
*****************************/
 
// Quartus II Verilog Template
// Single port RAM with single read/write address 
 
module single_port_ram #(
    parameter Dw=8,
    parameter Aw=6,
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
    data,
    addr,
    we,
    clk,
    q
);
 
    input [(Dw-1):0] data;
    input [(Aw-1):0] addr;
    input we, clk;
    output [(Dw-1):0] q;
 
    // Declare the RAM variable
    reg [Dw-1:0] ram[2**Aw-1:0];
 
        // initial the memory if the file is defined
        generate
            /* verilator lint_off WIDTH */
                if (INITIAL_EN == "YES") begin : init
                /* verilator lint_on WIDTH */
                    initial $readmemh(INIT_FILE,ram);
                end
        endgenerate
 
    // Variable to hold the registered read address
    reg [Aw-1:0] addr_reg;
 
    always @ (posedge clk)
    begin
        // Write
        if (we)
            ram[addr] <= data;
            addr_reg <= addr;
    end
 
    // Continuous assignment implies read returns NEW data.
    // This is the natural behavior of the TriMatrix memory
    // blocks in Single Port mode.  
    assign q = ram[addr_reg];
 
endmodule
 
 
 
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_peripheral/] [ram/] [generic_ram.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`/**********************************************************************`
2			`** File: generic_ram.v`
3			`**`
4			`**`
5			`** Copyright (C) 2014-2017 Alireza Monemi`
6			`**`
7			`** This file is part of ProNoC`
8			`**`
9			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
10			`** you can redistribute it and/or modify it under the terms of the GNU`
11			`** Lesser General Public License as published by the Free Software Foundation,`
12			`** either version 2 of the License, or (at your option) any later version.`
13			`**`
14			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
21			`**`
22			`**`
23			`** Description:`
24			`** Generic single dual port ram`
25			`**`
26			`**`
27			`*******************************************************************/`
28
29			`// synthesis translate_off`
30			`timescale 1ns / 1ps
31			`// synthesis translate_on`
32
33
34
35			`/********************`
36			`* generic_dual_port_ram`
37			`********************/`
38
39			`module generic_dual_port_ram #(`
40			`parameter Dw=8,`
41			`parameter Aw=6,`
42			`parameter BYTE_WR_EN= "YES",//"YES","NO"`
43			`parameter INITIAL_EN= "NO",`
44			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
45			`)`
46			`(`
47			`data_a,`
48			`data_b,`
49			`addr_a,`
50			`addr_b,`
51			`byteena_a,`
52			`byteena_b,`
53			`we_a,`
54			`we_b,`
55			`clk,`
56			`q_a,`
57			`q_b`
58			`);`
59
60			`/* verilator lint_off WIDTH */`
61			`localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;`
62			`/* verilator lint_on WIDTH */`
63
64			`input [(Dw-1):0] data_a, data_b;`
65			`input [(Aw-1):0] addr_a, addr_b;`
66			`input [BYTE_ENw-1 : 0] byteena_a, byteena_b;`
67			`input we_a, we_b, clk;`
68			`output [(Dw-1):0] q_a, q_b;`
69
70			`generate`
71			`/* verilator lint_off WIDTH */`
72			`if ( BYTE_WR_EN == "NO") begin : no_byten`
73			`/* verilator lint_on WIDTH */`
74
75			`dual_port_ram #(`
76			`.Dw (Dw),`
77			`.Aw (Aw),`
78			`.INITIAL_EN(INITIAL_EN),`
79			`.INIT_FILE(INIT_FILE)`
80			`)`
81			`the_ram`
82			`(`
83			`.data_a (data_a),`
84			`.data_b (data_b),`
85			`.addr_a (addr_a),`
86			`.addr_b (addr_b),`
87			`.we_a (we_a),`
88			`.we_b (we_b),`
89			`.clk (clk),`
90			`.q_a (q_a),`
91			`.q_b (q_b)`
92			`);`
93
94			`end else begin : byten`
95
96			`byte_enabled_true_dual_port_ram #(`
97			`.BYTE_WIDTH(8),`
98			`.ADDRESS_WIDTH(Aw),`
99			`.BYTES(Dw/8),`
100			`.INITIAL_EN(INITIAL_EN),`
101			`.INIT_FILE(INIT_FILE)`
102
103			`)`
104			`the_ram`
105			`(`
106			`.addr1 (addr_a),`
107			`.addr2 (addr_b),`
108			`.be1 (byteena_a),`
109			`.be2 (byteena_b),`
110			`.data_in1 (data_a),`
111			`.data_in2 (data_b),`
112			`.we1 (we_a),`
113			`.we2 (we_b),`
114			`.clk (clk),`
115			`.data_out1 (q_a),`
116			`.data_out2 (q_b)`
117			`);`
118			`end`
119			`endgenerate`
120
121			`endmodule`
122
123
124
125
126
127
128			`/********************`
129			`* generic_single_port_ram`
130			`********************/`
131
132
133
134			`module generic_single_port_ram #(`
135			`parameter Dw=8,`
136			`parameter Aw=6,`
137			`parameter BYTE_WR_EN= "YES",//"YES","NO"`
138			`parameter INITIAL_EN= "NO",`
139			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
140			`)`
141			`(`
142			`data,`
143			`addr,`
144			`byteen,`
145			`we,`
146			`clk,`
147			`q`
148
149			`);`
150
151			`/* verilator lint_off WIDTH */`
152			`localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;`
153			`/* verilator lint_on WIDTH */`
154
155			`input [(Dw-1):0] data;`
156			`input [(Aw-1):0] addr;`
157			`input [BYTE_ENw-1 : 0] byteen;`
158			`input we, clk;`
159			`output [(Dw-1):0] q;`
160
161			`generate`
162			`/* verilator lint_off WIDTH */`
163			`if ( BYTE_WR_EN == "NO") begin : no_byten`
164			`/* verilator lint_on WIDTH */`
165
166			`single_port_ram #(`
167			`.Dw (Dw),`
168			`.Aw (Aw),`
169			`.INITIAL_EN(INITIAL_EN),`
170			`.INIT_FILE(INIT_FILE)`
171			`)`
172			`the_ram`
173			`(`
174			`.data (data),`
175			`.addr (addr),`
176			`.we (we),`
177			`.clk (clk),`
178			`.q (q)`
179			`);`
180
181			`end else begin : byten`
182
183			`byte_enabled_single_port_ram #(`
184			`.BYTE_WIDTH(8),`
185			`.ADDRESS_WIDTH(Aw),`
186			`.BYTES(Dw/8),`
187			`.INITIAL_EN(INITIAL_EN),`
188			`.INIT_FILE(INIT_FILE)`
189
190			`)`
191			`the_ram`
192			`(`
193			`.addr (addr),`
194			`.be (byteen),`
195			`.data_in(data),`
196			`.we (we),`
197			`.clk (clk),`
198			`.data_out(q)`
199			`);`
200			`end`
201			`endgenerate`
202
203			`endmodule`
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221			`/*******************`
222
223			`dual_port_ram`
224
225			`********************/`
226
227
228			`// Quartus II Verilog Template`
229			`// True Dual Port RAM with single clock`
230
231
232			`module dual_port_ram`
233			`#(`
234			`parameter Dw=8,`
235			`parameter Aw=6,`
236			`parameter INITIAL_EN= "NO",`
237			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file`
238			`)`
239			`(`
240			`data_a,`
241			`data_b,`
242			`addr_a,`
243			`addr_b,`
244			`we_a,`
245			`we_b,`
246			`clk,`
247			`q_a,`
248			`q_b`
249			`);`
250
251
252			`input [(Dw-1):0] data_a, data_b;`
253			`input [(Aw-1):0] addr_a, addr_b;`
254			`input we_a, we_b, clk;`
255			`output reg [(Dw-1):0] q_a, q_b;`
256
257			`// Declare the RAM variable`
258			`reg [Dw-1:0] ram[2**Aw-1:0];`
259
260			`// initial the memory if the file is defined`
261			`generate`
262			`/* verilator lint_off WIDTH */`
263			`if (INITIAL_EN == "YES") begin : init`
264			`/* verilator lint_on WIDTH */`
265			`initial $readmemh(INIT_FILE,ram);`
266			`end`
267			`endgenerate`
268
269
270			`// Port A`
271			`always @ (posedge clk)`
272			`begin`
273			`if (we_a)`
274			`begin`
275			`ram[addr_a] <= data_a;`
276			`q_a <= data_a;`
277			`end`
278			`else`
279			`begin`
280			`q_a <= ram[addr_a];`
281			`end`
282			`end`
283
284			`// Port B`
285			`always @ (posedge clk)`
286			`begin`
287			`if (we_b)`
288			`begin`
289			`ram[addr_b] <= data_b;`
290			`q_b <= data_b;`
291			`end`
292			`else`
293			`begin`
294			`q_b <= ram[addr_b];`
295			`end`
296			`end`
297
298
299
300			`endmodule`
301
302
303
304			`/****************`
305			`*simple_dual_port_ram`
306			`*`
307			`*****************/`
308
309
310
311			`// Quartus II Verilog Template`
312			`// Simple Dual Port RAM with separate read/write addresses and`
313			`// single read/write clock`
314
315			`module simple_dual_port_ram #(`
316			`parameter Dw=8,`
317			`parameter Aw=6,`
318			`parameter INITIAL_EN= "NO",`
319			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
320			`)`
321			`(`
322			`data,`
323			`read_addr,`
324			`write_addr,`
325			`we,`
326			`clk,`
327			`q`
328			`);`
329
330			`input [Dw-1 :0] data;`
331			`input [Aw-1 :0] read_addr;`
332			`input [Aw-1 :0] write_addr;`
333			`input we;`
334			`input clk;`
335			`output reg [Dw-1 :0] q;`
336
337
338			`// Declare the RAM variable`
339			`reg [Dw-1:0] ram [2**Aw-1:0];`
340
341			`// initial the memory if the file is defined`
342			`generate`
343			`/* verilator lint_off WIDTH */`
344			`if (INITIAL_EN == "YES") begin : init`
345			`/* verilator lint_on WIDTH */`
346			`initial $readmemh(INIT_FILE,ram);`
347			`end`
348			`endgenerate`
349
350			`always @ (posedge clk)`
351			`begin`
352			`// Write`
353			`if (we)`
354			`ram[write_addr] <= data;`
355
356			`// Read (if read_addr == write_addr, return OLD data). To return`
357			`// NEW data, use = (blocking write) rather than <= (non-blocking write)`
358			`// in the write assignment. NOTE: NEW data may require extra bypass`
359			`// logic around the RAM.`
360			`q <= ram[read_addr];`
361			`end`
362
363			`endmodule`
364
365
366
367
368
369
370
371			`/*****************************`
372
373			`single_port_ram`
374
375
376			`*****************************/`
377
378			`// Quartus II Verilog Template`
379			`// Single port RAM with single read/write address`
380
381			`module single_port_ram #(`
382			`parameter Dw=8,`
383			`parameter Aw=6,`
384			`parameter INITIAL_EN= "NO",`
385			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
386			`)`
387			`(`
388			`data,`
389			`addr,`
390			`we,`
391			`clk,`
392			`q`
393			`);`
394
395			`input [(Dw-1):0] data;`
396			`input [(Aw-1):0] addr;`
397			`input we, clk;`
398			`output [(Dw-1):0] q;`
399
400			`// Declare the RAM variable`
401			`reg [Dw-1:0] ram[2**Aw-1:0];`
402
403			`// initial the memory if the file is defined`
404			`generate`
405			`/* verilator lint_off WIDTH */`
406			`if (INITIAL_EN == "YES") begin : init`
407			`/* verilator lint_on WIDTH */`
408			`initial $readmemh(INIT_FILE,ram);`
409			`end`
410			`endgenerate`
411
412			`// Variable to hold the registered read address`
413			`reg [Aw-1:0] addr_reg;`
414
415			`always @ (posedge clk)`
416			`begin`
417			`// Write`
418			`if (we)`
419			`ram[addr] <= data;`
420			`addr_reg <= addr;`
421			`end`
422
423			`// Continuous assignment implies read returns NEW data.`
424			`// This is the natural behavior of the TriMatrix memory`
425			`// blocks in Single Port mode.`
426			`assign q = ram[addr_reg];`
427
428			`endmodule`
429
430
431
432