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alirezamon |
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/**************************************************************************
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** WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
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** OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
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****************************************************************************/
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/**********************************************************************
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** File: /home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_topolgy/custom1/Tcustom1Rcustom_look_ahead_routing.v
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**
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** Copyright (C) 2014-2019 Alireza Monemi
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**
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** This file is part of ProNoC 1.9.1
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**
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** ProNoC ( stands for Prototype Network-on-chip) is free software:
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** you can redistribute it and/or modify it under the terms of the GNU
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** Lesser General Public License as published by the Free Software Foundation,
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** either version 2 of the License, or (at your option) any later version.
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**
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** ProNoC is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
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** Public License for more details.
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**
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** You should have received a copy of the GNU Lesser General Public
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** License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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******************************************************************************/
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/*******************
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* Tcustom1Rcustom_look_ahead_routing
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*******************/
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module Tcustom1Rcustom_look_ahead_routing #(
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parameter RAw = 3,
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parameter EAw = 3,
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parameter DSTPw=4
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)
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(
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reset,
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clk,
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current_r_addr,
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dest_e_addr,
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src_e_addr,
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destport
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);
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input [RAw-1 :0] current_r_addr;
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input [EAw-1 :0] dest_e_addr;
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input [EAw-1 :0] src_e_addr;
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output [DSTPw-1 :0] destport;
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input reset,clk;
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reg [EAw-1 :0] dest_e_addr_delay;
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reg [EAw-1 :0] src_e_addr_delay;
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always @(posedge clk)begin
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if(reset)begin
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dest_e_addr_delay<={EAw{1'b0}};
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src_e_addr_delay<={EAw{1'b0}};
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end else begin
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dest_e_addr_delay<=dest_e_addr;
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src_e_addr_delay<=src_e_addr;
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end
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end
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Tcustom1Rcustom_look_ahead_routing_comb #(
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.RAw(RAw),
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.EAw(EAw),
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.DSTPw(DSTPw)
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)
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lkp_cmb
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(
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.current_r_addr(current_r_addr),
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.dest_e_addr(dest_e_addr_delay),
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.src_e_addr(src_e_addr_delay),
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.destport(destport)
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);
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endmodule
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/*******************
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* Tcustom1Rcustom_look_ahead_routing_comb
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*******************/
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module Tcustom1Rcustom_look_ahead_routing_comb #(
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parameter RAw = 3,
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parameter EAw = 3,
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parameter DSTPw=4
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)
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(
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current_r_addr,
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dest_e_addr,
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src_e_addr,
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destport
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);
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input [RAw-1 :0] current_r_addr;
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input [EAw-1 :0] dest_e_addr;
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input [EAw-1 :0] src_e_addr;
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output reg [DSTPw-1 :0] destport;
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localparam [EAw-1 : 0] E0=0;
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localparam [EAw-1 : 0] E1=1;
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localparam [EAw-1 : 0] E2=2;
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localparam [EAw-1 : 0] E3=3;
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localparam [EAw-1 : 0] E4=4;
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localparam [EAw-1 : 0] E5=5;
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localparam [EAw-1 : 0] E6=6;
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localparam [EAw-1 : 0] E7=7;
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localparam [EAw-1 : 0] E8=8;
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localparam [EAw-1 : 0] E9=9;
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localparam [EAw-1 : 0] E10=10;
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localparam [EAw-1 : 0] E11=11;
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localparam [EAw-1 : 0] E12=12;
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localparam [EAw-1 : 0] E13=13;
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localparam [EAw-1 : 0] E14=14;
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localparam [EAw-1 : 0] E15=15;
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always@(*)begin
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destport=0;
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case(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router.
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0: begin
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case({src_e_addr,dest_e_addr})
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{E0,E9},{E0,E10}: begin
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destport= 0;
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end
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{E0,E2},{E0,E3},{E0,E8},{E0,E11},{E0,E12}: begin
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destport= 1;
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end
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{E0,E1},{E0,E4},{E0,E5},{E0,E6},{E0,E7},{E0,E13},{E0,E14},{E0,E15}: begin
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destport= 2;
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end
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default: begin
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destport= {DSTPw{1'bX}};
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end
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endcase
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end//0
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1: begin
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case({src_e_addr,dest_e_addr})
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{E1,E2},{E1,E7},{E2,E7}: begin
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destport= 0;
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end
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{E1,E3},{E1,E4},{E1,E5},{E1,E6},{E1,E8},{E1,E9},{E1,E11},{E1,E12},{E1,E13},{E1,E14},{E1,E15},{E2,E9},{E2,E12}: begin
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destport= 1;
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end
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{E1,E0},{E1,E10},{E2,E0},{E2,E10}: begin
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destport= 2;
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end
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default: begin
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destport= {DSTPw{1'bX}};
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end
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endcase
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end//1
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2: begin
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case({src_e_addr,dest_e_addr})
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{E1,E11},{E2,E1},{E2,E11}: begin
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destport= 0;
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end
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{E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E0},{E2,E4},{E2,E5},{E2,E6},{E2,E7},{E2,E8},{E2,E9},{E2,E10},{E2,E12},{E2,E13},{E2,E14},{E2,E15}: begin
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destport= 1;
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end
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{E1,E3},{E2,E3}: begin
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destport= 3;
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end
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default: begin
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destport= {DSTPw{1'bX}};
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end
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endcase
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end//2
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3: begin
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case({src_e_addr,dest_e_addr})
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{E3,E4},{E3,E11}: begin
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destport= 0;
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end
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{E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E10},{E3,E12},{E3,E13},{E3,E14}: begin
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destport= 1;
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end
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{E3,E2}: begin
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destport= 2;
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end
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{E3,E0},{E3,E5},{E3,E9},{E3,E15}: begin
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destport= 3;
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end
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default: begin
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destport= {DSTPw{1'bX}};
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end
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endcase
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end//3
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4: begin
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case({src_e_addr,dest_e_addr})
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{E3,E13},{E4,E3},{E4,E13},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin
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destport= 0;
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end
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{E4,E2},{E4,E11},{E4,E14}: begin
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destport= 1;
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end
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{E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15}: begin
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destport= 2;
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end
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{E3,E6},{E4,E6}: begin
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destport= 3;
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end
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{E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E7},{E4,E8},{E4,E10}: begin
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destport= 4;
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end
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default: begin
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destport= {DSTPw{1'bX}};
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end
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endcase
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end//4
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5: begin
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case({src_e_addr,dest_e_addr})
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{E0,E6},{E0,E15},{E3,E9},{E3,E15},{E4,E9},{E4,E15},{E5,E6},{E5,E9},{E5,E15},{E6,E9},{E6,E15},{E9,E6},{E9,E15},{E13,E9},{E14,E9},{E15,E9}: begin
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destport= 0;
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end
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{E0,E4},{E0,E13},{E4,E12},{E5,E1},{E5,E2},{E5,E3},{E5,E4},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E5,E13},{E5,E14},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin
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destport= 1;
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end
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{E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11}: begin
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destport= 2;
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end
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{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E11,E0},{E13,E0},{E15,E0}: begin
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destport= 3;
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end
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default: begin
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destport= {DSTPw{1'bX}};
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end
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endcase
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end//5
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6: begin
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| 233 |
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case({src_e_addr,dest_e_addr})
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{E0,E13},{E3,E5},{E4,E5},{E5,E13},{E6,E5},{E6,E13},{E9,E13}: begin
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destport= 0;
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end
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{E3,E15},{E4,E12},{E4,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin
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| 238 |
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destport= 1;
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end
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{E0,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E9,E3},{E9,E4}: begin
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| 241 |
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destport= 2;
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| 242 |
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end
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| 243 |
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{E3,E0},{E3,E9},{E4,E0},{E4,E9},{E6,E0},{E6,E9}: begin
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| 244 |
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destport= 3;
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| 245 |
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end
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| 246 |
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{E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14}: begin
|
| 247 |
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destport= 4;
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| 248 |
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end
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| 249 |
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default: begin
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| 250 |
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destport= {DSTPw{1'bX}};
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| 251 |
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end
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| 252 |
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endcase
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| 253 |
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end//6
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| 254 |
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7: begin
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| 255 |
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case({src_e_addr,dest_e_addr})
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| 256 |
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{E0,E1},{E1,E8},{E1,E10},{E2,E10},{E3,E1},{E3,E10},{E4,E1},{E4,E10},{E5,E1},{E6,E1},{E7,E1},{E7,E8},{E7,E10},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E11,E10},{E12,E1},{E13,E1},{E13,E10},{E14,E1},{E14,E10},{E15,E1}: begin
|
| 257 |
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destport= 0;
|
| 258 |
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end
|
| 259 |
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{E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12}: begin
|
| 260 |
|
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destport= 1;
|
| 261 |
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end
|
| 262 |
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{E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15}: begin
|
| 263 |
|
|
destport= 2;
|
| 264 |
|
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end
|
| 265 |
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{E1,E0},{E2,E0},{E7,E0},{E14,E0}: begin
|
| 266 |
|
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destport= 3;
|
| 267 |
|
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end
|
| 268 |
|
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default: begin
|
| 269 |
|
|
destport= {DSTPw{1'bX}};
|
| 270 |
|
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end
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| 271 |
|
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endcase
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| 272 |
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end//7
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| 273 |
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8: begin
|
| 274 |
|
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case({src_e_addr,dest_e_addr})
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| 275 |
|
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{E1,E12},{E2,E12},{E3,E7},{E4,E7},{E7,E12},{E7,E14},{E8,E7},{E8,E12},{E8,E14},{E9,E7},{E11,E7},{E13,E7},{E14,E7}: begin
|
| 276 |
|
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destport= 0;
|
| 277 |
|
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end
|
| 278 |
|
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{E1,E15},{E7,E5},{E7,E15},{E8,E4},{E8,E5},{E8,E15}: begin
|
| 279 |
|
|
destport= 1;
|
| 280 |
|
|
end
|
| 281 |
|
|
{E1,E4},{E1,E9},{E2,E9},{E3,E10},{E4,E10},{E7,E3},{E7,E4},{E7,E6},{E7,E9},{E7,E13},{E8,E0},{E8,E3},{E8,E6},{E8,E9},{E8,E13},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin
|
| 282 |
|
|
destport= 2;
|
| 283 |
|
|
end
|
| 284 |
|
|
{E3,E1},{E4,E1},{E8,E1},{E8,E10},{E9,E1},{E11,E1},{E13,E1},{E14,E1}: begin
|
| 285 |
|
|
destport= 3;
|
| 286 |
|
|
end
|
| 287 |
|
|
{E7,E2},{E7,E11},{E8,E2},{E8,E11}: begin
|
| 288 |
|
|
destport= 4;
|
| 289 |
|
|
end
|
| 290 |
|
|
default: begin
|
| 291 |
|
|
destport= {DSTPw{1'bX}};
|
| 292 |
|
|
end
|
| 293 |
|
|
endcase
|
| 294 |
|
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end//8
|
| 295 |
|
|
9: begin
|
| 296 |
|
|
case({src_e_addr,dest_e_addr})
|
| 297 |
|
|
{E0,E5},{E0,E12},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E9,E5},{E9,E12},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin
|
| 298 |
|
|
destport= 0;
|
| 299 |
|
|
end
|
| 300 |
|
|
{E0,E11},{E0,E14},{E0,E15},{E9,E2},{E9,E11},{E9,E15}: begin
|
| 301 |
|
|
destport= 1;
|
| 302 |
|
|
end
|
| 303 |
|
|
{E0,E4},{E0,E6},{E0,E13},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin
|
| 304 |
|
|
destport= 2;
|
| 305 |
|
|
end
|
| 306 |
|
|
{E9,E10}: begin
|
| 307 |
|
|
destport= 3;
|
| 308 |
|
|
end
|
| 309 |
|
|
{E0,E8},{E9,E1},{E9,E7},{E9,E8}: begin
|
| 310 |
|
|
destport= 4;
|
| 311 |
|
|
end
|
| 312 |
|
|
default: begin
|
| 313 |
|
|
destport= {DSTPw{1'bX}};
|
| 314 |
|
|
end
|
| 315 |
|
|
endcase
|
| 316 |
|
|
end//9
|
| 317 |
|
|
10: begin
|
| 318 |
|
|
case({src_e_addr,dest_e_addr})
|
| 319 |
|
|
{E0,E7},{E1,E0},{E2,E0},{E5,E7},{E6,E7},{E7,E0},{E10,E0},{E10,E7},{E10,E12},{E12,E7},{E14,E0},{E15,E7}: begin
|
| 320 |
|
|
destport= 0;
|
| 321 |
|
|
end
|
| 322 |
|
|
{E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15}: begin
|
| 323 |
|
|
destport= 1;
|
| 324 |
|
|
end
|
| 325 |
|
|
{E10,E9}: begin
|
| 326 |
|
|
destport= 2;
|
| 327 |
|
|
end
|
| 328 |
|
|
{E0,E1},{E5,E1},{E6,E1},{E10,E1},{E12,E1},{E15,E1}: begin
|
| 329 |
|
|
destport= 3;
|
| 330 |
|
|
end
|
| 331 |
|
|
{E10,E8}: begin
|
| 332 |
|
|
destport= 4;
|
| 333 |
|
|
end
|
| 334 |
|
|
default: begin
|
| 335 |
|
|
destport= {DSTPw{1'bX}};
|
| 336 |
|
|
end
|
| 337 |
|
|
endcase
|
| 338 |
|
|
end//10
|
| 339 |
|
|
11: begin
|
| 340 |
|
|
case({src_e_addr,dest_e_addr})
|
| 341 |
|
|
{E0,E2},{E0,E3},{E1,E3},{E1,E14},{E2,E3},{E2,E14},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E11,E3},{E11,E14},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin
|
| 342 |
|
|
destport= 0;
|
| 343 |
|
|
end
|
| 344 |
|
|
{E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15}: begin
|
| 345 |
|
|
destport= 1;
|
| 346 |
|
|
end
|
| 347 |
|
|
{E1,E6},{E2,E4},{E2,E6},{E2,E13},{E11,E4},{E11,E6},{E11,E13}: begin
|
| 348 |
|
|
destport= 2;
|
| 349 |
|
|
end
|
| 350 |
|
|
{E2,E8},{E3,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10}: begin
|
| 351 |
|
|
destport= 3;
|
| 352 |
|
|
end
|
| 353 |
|
|
default: begin
|
| 354 |
|
|
destport= {DSTPw{1'bX}};
|
| 355 |
|
|
end
|
| 356 |
|
|
endcase
|
| 357 |
|
|
end//11
|
| 358 |
|
|
12: begin
|
| 359 |
|
|
case({src_e_addr,dest_e_addr})
|
| 360 |
|
|
{E0,E8},{E1,E9},{E1,E15},{E2,E9},{E5,E8},{E5,E10},{E6,E8},{E6,E10},{E7,E9},{E8,E9},{E8,E10},{E9,E8},{E9,E10},{E10,E8},{E10,E9},{E10,E15},{E11,E9},{E12,E8},{E12,E9},{E12,E10},{E12,E15},{E15,E8},{E15,E10}: begin
|
| 361 |
|
|
destport= 0;
|
| 362 |
|
|
end
|
| 363 |
|
|
{E0,E2},{E0,E3},{E0,E11},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E2},{E10,E11},{E10,E14},{E12,E1},{E12,E2},{E12,E7},{E12,E11},{E12,E14},{E15,E1},{E15,E7}: begin
|
| 364 |
|
|
destport= 2;
|
| 365 |
|
|
end
|
| 366 |
|
|
{E8,E0},{E8,E4},{E9,E1},{E9,E7},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E0},{E12,E3},{E12,E4},{E12,E6},{E12,E13}: begin
|
| 367 |
|
|
destport= 3;
|
| 368 |
|
|
end
|
| 369 |
|
|
{E8,E5},{E10,E5},{E12,E5}: begin
|
| 370 |
|
|
destport= 4;
|
| 371 |
|
|
end
|
| 372 |
|
|
default: begin
|
| 373 |
|
|
destport= {DSTPw{1'bX}};
|
| 374 |
|
|
end
|
| 375 |
|
|
endcase
|
| 376 |
|
|
end//12
|
| 377 |
|
|
13: begin
|
| 378 |
|
|
case({src_e_addr,dest_e_addr})
|
| 379 |
|
|
{E0,E4},{E1,E4},{E1,E6},{E2,E4},{E2,E6},{E3,E6},{E3,E14},{E4,E6},{E4,E14},{E5,E4},{E5,E14},{E6,E4},{E7,E4},{E7,E6},{E8,E4},{E8,E6},{E9,E4},{E9,E14},{E10,E4},{E10,E6},{E11,E4},{E11,E6},{E12,E4},{E12,E6},{E13,E4},{E13,E6},{E13,E14},{E14,E4},{E14,E6},{E15,E4},{E15,E6}: begin
|
| 380 |
|
|
destport= 0;
|
| 381 |
|
|
end
|
| 382 |
|
|
{E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15}: begin
|
| 383 |
|
|
destport= 1;
|
| 384 |
|
|
end
|
| 385 |
|
|
{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin
|
| 386 |
|
|
destport= 2;
|
| 387 |
|
|
end
|
| 388 |
|
|
{E3,E1},{E3,E7},{E3,E8},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10}: begin
|
| 389 |
|
|
destport= 3;
|
| 390 |
|
|
end
|
| 391 |
|
|
{E4,E2},{E4,E11},{E5,E2},{E13,E2},{E13,E11}: begin
|
| 392 |
|
|
destport= 4;
|
| 393 |
|
|
end
|
| 394 |
|
|
default: begin
|
| 395 |
|
|
destport= {DSTPw{1'bX}};
|
| 396 |
|
|
end
|
| 397 |
|
|
endcase
|
| 398 |
|
|
end//13
|
| 399 |
|
|
14: begin
|
| 400 |
|
|
case({src_e_addr,dest_e_addr})
|
| 401 |
|
|
{E0,E11},{E2,E8},{E2,E13},{E2,E15},{E3,E8},{E4,E8},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E7,E13},{E7,E15},{E8,E11},{E8,E13},{E8,E15},{E9,E11},{E10,E11},{E11,E8},{E11,E13},{E11,E15},{E12,E11},{E13,E8},{E13,E11},{E13,E15},{E14,E8},{E14,E11},{E14,E13},{E14,E15},{E15,E11}: begin
|
| 402 |
|
|
destport= 0;
|
| 403 |
|
|
end
|
| 404 |
|
|
{E3,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12}: begin
|
| 405 |
|
|
destport= 1;
|
| 406 |
|
|
end
|
| 407 |
|
|
{E0,E2},{E1,E4},{E2,E4},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E7,E3},{E7,E4},{E8,E2},{E8,E3},{E9,E2},{E10,E2},{E11,E4},{E12,E2},{E13,E2},{E14,E2},{E14,E3},{E14,E4},{E15,E2}: begin
|
| 408 |
|
|
destport= 2;
|
| 409 |
|
|
end
|
| 410 |
|
|
{E0,E3},{E1,E6},{E1,E13},{E2,E6},{E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E7,E6},{E8,E6},{E11,E1},{E11,E6},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E6},{E14,E7},{E14,E10}: begin
|
| 411 |
|
|
destport= 3;
|
| 412 |
|
|
end
|
| 413 |
|
|
{E1,E5},{E2,E5},{E7,E5},{E11,E0},{E11,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9}: begin
|
| 414 |
|
|
destport= 4;
|
| 415 |
|
|
end
|
| 416 |
|
|
default: begin
|
| 417 |
|
|
destport= {DSTPw{1'bX}};
|
| 418 |
|
|
end
|
| 419 |
|
|
endcase
|
| 420 |
|
|
end//14
|
| 421 |
|
|
15: begin
|
| 422 |
|
|
case({src_e_addr,dest_e_addr})
|
| 423 |
|
|
{E0,E14},{E1,E5},{E1,E13},{E2,E5},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E6,E14},{E7,E5},{E8,E5},{E10,E5},{E10,E13},{E10,E14},{E11,E5},{E11,E12},{E12,E5},{E12,E13},{E12,E14},{E13,E5},{E13,E12},{E14,E5},{E14,E12},{E15,E5},{E15,E12},{E15,E13},{E15,E14}: begin
|
| 424 |
|
|
destport= 0;
|
| 425 |
|
|
end
|
| 426 |
|
|
{E8,E4},{E10,E3},{E10,E4},{E11,E9},{E12,E3},{E12,E4},{E15,E3},{E15,E4}: begin
|
| 427 |
|
|
destport= 2;
|
| 428 |
|
|
end
|
| 429 |
|
|
{E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E10,E6},{E11,E0},{E12,E6},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E1},{E15,E6},{E15,E7},{E15,E9},{E15,E10}: begin
|
| 430 |
|
|
destport= 3;
|
| 431 |
|
|
end
|
| 432 |
|
|
{E0,E2},{E0,E3},{E0,E11},{E5,E8},{E5,E11},{E6,E2},{E6,E8},{E6,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E15,E2},{E15,E8},{E15,E11}: begin
|
| 433 |
|
|
destport= 4;
|
| 434 |
|
|
end
|
| 435 |
|
|
default: begin
|
| 436 |
|
|
destport= {DSTPw{1'bX}};
|
| 437 |
|
|
end
|
| 438 |
|
|
endcase
|
| 439 |
|
|
end//15
|
| 440 |
|
|
default: begin
|
| 441 |
|
|
destport= {DSTPw{1'bX}};
|
| 442 |
|
|
end
|
| 443 |
|
|
endcase
|
| 444 |
|
|
end
|
| 445 |
|
|
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
endmodule
|
| 449 |
|
|
|
| 450 |
|
|
|
