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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [rtl/] [src_topolgy/] [custom1/] [custom1_noc.sv] - Blame information for rev 48

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1 48 alirezamon
 
2
/**************************************************************************
3
**      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
4
**      OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
5
****************************************************************************/
6
 
7
 
8
/**********************************************************************
9
**      File: /home/alireza/work/git/hca_git/ProNoC/mpsoc/rtl/src_topolgy/custom1/custom1_noc.sv
10
**
11
**      Copyright (C) 2014-2019  Alireza Monemi
12
**
13
**      This file is part of ProNoC 1.9.1
14
**
15
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
16
**      you can redistribute it and/or modify it under the terms of the GNU
17
**      Lesser General Public License as published by the Free Software Foundation,
18
**      either version 2 of the License, or (at your option) any later version.
19
**
20
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
21
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
22
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
23
**      Public License for more details.
24
**
25
**      You should have received a copy of the GNU Lesser General Public
26
**      License along with ProNoC. If not, see .
27
******************************************************************************/
28
 
29
module   custom1_noc
30
        import pronoc_pkg::*;
31
        (
32
        reset,
33
        clk,
34
        //T0,
35
        T0_chan_in,
36
        T0_chan_out,
37
        //T1,
38
        T1_chan_in,
39
        T1_chan_out,
40
        //T2,
41
        T2_chan_in,
42
        T2_chan_out,
43
        //T3,
44
        T3_chan_in,
45
        T3_chan_out,
46
        //T4,
47
        T4_chan_in,
48
        T4_chan_out,
49
        //T5,
50
        T5_chan_in,
51
        T5_chan_out,
52
        //T6,
53
        T6_chan_in,
54
        T6_chan_out,
55
        //T7,
56
        T7_chan_in,
57
        T7_chan_out,
58
        //T8,
59
        T8_chan_in,
60
        T8_chan_out,
61
        //T9,
62
        T9_chan_in,
63
        T9_chan_out,
64
        //T10,
65
        T10_chan_in,
66
        T10_chan_out,
67
        //T11,
68
        T11_chan_in,
69
        T11_chan_out,
70
        //T12,
71
        T12_chan_in,
72
        T12_chan_out,
73
        //T13,
74
        T13_chan_in,
75
        T13_chan_out,
76
        //T14,
77
        T14_chan_in,
78
        T14_chan_out,
79
        //T15,
80
        T15_chan_in,
81
        T15_chan_out
82
);
83
 
84
         function integer log2;
85
      input integer number; begin
86
         log2=(number <=1) ? 1: 0;
87
         while(2**log2
88
            log2=log2+1;
89
         end
90
      end
91
    endfunction // log2
92
 
93
        localparam
94
                NE = 16,
95
                NR = 16,
96
                RAw=log2(NR);
97
 
98
 
99
 
100
 
101
    input reset,clk;
102
 
103
 
104
        /*******************
105
        *               T0
106
        *******************/
107
        input  smartflit_chanel_t T0_chan_in;
108
        output smartflit_chanel_t T0_chan_out;
109
 
110
        /*******************
111
        *               T1
112
        *******************/
113
        input  smartflit_chanel_t T1_chan_in;
114
        output smartflit_chanel_t T1_chan_out;
115
 
116
        /*******************
117
        *               T2
118
        *******************/
119
        input  smartflit_chanel_t T2_chan_in;
120
        output smartflit_chanel_t T2_chan_out;
121
 
122
        /*******************
123
        *               T3
124
        *******************/
125
        input  smartflit_chanel_t T3_chan_in;
126
        output smartflit_chanel_t T3_chan_out;
127
 
128
        /*******************
129
        *               T4
130
        *******************/
131
        input  smartflit_chanel_t T4_chan_in;
132
        output smartflit_chanel_t T4_chan_out;
133
 
134
        /*******************
135
        *               T5
136
        *******************/
137
        input  smartflit_chanel_t T5_chan_in;
138
        output smartflit_chanel_t T5_chan_out;
139
 
140
        /*******************
141
        *               T6
142
        *******************/
143
        input  smartflit_chanel_t T6_chan_in;
144
        output smartflit_chanel_t T6_chan_out;
145
 
146
        /*******************
147
        *               T7
148
        *******************/
149
        input  smartflit_chanel_t T7_chan_in;
150
        output smartflit_chanel_t T7_chan_out;
151
 
152
        /*******************
153
        *               T8
154
        *******************/
155
        input  smartflit_chanel_t T8_chan_in;
156
        output smartflit_chanel_t T8_chan_out;
157
 
158
        /*******************
159
        *               T9
160
        *******************/
161
        input  smartflit_chanel_t T9_chan_in;
162
        output smartflit_chanel_t T9_chan_out;
163
 
164
        /*******************
165
        *               T10
166
        *******************/
167
        input  smartflit_chanel_t T10_chan_in;
168
        output smartflit_chanel_t T10_chan_out;
169
 
170
        /*******************
171
        *               T11
172
        *******************/
173
        input  smartflit_chanel_t T11_chan_in;
174
        output smartflit_chanel_t T11_chan_out;
175
 
176
        /*******************
177
        *               T12
178
        *******************/
179
        input  smartflit_chanel_t T12_chan_in;
180
        output smartflit_chanel_t T12_chan_out;
181
 
182
        /*******************
183
        *               T13
184
        *******************/
185
        input  smartflit_chanel_t T13_chan_in;
186
        output smartflit_chanel_t T13_chan_out;
187
 
188
        /*******************
189
        *               T14
190
        *******************/
191
        input  smartflit_chanel_t T14_chan_in;
192
        output smartflit_chanel_t T14_chan_out;
193
 
194
        /*******************
195
        *               T15
196
        *******************/
197
        input  smartflit_chanel_t T15_chan_in;
198
        output smartflit_chanel_t T15_chan_out;
199
 
200
        /*******************
201
        *               R0
202
        *******************/
203
        wire R0_clk;
204
        wire R0_reset;
205
 
206
        wire [RAw-1 :  0] R0_current_r_addr;
207
 
208
        smartflit_chanel_t    R0_chan_in   [3-1 : 0];
209
        smartflit_chanel_t    R0_chan_out  [3-1 : 0];
210
 
211
 
212
        /*******************
213
        *               R1
214
        *******************/
215
        wire R1_clk;
216
        wire R1_reset;
217
 
218
        wire [RAw-1 :  0] R1_current_r_addr;
219
 
220
        smartflit_chanel_t    R1_chan_in   [3-1 : 0];
221
        smartflit_chanel_t    R1_chan_out  [3-1 : 0];
222
 
223
 
224
        /*******************
225
        *               R2
226
        *******************/
227
        wire R2_clk;
228
        wire R2_reset;
229
 
230
        wire [RAw-1 :  0] R2_current_r_addr;
231
 
232
        smartflit_chanel_t    R2_chan_in   [3-1 : 0];
233
        smartflit_chanel_t    R2_chan_out  [3-1 : 0];
234
 
235
 
236
        /*******************
237
        *               R3
238
        *******************/
239
        wire R3_clk;
240
        wire R3_reset;
241
 
242
        wire [RAw-1 :  0] R3_current_r_addr;
243
 
244
        smartflit_chanel_t    R3_chan_in   [3-1 : 0];
245
        smartflit_chanel_t    R3_chan_out  [3-1 : 0];
246
 
247
 
248
        /*******************
249
        *               R4
250
        *******************/
251
        wire R4_clk;
252
        wire R4_reset;
253
 
254
        wire [RAw-1 :  0] R4_current_r_addr;
255
 
256
        smartflit_chanel_t    R4_chan_in   [4-1 : 0];
257
        smartflit_chanel_t    R4_chan_out  [4-1 : 0];
258
 
259
 
260
        /*******************
261
        *               R5
262
        *******************/
263
        wire R5_clk;
264
        wire R5_reset;
265
 
266
        wire [RAw-1 :  0] R5_current_r_addr;
267
 
268
        smartflit_chanel_t    R5_chan_in   [4-1 : 0];
269
        smartflit_chanel_t    R5_chan_out  [4-1 : 0];
270
 
271
 
272
        /*******************
273
        *               R6
274
        *******************/
275
        wire R6_clk;
276
        wire R6_reset;
277
 
278
        wire [RAw-1 :  0] R6_current_r_addr;
279
 
280
        smartflit_chanel_t    R6_chan_in   [4-1 : 0];
281
        smartflit_chanel_t    R6_chan_out  [4-1 : 0];
282
 
283
 
284
        /*******************
285
        *               R7
286
        *******************/
287
        wire R7_clk;
288
        wire R7_reset;
289
 
290
        wire [RAw-1 :  0] R7_current_r_addr;
291
 
292
        smartflit_chanel_t    R7_chan_in   [4-1 : 0];
293
        smartflit_chanel_t    R7_chan_out  [4-1 : 0];
294
 
295
 
296
        /*******************
297
        *               R12
298
        *******************/
299
        wire R12_clk;
300
        wire R12_reset;
301
 
302
        wire [RAw-1 :  0] R12_current_r_addr;
303
 
304
        smartflit_chanel_t    R12_chan_in   [4-1 : 0];
305
        smartflit_chanel_t    R12_chan_out  [4-1 : 0];
306
 
307
 
308
        /*******************
309
        *               R13
310
        *******************/
311
        wire R13_clk;
312
        wire R13_reset;
313
 
314
        wire [RAw-1 :  0] R13_current_r_addr;
315
 
316
        smartflit_chanel_t    R13_chan_in   [4-1 : 0];
317
        smartflit_chanel_t    R13_chan_out  [4-1 : 0];
318
 
319
 
320
        /*******************
321
        *               R14
322
        *******************/
323
        wire R14_clk;
324
        wire R14_reset;
325
 
326
        wire [RAw-1 :  0] R14_current_r_addr;
327
 
328
        smartflit_chanel_t    R14_chan_in   [4-1 : 0];
329
        smartflit_chanel_t    R14_chan_out  [4-1 : 0];
330
 
331
 
332
        /*******************
333
        *               R15
334
        *******************/
335
        wire R15_clk;
336
        wire R15_reset;
337
 
338
        wire [RAw-1 :  0] R15_current_r_addr;
339
 
340
        smartflit_chanel_t    R15_chan_in   [4-1 : 0];
341
        smartflit_chanel_t    R15_chan_out  [4-1 : 0];
342
 
343
 
344
        /*******************
345
        *               R8
346
        *******************/
347
        wire R8_clk;
348
        wire R8_reset;
349
 
350
        wire [RAw-1 :  0] R8_current_r_addr;
351
 
352
        smartflit_chanel_t    R8_chan_in   [5-1 : 0];
353
        smartflit_chanel_t    R8_chan_out  [5-1 : 0];
354
 
355
 
356
        /*******************
357
        *               R9
358
        *******************/
359
        wire R9_clk;
360
        wire R9_reset;
361
 
362
        wire [RAw-1 :  0] R9_current_r_addr;
363
 
364
        smartflit_chanel_t    R9_chan_in   [5-1 : 0];
365
        smartflit_chanel_t    R9_chan_out  [5-1 : 0];
366
 
367
 
368
        /*******************
369
        *               R10
370
        *******************/
371
        wire R10_clk;
372
        wire R10_reset;
373
 
374
        wire [RAw-1 :  0] R10_current_r_addr;
375
 
376
        smartflit_chanel_t    R10_chan_in   [5-1 : 0];
377
        smartflit_chanel_t    R10_chan_out  [5-1 : 0];
378
 
379
 
380
        /*******************
381
        *               R11
382
        *******************/
383
        wire R11_clk;
384
        wire R11_reset;
385
 
386
        wire [RAw-1 :  0] R11_current_r_addr;
387
 
388
        smartflit_chanel_t    R11_chan_in   [5-1 : 0];
389
        smartflit_chanel_t    R11_chan_out  [5-1 : 0];
390
 
391
 
392
 
393
 
394
        /*******************
395
        *               R0
396
        *******************/
397
        router_top #(
398
                .P(3)
399
        )
400
        R0
401
        (
402
                .clk(R0_clk),
403
                .reset(R0_reset),
404
                .current_r_addr  (R0_current_r_addr),
405
                .chan_in   (R0_chan_in),
406
                .chan_out  (R0_chan_out)
407
        );
408
 
409
                assign R0_clk = clk;
410
                assign R0_reset = reset;
411
                assign R0_current_r_addr = 0;
412
//Connect R0 port 0 to  T0 port 0
413
                assign R0_chan_in [0]  = T0_chan_in;
414
                assign T0_chan_out = R0_chan_out [0];
415
//Connect R0 port 1 to  R14 port 3
416
                assign R0_chan_in [1]   = R14_chan_out [3];
417
//Connect R0 port 2 to  R13 port 3
418
                assign R0_chan_in [2]   = R13_chan_out [3];
419
 
420
        /*******************
421
        *               R1
422
        *******************/
423
        router_top #(
424
                .P(3)
425
        )
426
        R1
427
        (
428
                .clk(R1_clk),
429
                .reset(R1_reset),
430
                .current_r_addr  (R1_current_r_addr),
431
                .chan_in   (R1_chan_in),
432
                .chan_out  (R1_chan_out)
433
        );
434
 
435
                assign R1_clk = clk;
436
                assign R1_reset = reset;
437
                assign R1_current_r_addr = 1;
438
//Connect R1 port 0 to  T1 port 0
439
                assign R1_chan_in [0]  = T1_chan_in;
440
                assign T1_chan_out = R1_chan_out [0];
441
//Connect R1 port 1 to  R7 port 3
442
                assign R1_chan_in [1]   = R7_chan_out [3];
443
//Connect R1 port 2 to  R2 port 2
444
                assign R1_chan_in [2]   = R2_chan_out [2];
445
 
446
        /*******************
447
        *               R2
448
        *******************/
449
        router_top #(
450
                .P(3)
451
        )
452
        R2
453
        (
454
                .clk(R2_clk),
455
                .reset(R2_reset),
456
                .current_r_addr  (R2_current_r_addr),
457
                .chan_in   (R2_chan_in),
458
                .chan_out  (R2_chan_out)
459
        );
460
 
461
                assign R2_clk = clk;
462
                assign R2_reset = reset;
463
                assign R2_current_r_addr = 2;
464
//Connect R2 port 0 to  T2 port 0
465
                assign R2_chan_in [0]  = T2_chan_in;
466
                assign T2_chan_out = R2_chan_out [0];
467
//Connect R2 port 1 to  R15 port 2
468
                assign R2_chan_in [1]   = R15_chan_out [2];
469
//Connect R2 port 2 to  R1 port 2
470
                assign R2_chan_in [2]   = R1_chan_out [2];
471
 
472
        /*******************
473
        *               R3
474
        *******************/
475
        router_top #(
476
                .P(3)
477
        )
478
        R3
479
        (
480
                .clk(R3_clk),
481
                .reset(R3_reset),
482
                .current_r_addr  (R3_current_r_addr),
483
                .chan_in   (R3_chan_in),
484
                .chan_out  (R3_chan_out)
485
        );
486
 
487
                assign R3_clk = clk;
488
                assign R3_reset = reset;
489
                assign R3_current_r_addr = 3;
490
//Connect R3 port 0 to  T3 port 0
491
                assign R3_chan_in [0]  = T3_chan_in;
492
                assign T3_chan_out = R3_chan_out [0];
493
//Connect R3 port 1 to  R15 port 3
494
                assign R3_chan_in [1]   = R15_chan_out [3];
495
//Connect R3 port 2 to  R4 port 2
496
                assign R3_chan_in [2]   = R4_chan_out [2];
497
 
498
        /*******************
499
        *               R4
500
        *******************/
501
        router_top #(
502
                .P(4)
503
        )
504
        R4
505
        (
506
                .clk(R4_clk),
507
                .reset(R4_reset),
508
                .current_r_addr  (R4_current_r_addr),
509
                .chan_in   (R4_chan_in),
510
                .chan_out  (R4_chan_out)
511
        );
512
 
513
                assign R4_clk = clk;
514
                assign R4_reset = reset;
515
                assign R4_current_r_addr = 4;
516
//Connect R4 port 0 to  T4 port 0
517
                assign R4_chan_in [0]  = T4_chan_in;
518
                assign T4_chan_out = R4_chan_out [0];
519
//Connect R4 port 1 to  R9 port 2
520
                assign R4_chan_in [1]   = R9_chan_out [2];
521
//Connect R4 port 2 to  R3 port 2
522
                assign R4_chan_in [2]   = R3_chan_out [2];
523
//Connect R4 port 3 to  R6 port 3
524
                assign R4_chan_in [3]   = R6_chan_out [3];
525
 
526
        /*******************
527
        *               R5
528
        *******************/
529
        router_top #(
530
                .P(4)
531
        )
532
        R5
533
        (
534
                .clk(R5_clk),
535
                .reset(R5_reset),
536
                .current_r_addr  (R5_current_r_addr),
537
                .chan_in   (R5_chan_in),
538
                .chan_out  (R5_chan_out)
539
        );
540
 
541
                assign R5_clk = clk;
542
                assign R5_reset = reset;
543
                assign R5_current_r_addr = 5;
544
//Connect R5 port 0 to  T5 port 0
545
                assign R5_chan_in [0]  = T5_chan_in;
546
                assign T5_chan_out = R5_chan_out [0];
547
//Connect R5 port 1 to  R11 port 4
548
                assign R5_chan_in [1]   = R11_chan_out [4];
549
//Connect R5 port 2 to  R6 port 2
550
                assign R5_chan_in [2]   = R6_chan_out [2];
551
//Connect R5 port 3 to  R13 port 2
552
                assign R5_chan_in [3]   = R13_chan_out [2];
553
 
554
        /*******************
555
        *               R6
556
        *******************/
557
        router_top #(
558
                .P(4)
559
        )
560
        R6
561
        (
562
                .clk(R6_clk),
563
                .reset(R6_reset),
564
                .current_r_addr  (R6_current_r_addr),
565
                .chan_in   (R6_chan_in),
566
                .chan_out  (R6_chan_out)
567
        );
568
 
569
                assign R6_clk = clk;
570
                assign R6_reset = reset;
571
                assign R6_current_r_addr = 6;
572
//Connect R6 port 0 to  T6 port 0
573
                assign R6_chan_in [0]  = T6_chan_in;
574
                assign T6_chan_out = R6_chan_out [0];
575
//Connect R6 port 1 to  R9 port 3
576
                assign R6_chan_in [1]   = R9_chan_out [3];
577
//Connect R6 port 2 to  R5 port 2
578
                assign R6_chan_in [2]   = R5_chan_out [2];
579
//Connect R6 port 3 to  R4 port 3
580
                assign R6_chan_in [3]   = R4_chan_out [3];
581
 
582
        /*******************
583
        *               R7
584
        *******************/
585
        router_top #(
586
                .P(4)
587
        )
588
        R7
589
        (
590
                .clk(R7_clk),
591
                .reset(R7_reset),
592
                .current_r_addr  (R7_current_r_addr),
593
                .chan_in   (R7_chan_in),
594
                .chan_out  (R7_chan_out)
595
        );
596
 
597
                assign R7_clk = clk;
598
                assign R7_reset = reset;
599
                assign R7_current_r_addr = 7;
600
//Connect R7 port 0 to  T7 port 0
601
                assign R7_chan_in [0]  = T7_chan_in;
602
                assign T7_chan_out = R7_chan_out [0];
603
//Connect R7 port 1 to  R12 port 3
604
                assign R7_chan_in [1]   = R12_chan_out [3];
605
//Connect R7 port 2 to  R14 port 2
606
                assign R7_chan_in [2]   = R14_chan_out [2];
607
//Connect R7 port 3 to  R1 port 1
608
                assign R7_chan_in [3]   = R1_chan_out [1];
609
 
610
        /*******************
611
        *               R12
612
        *******************/
613
        router_top #(
614
                .P(4)
615
        )
616
        R12
617
        (
618
                .clk(R12_clk),
619
                .reset(R12_reset),
620
                .current_r_addr  (R12_current_r_addr),
621
                .chan_in   (R12_chan_in),
622
                .chan_out  (R12_chan_out)
623
        );
624
 
625
                assign R12_clk = clk;
626
                assign R12_reset = reset;
627
                assign R12_current_r_addr = 8;
628
//Connect R12 port 0 to  T8 port 0
629
                assign R12_chan_in [0]  = T8_chan_in;
630
                assign T8_chan_out = R12_chan_out [0];
631
//Connect R12 port 1 to  R8 port 4
632
                assign R12_chan_in [1]   = R8_chan_out [4];
633
//Connect R12 port 2 to  R10 port 3
634
                assign R12_chan_in [2]   = R10_chan_out [3];
635
//Connect R12 port 3 to  R7 port 1
636
                assign R12_chan_in [3]   = R7_chan_out [1];
637
 
638
        /*******************
639
        *               R13
640
        *******************/
641
        router_top #(
642
                .P(4)
643
        )
644
        R13
645
        (
646
                .clk(R13_clk),
647
                .reset(R13_reset),
648
                .current_r_addr  (R13_current_r_addr),
649
                .chan_in   (R13_chan_in),
650
                .chan_out  (R13_chan_out)
651
        );
652
 
653
                assign R13_clk = clk;
654
                assign R13_reset = reset;
655
                assign R13_current_r_addr = 9;
656
//Connect R13 port 0 to  T9 port 0
657
                assign R13_chan_in [0]  = T9_chan_in;
658
                assign T9_chan_out = R13_chan_out [0];
659
//Connect R13 port 1 to  R8 port 2
660
                assign R13_chan_in [1]   = R8_chan_out [2];
661
//Connect R13 port 2 to  R5 port 3
662
                assign R13_chan_in [2]   = R5_chan_out [3];
663
//Connect R13 port 3 to  R0 port 2
664
                assign R13_chan_in [3]   = R0_chan_out [2];
665
 
666
        /*******************
667
        *               R14
668
        *******************/
669
        router_top #(
670
                .P(4)
671
        )
672
        R14
673
        (
674
                .clk(R14_clk),
675
                .reset(R14_reset),
676
                .current_r_addr  (R14_current_r_addr),
677
                .chan_in   (R14_chan_in),
678
                .chan_out  (R14_chan_out)
679
        );
680
 
681
                assign R14_clk = clk;
682
                assign R14_reset = reset;
683
                assign R14_current_r_addr = 10;
684
//Connect R14 port 0 to  T10 port 0
685
                assign R14_chan_in [0]  = T10_chan_in;
686
                assign T10_chan_out = R14_chan_out [0];
687
//Connect R14 port 1 to  R8 port 3
688
                assign R14_chan_in [1]   = R8_chan_out [3];
689
//Connect R14 port 2 to  R7 port 2
690
                assign R14_chan_in [2]   = R7_chan_out [2];
691
//Connect R14 port 3 to  R0 port 1
692
                assign R14_chan_in [3]   = R0_chan_out [1];
693
 
694
        /*******************
695
        *               R15
696
        *******************/
697
        router_top #(
698
                .P(4)
699
        )
700
        R15
701
        (
702
                .clk(R15_clk),
703
                .reset(R15_reset),
704
                .current_r_addr  (R15_current_r_addr),
705
                .chan_in   (R15_chan_in),
706
                .chan_out  (R15_chan_out)
707
        );
708
 
709
                assign R15_clk = clk;
710
                assign R15_reset = reset;
711
                assign R15_current_r_addr = 11;
712
//Connect R15 port 0 to  T11 port 0
713
                assign R15_chan_in [0]  = T11_chan_in;
714
                assign T11_chan_out = R15_chan_out [0];
715
//Connect R15 port 1 to  R10 port 4
716
                assign R15_chan_in [1]   = R10_chan_out [4];
717
//Connect R15 port 2 to  R2 port 1
718
                assign R15_chan_in [2]   = R2_chan_out [1];
719
//Connect R15 port 3 to  R3 port 1
720
                assign R15_chan_in [3]   = R3_chan_out [1];
721
 
722
        /*******************
723
        *               R8
724
        *******************/
725
        router_top #(
726
                .P(5)
727
        )
728
        R8
729
        (
730
                .clk(R8_clk),
731
                .reset(R8_reset),
732
                .current_r_addr  (R8_current_r_addr),
733
                .chan_in   (R8_chan_in),
734
                .chan_out  (R8_chan_out)
735
        );
736
 
737
                assign R8_clk = clk;
738
                assign R8_reset = reset;
739
                assign R8_current_r_addr = 12;
740
//Connect R8 port 0 to  T12 port 0
741
                assign R8_chan_in [0]  = T12_chan_in;
742
                assign T12_chan_out = R8_chan_out [0];
743
//Connect R8 port 1 to  R11 port 1
744
                assign R8_chan_in [1]   = R11_chan_out [1];
745
//Connect R8 port 2 to  R13 port 1
746
                assign R8_chan_in [2]   = R13_chan_out [1];
747
//Connect R8 port 3 to  R14 port 1
748
                assign R8_chan_in [3]   = R14_chan_out [1];
749
//Connect R8 port 4 to  R12 port 1
750
                assign R8_chan_in [4]   = R12_chan_out [1];
751
 
752
        /*******************
753
        *               R9
754
        *******************/
755
        router_top #(
756
                .P(5)
757
        )
758
        R9
759
        (
760
                .clk(R9_clk),
761
                .reset(R9_reset),
762
                .current_r_addr  (R9_current_r_addr),
763
                .chan_in   (R9_chan_in),
764
                .chan_out  (R9_chan_out)
765
        );
766
 
767
                assign R9_clk = clk;
768
                assign R9_reset = reset;
769
                assign R9_current_r_addr = 13;
770
//Connect R9 port 0 to  T13 port 0
771
                assign R9_chan_in [0]  = T13_chan_in;
772
                assign T13_chan_out = R9_chan_out [0];
773
//Connect R9 port 1 to  R11 port 3
774
                assign R9_chan_in [1]   = R11_chan_out [3];
775
//Connect R9 port 2 to  R4 port 1
776
                assign R9_chan_in [2]   = R4_chan_out [1];
777
//Connect R9 port 3 to  R6 port 1
778
                assign R9_chan_in [3]   = R6_chan_out [1];
779
//Connect R9 port 4 to  R10 port 2
780
                assign R9_chan_in [4]   = R10_chan_out [2];
781
 
782
        /*******************
783
        *               R10
784
        *******************/
785
        router_top #(
786
                .P(5)
787
        )
788
        R10
789
        (
790
                .clk(R10_clk),
791
                .reset(R10_reset),
792
                .current_r_addr  (R10_current_r_addr),
793
                .chan_in   (R10_chan_in),
794
                .chan_out  (R10_chan_out)
795
        );
796
 
797
                assign R10_clk = clk;
798
                assign R10_reset = reset;
799
                assign R10_current_r_addr = 14;
800
//Connect R10 port 0 to  T14 port 0
801
                assign R10_chan_in [0]  = T14_chan_in;
802
                assign T14_chan_out = R10_chan_out [0];
803
//Connect R10 port 1 to  R11 port 2
804
                assign R10_chan_in [1]   = R11_chan_out [2];
805
//Connect R10 port 2 to  R9 port 4
806
                assign R10_chan_in [2]   = R9_chan_out [4];
807
//Connect R10 port 3 to  R12 port 2
808
                assign R10_chan_in [3]   = R12_chan_out [2];
809
//Connect R10 port 4 to  R15 port 1
810
                assign R10_chan_in [4]   = R15_chan_out [1];
811
 
812
        /*******************
813
        *               R11
814
        *******************/
815
        router_top #(
816
                .P(5)
817
        )
818
        R11
819
        (
820
                .clk(R11_clk),
821
                .reset(R11_reset),
822
                .current_r_addr  (R11_current_r_addr),
823
                .chan_in   (R11_chan_in),
824
                .chan_out  (R11_chan_out)
825
        );
826
 
827
                assign R11_clk = clk;
828
                assign R11_reset = reset;
829
                assign R11_current_r_addr = 15;
830
//Connect R11 port 0 to  T15 port 0
831
                assign R11_chan_in [0]  = T15_chan_in;
832
                assign T15_chan_out = R11_chan_out [0];
833
//Connect R11 port 1 to  R8 port 1
834
                assign R11_chan_in [1]   = R8_chan_out [1];
835
//Connect R11 port 2 to  R10 port 1
836
                assign R11_chan_in [2]   = R10_chan_out [1];
837
//Connect R11 port 3 to  R9 port 1
838
                assign R11_chan_in [3]   = R9_chan_out [1];
839
//Connect R11 port 4 to  R5 port 1
840
                assign R11_chan_in [4]   = R5_chan_out [1];
841
 
842
 
843
 
844
 
845
endmodule

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