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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [script/] [model.tcl] - Blame information for rev 43

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Line No. Rev Author Line
1 16 alirezamon 
#!/usr/bin/tclsh
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###################################################################
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## Author      : Alireza Monemi
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## Email       :
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## Description : Compile all verilog files inside the design folder
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##             : using modelsim
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###################################################################
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set text "###################################################################"
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set text "##                Start Compilation Script "
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set text "###################################################################"
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###################################################################
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##---- Specify variables
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set text "###################################################################"
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set text "##---- Specify variables"
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##-- Project path variables
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set path                        [pwd]/..
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set src_noc_path                        $path/src_noc
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set src_modelsim_path                   $path/src_modelsim
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set comp_path                   $path/../mpsoc_work/modelsim
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set work_path                   $comp_path/work
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set file_list [glob -directory $src_noc_path *.v]
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set modelsim_file_list [glob -directory $src_modelsim_path *.v]
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##-- change directory
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file mkdir $comp_path
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cd $comp_path
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exec rm -Rf *
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proc r  {} {uplevel #0 source compile.tcl}
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proc rr {} {global last_compile_time
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            set last_compile_time 0
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            r                            }
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proc q  {} {quit -force                  }
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proc sleep {N} {
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    after [expr {int($N * 1000)}]
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}
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#Does this installation support Tk?
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set tk_ok 1
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if [catch {package require Tk}] {set tk_ok 0}
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###################################################################
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##---- 1. Creating working library
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set text "###################################################################"
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set text "##---- 1. Creating working library"
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##-- Create work lib
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vlib $work_path
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##-- Mapping work lib
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vmap work $work_path
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###################################################################
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##---- 3. Compile the Design
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set text "###################################################################"
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set text "##---- 3. Compile the Design"
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# Compile out of date files
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set time_now [clock seconds]
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if {[file isfile start_time.txt] != 0} {
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        set fp [open start_time.txt r]
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        set line [gets $fp]
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        close $fp
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        regexp {\d+} $line last_compile_time
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        puts "last compiled time is  $last_compile_time"
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} else {
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        set last_compile_time 0
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}
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set last_compile_time 0
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foreach f $file_list {
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                if { $last_compile_time < [file mtime $f] } {
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                        vlog -work  $work_path  +incdir+$src_noc_path  $f
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                         set last_compile_time 0
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                } else {
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                         puts "$f is uptodate"
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                }
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        }
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foreach f $modelsim_file_list {
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                if { $last_compile_time < [file mtime $f] } {
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                        vlog -work  $work_path  +incdir+$src_modelsim_path  $f
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                         set last_compile_time 0
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                } else {
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                         puts "$f is uptodate"
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                }
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        }
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set last_compile_time $time_now
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set text "###################################################################"
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set text "##                       END OF COMPILATION"
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set text "###################################################################"
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111 38 alirezamon 
#vsim -t ps work.testbench_router
112 16 alirezamon 
vsim  -t ps  work.testbench_modelsim
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run 100 ms
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#save last compile time
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  set fp [open start_time.txt w]
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  puts $fp "Start time was [clock seconds]"
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  close $fp
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#q
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#####################################################################################
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