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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_led_test/] [src/] [top.v] - Blame information for rev 38

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module top (
        LED
);
        output [6:0] LED;
 
        wire [1:0] jtag_out;
 
        jtag_control_port #(
                .VJTAG_INDEX(127),
                .DW(2)
        )
        uut
        (
                .jtag_out(jtag_out)
        );
 
        assign LED[0]=jtag_out[0];
        assign LED[1]=jtag_out[1];
 
 
endmodule
 
 
 
 
 
module jtag_control_port #(
        parameter VJTAG_INDEX=127,
        parameter DW=2
 
)(
        jtag_out
);
 
 
        output [DW-1    :       0] jtag_out;
 
 
 
        //vjtag vjtag signals declaration
        wire    [2:0]  ir_out ,  ir_in;
        wire      tdo, tck,       tdi;
        wire      cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
 
 
        vjtag   #(
         .VJTAG_INDEX(VJTAG_INDEX)
        )
        vjtag_inst (
        .ir_out ( ir_out ),
        .tdo ( tdo ),
        .ir_in ( ir_in ),
        .tck ( tck ),
        .tdi ( tdi ),
        .virtual_state_cdr      ( cdr ),
        .virtual_state_cir      ( cir ),
        .virtual_state_e1dr     ( e1dr ),
        .virtual_state_e2dr     ( e2dr ),
        .virtual_state_pdr      ( pdr ),
        .virtual_state_sdr      ( sdr ),
        .virtual_state_udr      ( udr ),
        .virtual_state_uir      ( uir )
        );
 
 
        // IR states
 
 
 
        reg [2:0] ir;
        reg bypass_reg;
        reg [DW-1       :       0] shift_buffer,shift_buffer_next;
        reg cdr_delayed,sdr_delayed;
        reg [DW-1       :       0] status,status_next;
 
        assign jtag_out = status ;
 /*
        always @(negedge tck)
        begin
                //  Delay the CDR signal by one half clock cycle
                cdr_delayed = cdr;
                sdr_delayed = sdr;
        end
        */
 
        assign ir_out = ir_in;  // Just pass the IR out
        assign tdo = (ir == 3'b000) ? bypass_reg : shift_buffer[0];
 
 
 
 
 
        always @(posedge tck )
        begin
                        if( uir ) ir <= ir_in; // Capture the instruction provided
                        bypass_reg <= tdi;
                        shift_buffer<=shift_buffer_next;
                        status<=status_next;
 
        end
 
generate
        if(DW==1)begin :DW1
                always @ (*)begin
                        shift_buffer_next=shift_buffer;
                        status_next = status;
                        if( sdr ) shift_buffer_next= tdi; //,shift_buffer[DW-1:1]};// shift buffer
                        if((ir == 3'b001) &  cdr ) shift_buffer_next  = status;
                        if((ir == 3'b001) &  udr ) status_next = shift_buffer;
                end
        end
        else begin :DWB
                always @ (*)begin
                        shift_buffer_next=shift_buffer;
                        status_next = status;
                        if( sdr ) shift_buffer_next= {tdi, shift_buffer[DW-1:1]};// shift buffer
                        if((ir == 3'b001) &  cdr ) shift_buffer_next  = status;
                        if((ir == 3'b001) &  udr ) status_next = shift_buffer;
                end
 
        end
endgenerate
 
 
endmodule

Line No.	Rev	Author	Line
1	38	alirezamon	`module top (`
2			`LED`
3			`);`
4			`output [6:0] LED;`
5
6			`wire [1:0] jtag_out;`
7
8			`jtag_control_port #(`
9			`.VJTAG_INDEX(127),`
10			`.DW(2)`
11			`)`
12			`uut`
13			`(`
14			`.jtag_out(jtag_out)`
15			`);`
16
17			`assign LED[0]=jtag_out[0];`
18			`assign LED[1]=jtag_out[1];`
19
20
21			`endmodule`
22
23
24
25
26
27			`module jtag_control_port #(`
28			`parameter VJTAG_INDEX=127,`
29			`parameter DW=2`
30
31			`)(`
32			`jtag_out`
33			`);`
34
35
36			`output [DW-1 : 0] jtag_out;`
37
38
39
40			`//vjtag vjtag signals declaration`
41			`wire [2:0] ir_out , ir_in;`
42			`wire tdo, tck, tdi;`
43			`wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;`
44
45
46			`vjtag #(`
47			`.VJTAG_INDEX(VJTAG_INDEX)`
48			`)`
49			`vjtag_inst (`
50			`.ir_out ( ir_out ),`
51			`.tdo ( tdo ),`
52			`.ir_in ( ir_in ),`
53			`.tck ( tck ),`
54			`.tdi ( tdi ),`
55			`.virtual_state_cdr ( cdr ),`
56			`.virtual_state_cir ( cir ),`
57			`.virtual_state_e1dr ( e1dr ),`
58			`.virtual_state_e2dr ( e2dr ),`
59			`.virtual_state_pdr ( pdr ),`
60			`.virtual_state_sdr ( sdr ),`
61			`.virtual_state_udr ( udr ),`
62			`.virtual_state_uir ( uir )`
63			`);`
64
65
66			`// IR states`
67
68
69
70			`reg [2:0] ir;`
71			`reg bypass_reg;`
72			`reg [DW-1 : 0] shift_buffer,shift_buffer_next;`
73			`reg cdr_delayed,sdr_delayed;`
74			`reg [DW-1 : 0] status,status_next;`
75
76			`assign jtag_out = status ;`
77			`/*`
78			`always @(negedge tck)`
79			`begin`
80			`// Delay the CDR signal by one half clock cycle`
81			`cdr_delayed = cdr;`
82			`sdr_delayed = sdr;`
83			`end`
84			`*/`
85
86			`assign ir_out = ir_in; // Just pass the IR out`
87			`assign tdo = (ir == 3'b000) ? bypass_reg : shift_buffer[0];`
88
89
90
91
92
93			`always @(posedge tck )`
94			`begin`
95			`if( uir ) ir <= ir_in; // Capture the instruction provided`
96			`bypass_reg <= tdi;`
97			`shift_buffer<=shift_buffer_next;`
98			`status<=status_next;`
99
100			`end`
101
102			`generate`
103			`if(DW==1)begin :DW1`
104			`always @ (*)begin`
105			`shift_buffer_next=shift_buffer;`
106			`status_next = status;`
107			`if( sdr ) shift_buffer_next= tdi; //,shift_buffer[DW-1:1]};// shift buffer`
108			`if((ir == 3'b001) & cdr ) shift_buffer_next = status;`
109			`if((ir == 3'b001) & udr ) status_next = shift_buffer;`
110			`end`
111			`end`
112			`else begin :DWB`
113			`always @ (*)begin`
114			`shift_buffer_next=shift_buffer;`
115			`status_next = status;`
116			`if( sdr ) shift_buffer_next= {tdi, shift_buffer[DW-1:1]};// shift buffer`
117			`if((ir == 3'b001) & cdr ) shift_buffer_next = status;`
118			`if((ir == 3'b001) & udr ) status_next = shift_buffer;`
119			`end`
120
121			`end`
122			`endgenerate`
123
124
125			`endmodule`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_led_test/] [src/] [top.v] - Blame information for rev 38