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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [Top.v] - Blame information for rev 38

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1 38 alirezamon
 
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/**********************************************************************
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**      File: Top.v
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**
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**      Copyright (C) 2014-2018  Alireza Monemi
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**
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**      This file is part of ProNoC 1.7.0
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**
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**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
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**      you can redistribute it and/or modify it under the terms of the GNU
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**      Lesser General Public License as published by the Free Software Foundation,
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**      either version 2 of the License, or (at your option) any later version.
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**
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**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
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**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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**      Public License for more details.
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**
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**      You should have received a copy of the GNU Lesser General Public
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**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
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******************************************************************************/
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module Top (
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        FPGA_CLK1_50,
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        KEY
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);
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         input                   FPGA_CLK1_50;
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         input  [1 : 0]   KEY;
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        ram_test_top uut(
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          .ss_clk_in( FPGA_CLK1_50  ),
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          .ss_reset_in(~ KEY [ 0])
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        );
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endmodule

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