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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [clk_source.v] - Blame information for rev 38

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`timescale 1ns / 1ps
 
module clk_source (
        input   reset_in,
        input   clk_in,
        output  reset_out,
        output  clk_out
 
);
 
 
        altera_reset_synchronizer sync(
 
                .reset_in       (reset_in),
                .clk            (clk_in),
                .reset_out      (reset_out)
        );
 
        assign clk_out=clk_in;
 
 
endmodule
 
 
 
 

Line No.	Rev	Author	Line
1	38	alirezamon	`timescale 1ns / 1ps
2
3			`module clk_source (`
4			`input reset_in,`
5			`input clk_in,`
6			`output reset_out,`
7			`output clk_out`
8
9			`);`
10
11
12			`altera_reset_synchronizer sync(`
13
14			`.reset_in (reset_in),`
15			`.clk (clk_in),`
16			`.reset_out (reset_out)`
17			`);`
18
19			`assign clk_out=clk_in;`
20
21
22			`endmodule`
23
24
25
26

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [clk_source.v] - Blame information for rev 38