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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [generic_ram.v] - Blame information for rev 38

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1 38 alirezamon 
/**********************************************************************
2 
**      File:  generic_ram.v
3 
**
4 
**
5 
**      Copyright (C) 2014-2017  Alireza Monemi
6 
**
7 
**      This file is part of ProNoC
8 
**
9 
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
10 
**      you can redistribute it and/or modify it under the terms of the GNU
11 
**      Lesser General Public License as published by the Free Software Foundation,
12 
**      either version 2 of the License, or (at your option) any later version.
13 
**
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**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
15 
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
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**      Public License for more details.
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**
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**      You should have received a copy of the GNU Lesser General Public
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**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
21 
**
22 
**
23 
**      Description:
24 
**      Generic single dual port ram
25 
**
26 
**
27 
*******************************************************************/
28 
 
29 
`timescale 1ns / 1ps
30 
 
31 
 
32 
/********************
33 
*       generic_dual_port_ram
34 
********************/
35 
 
36 
module generic_dual_port_ram #(
37 
    parameter Dw=8,
38 
    parameter Aw=6,
39 
    parameter BYTE_WR_EN= "YES",//"YES","NO"
40 
    parameter INITIAL_EN= "NO",
41 
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
42 
)
43 
(
44 
   data_a,
45 
   data_b,
46 
   addr_a,
47 
   addr_b,
48 
   byteena_a,
49 
   byteena_b,
50 
   we_a,
51 
   we_b,
52 
   clk,
53 
   q_a,
54 
   q_b
55 
);
56 
 
57 
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
58 
 
59 
    input [(Dw-1):0] data_a, data_b;
60 
    input [(Aw-1):0] addr_a, addr_b;
61 
    input [BYTE_ENw-1   :       0]       byteena_a, byteena_b;
62 
    input we_a, we_b, clk;
63 
    output  [(Dw-1):0] q_a, q_b;
64 
 
65 
generate
66 
if   ( BYTE_WR_EN == "NO") begin : no_byten
67 
 
68 
        dual_port_ram #(
69 
                .Dw (Dw),
70 
                .Aw (Aw),
71 
                .INITIAL_EN(INITIAL_EN),
72 
                .INIT_FILE(INIT_FILE)
73 
        )
74 
        the_ram
75 
        (
76 
                .data_a     (data_a),
77 
                .data_b     (data_b),
78 
                .addr_a     (addr_a),
79 
                .addr_b     (addr_b),
80 
                .we_a           (we_a),
81 
                .we_b           (we_b),
82 
                .clk            (clk),
83 
                .q_a            (q_a),
84 
                .q_b            (q_b)
85 
        );
86 
 
87 
end else begin : byten
88 
 
89 
   byte_enabled_true_dual_port_ram #(
90 
                .BYTE_WIDTH(8),
91 
                .ADDRESS_WIDTH(Aw),
92 
                .BYTES(Dw/8),
93 
                .INITIAL_EN(INITIAL_EN),
94 
                .INIT_FILE(INIT_FILE)
95 
 
96 
        )
97 
        the_ram
98 
        (
99 
                .addr1          (addr_a),
100 
                .addr2          (addr_b),
101 
                .be1            (byteena_a),
102 
                .be2            (byteena_b),
103 
                .data_in1       (data_a),
104 
                .data_in2       (data_b),
105 
                .we1            (we_a),
106 
                .we2            (we_b),
107 
                .clk            (clk),
108 
                .data_out1      (q_a),
109 
                .data_out2      (q_b)
110 
        );
111 
 end
112 
endgenerate
113 
 
114 
endmodule
115 
 
116 
 
117 
 
118 
 
119 
 
120 
 
121 
/********************
122 
*       generic_single_port_ram
123 
********************/
124 
 
125 
 
126 
 
127 
module generic_single_port_ram #(
128 
    parameter Dw=8,
129 
    parameter Aw=6,
130 
    parameter BYTE_WR_EN= "YES",//"YES","NO"
131 
    parameter INITIAL_EN= "NO",
132 
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
133 
)
134 
(
135 
   data,
136 
   addr,
137 
   byteen,
138 
   we,
139 
   clk,
140 
   q
141 
 
142 
);
143 
 
144 
        localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
145 
 
146 
        input [(Dw-1):0] data;
147 
        input [(Aw-1):0] addr;
148 
        input [BYTE_ENw-1       :       0]       byteen;
149 
        input we, clk;
150 
        output  [(Dw-1):0] q;
151 
 
152 
generate
153 
if   ( BYTE_WR_EN == "NO") begin : no_byten
154 
 
155 
 
156 
        single_port_ram #(
157 
                .Dw (Dw),
158 
                .Aw (Aw),
159 
                .INITIAL_EN(INITIAL_EN),
160 
                .INIT_FILE(INIT_FILE)
161 
        )
162 
        the_ram
163 
        (
164 
                .data     (data),
165 
                .addr     (addr),
166 
                .we       (we),
167 
                .clk      (clk),
168 
                .q        (q)
169 
        );
170 
 
171 
end else begin : byten
172 
 
173 
        byte_enabled_single_port_ram #(
174 
                .BYTE_WIDTH(8),
175 
                .ADDRESS_WIDTH(Aw),
176 
                .BYTES(Dw/8),
177 
                .INITIAL_EN(INITIAL_EN),
178 
                .INIT_FILE(INIT_FILE)
179 
 
180 
        )
181 
        the_ram
182 
        (
183 
                .addr   (addr),
184 
                .be     (byteen),
185 
                .data_in(data),
186 
                .we     (we),
187 
                .clk    (clk),
188 
                .data_out(q)
189 
        );
190 
end
191 
endgenerate
192 
 
193 
endmodule
194 
 
195 
 
196 
 
197 
 
198 
 
199 
 
200 
 
201 
 
202 
 
203 
 
204 
 
205 
 
206 
 
207 
 
208 
 
209 
 
210 
 
211 
/*******************
212 
 
213 
    dual_port_ram
214 
 
215 
********************/
216 
 
217 
 
218 
// Quartus II Verilog Template
219 
// True Dual Port RAM with single clock
220 
 
221 
 
222 
module dual_port_ram
223 
#(
224 
    parameter Dw=8,
225 
    parameter Aw=6,
226 
    parameter INITIAL_EN= "NO",
227 
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file
228 
)
229 
(
230 
   data_a,
231 
   data_b,
232 
   addr_a,
233 
   addr_b,
234 
   we_a,
235 
   we_b,
236 
   clk,
237 
   q_a,
238 
   q_b
239 
);
240 
 
241 
 
242 
    input [(Dw-1):0] data_a, data_b;
243 
    input [(Aw-1):0] addr_a, addr_b;
244 
    input we_a, we_b, clk;
245 
    output  reg [(Dw-1):0] q_a, q_b;
246 
 
247 
    // Declare the RAM variable
248 
    reg [Dw-1:0] ram[2**Aw-1:0];
249 
 
250 
        // initial the memory if the file is defined
251 
        generate
252 
                if (INITIAL_EN == "YES") begin : init
253 
                    initial $readmemh(INIT_FILE,ram);
254 
                end
255 
        endgenerate
256 
 
257 
 
258 
    // Port A
259 
    always @ (posedge clk)
260 
    begin
261 
        if (we_a)
262 
        begin
263 
            ram[addr_a] <= data_a;
264 
            q_a <= data_a;
265 
        end
266 
        else
267 
        begin
268 
            q_a <= ram[addr_a];
269 
        end
270 
    end
271 
 
272 
    // Port B
273 
    always @ (posedge clk)
274 
    begin
275 
        if (we_b)
276 
        begin
277 
            ram[addr_b] <= data_b;
278 
            q_b <= data_b;
279 
        end
280 
        else
281 
        begin
282 
            q_b <= ram[addr_b];
283 
        end
284 
    end
285 
 
286 
 
287 
 
288 
endmodule
289 
 
290 
 
291 
 
292 
/****************
293 
*simple_dual_port_ram
294 
*
295 
*****************/
296 
 
297 
 
298 
 
299 
// Quartus II Verilog Template
300 
// Simple Dual Port RAM with separate read/write addresses and
301 
// single read/write clock
302 
 
303 
module simple_dual_port_ram #(
304 
        parameter Dw=8,
305 
        parameter Aw=6,
306 
        parameter INITIAL_EN= "NO",
307 
        parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
308 
)
309 
(
310 
        data,
311 
        read_addr,
312 
        write_addr,
313 
        we,
314 
        clk,
315 
        q
316 
);
317 
 
318 
        input   [Dw-1   :0] data;
319 
        input   [Aw-1   :0] read_addr;
320 
        input   [Aw-1   :0] write_addr;
321 
        input we;
322 
        input clk;
323 
        output reg [Dw-1        :0] q;
324 
 
325 
 
326 
        // Declare the RAM variable
327 
        reg [Dw-1:0] ram [2**Aw-1:0];
328 
 
329 
        // initial the memory if the file is defined
330 
        generate
331 
                if (INITIAL_EN == "YES") begin : init
332 
                    initial $readmemh(INIT_FILE,ram);
333 
                end
334 
        endgenerate
335 
 
336 
        always @ (posedge clk)
337 
        begin
338 
                // Write
339 
                if (we)
340 
                        ram[write_addr] <= data;
341 
 
342 
                // Read (if read_addr == write_addr, return OLD data).  To return
343 
                // NEW data, use = (blocking write) rather than <= (non-blocking write)
344 
                // in the write assignment.      NOTE: NEW data may require extra bypass
345 
                // logic around the RAM.
346 
                q <= ram[read_addr];
347 
        end
348 
 
349 
endmodule
350 
 
351 
 
352 
 
353 
 
354 
 
355 
 
356 
 
357 
/*****************************
358 
 
359 
        single_port_ram
360 
 
361 
 
362 
*****************************/
363 
 
364 
// Quartus II Verilog Template
365 
// Single port RAM with single read/write address
366 
 
367 
module single_port_ram #(
368 
    parameter Dw=8,
369 
    parameter Aw=6,
370 
    parameter INITIAL_EN= "NO",
371 
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
372 
)
373 
(
374 
    data,
375 
    addr,
376 
    we,
377 
    clk,
378 
    q
379 
);
380 
 
381 
    input [(Dw-1):0] data;
382 
    input [(Aw-1):0] addr;
383 
    input we, clk;
384 
    output [(Dw-1):0] q;
385 
 
386 
    // Declare the RAM variable
387 
    reg [Dw-1:0] ram[2**Aw-1:0];
388 
 
389 
        // initial the memory if the file is defined
390 
        generate
391 
                if (INITIAL_EN == "YES") begin : init
392 
                    initial $readmemh(INIT_FILE,ram);
393 
                end
394 
        endgenerate
395 
 
396 
    // Variable to hold the registered read address
397 
    reg [Aw-1:0] addr_reg;
398 
 
399 
    always @ (posedge clk)
400 
    begin
401 
        // Write
402 
        if (we)
403 
            ram[addr] <= data;
404 
            addr_reg <= addr;
405 
    end
406 
 
407 
    // Continuous assignment implies read returns NEW data.
408 
    // This is the natural behavior of the TriMatrix memory
409 
    // blocks in Single Port mode.
410 
    assign q = ram[addr_reg];
411 
 
412 
endmodule
413 
 
414 
 
415 
 
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