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/**********************************************************************
**      File:  generic_ram.v
**
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**      Description:
**      Generic single dual port ram
**
**
*******************************************************************/
 
`timescale 1ns / 1ps
 
 
/********************
*       generic_dual_port_ram
********************/
 
module generic_dual_port_ram #(
    parameter Dw=8,
    parameter Aw=6,
    parameter BYTE_WR_EN= "YES",//"YES","NO"
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
   data_a,
   data_b,
   addr_a,
   addr_b,
   byteena_a,
   byteena_b,
   we_a,
   we_b,
   clk,
   q_a,
   q_b
);
 
/* verilator lint_off WIDTH */
localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
/* verilator lint_on WIDTH */
 
    input [(Dw-1):0] data_a, data_b;
    input [(Aw-1):0] addr_a, addr_b;
    input [BYTE_ENw-1   :       0]       byteena_a, byteena_b;
    input we_a, we_b, clk;
    output  [(Dw-1):0] q_a, q_b;
 
generate
/* verilator lint_off WIDTH */
if   ( BYTE_WR_EN == "NO") begin : no_byten
/* verilator lint_on WIDTH */
        dual_port_ram #(
                .Dw (Dw),
                .Aw (Aw),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
        )
        the_ram
        (
                .data_a     (data_a),
                .data_b     (data_b),
                .addr_a     (addr_a),
                .addr_b     (addr_b),
                .we_a           (we_a),
                .we_b           (we_b),
                .clk            (clk),
                .q_a            (q_a),
                .q_b            (q_b)
        );
 
end else begin : byten
 
   byte_enabled_true_dual_port_ram #(
                .BYTE_WIDTH(8),
                .ADDRESS_WIDTH(Aw),
                .BYTES(Dw/8),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
 
        )
        the_ram
        (
                .addr1          (addr_a),
                .addr2          (addr_b),
                .be1            (byteena_a),
                .be2            (byteena_b),
                .data_in1       (data_a),
                .data_in2       (data_b),
                .we1            (we_a),
                .we2            (we_b),
                .clk            (clk),
                .data_out1      (q_a),
                .data_out2      (q_b)
        );
 end
endgenerate
 
endmodule
 
 
 
 
 
 
/********************
*       generic_single_port_ram
********************/
 
 
 
module generic_single_port_ram #(
    parameter Dw=8,
    parameter Aw=6,
    parameter BYTE_WR_EN= "YES",//"YES","NO"
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
   data,
   addr,
   byteen,
   we,
   clk,
   q
 
);
/* verilator lint_off WIDTH */
        localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;
/* verilator lint_on WIDTH */
 
        input [(Dw-1):0] data;
        input [(Aw-1):0] addr;
        input [BYTE_ENw-1       :       0]       byteen;
        input we, clk;
        output  [(Dw-1):0] q;
 
generate
/* verilator lint_off WIDTH */
if   ( BYTE_WR_EN == "NO") begin : no_byten
/* verilator lint_on WIDTH */
 
        single_port_ram #(
                .Dw (Dw),
                .Aw (Aw),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
        )
        the_ram
        (
                .data     (data),
                .addr     (addr),
                .we       (we),
                .clk      (clk),
                .q        (q)
        );
 
end else begin : byten
 
        byte_enabled_single_port_ram #(
                .BYTE_WIDTH(8),
                .ADDRESS_WIDTH(Aw),
                .BYTES(Dw/8),
                .INITIAL_EN(INITIAL_EN),
                .INIT_FILE(INIT_FILE)
 
        )
        the_ram
        (
                .addr   (addr),
                .be     (byteen),
                .data_in(data),
                .we     (we),
                .clk    (clk),
                .data_out(q)
        );
end
endgenerate
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/*******************
 
    dual_port_ram
 
********************/
 
 
// Quartus II Verilog Template
// True Dual Port RAM with single clock
 
 
module dual_port_ram
#(
    parameter Dw=8,
    parameter Aw=6,
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file 
)
(
   data_a,
   data_b,
   addr_a,
   addr_b,
   we_a,
   we_b,
   clk,
   q_a,
   q_b
);
 
 
    input [(Dw-1):0] data_a, data_b;
    input [(Aw-1):0] addr_a, addr_b;
    input we_a, we_b, clk;
    output  reg [(Dw-1):0] q_a, q_b;
 
    // Declare the RAM variable
    reg [Dw-1:0] ram[2**Aw-1:0];
 
        // initial the memory if the file is defined
        generate
            /* verilator lint_off WIDTH */
                if (INITIAL_EN == "YES") begin : init
                /* verilator lint_on WIDTH */
                    initial $readmemh(INIT_FILE,ram);
                end
        endgenerate
 
 
    // Port A 
    always @ (posedge clk)
    begin
        if (we_a)
        begin
            ram[addr_a] <= data_a;
            q_a <= data_a;
        end
        else
        begin
            q_a <= ram[addr_a];
        end
    end
 
    // Port B 
    always @ (posedge clk)
    begin
        if (we_b)
        begin
            ram[addr_b] <= data_b;
            q_b <= data_b;
        end
        else
        begin
            q_b <= ram[addr_b];
        end
    end
 
 
 
endmodule
 
 
 
/****************
*simple_dual_port_ram
*
*****************/
 
 
 
// Quartus II Verilog Template
// Simple Dual Port RAM with separate read/write addresses and
// single read/write clock
 
module simple_dual_port_ram #(
        parameter Dw=8,
        parameter Aw=6,
        parameter INITIAL_EN= "NO",
        parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
        data,
        read_addr,
        write_addr,
        we,
        clk,
        q
);
 
        input   [Dw-1   :0] data;
        input   [Aw-1   :0] read_addr;
        input   [Aw-1   :0] write_addr;
        input we;
        input clk;
        output reg [Dw-1        :0] q;
 
 
        // Declare the RAM variable
        reg [Dw-1:0] ram [2**Aw-1:0];
 
        // initial the memory if the file is defined
        generate
            /* verilator lint_off WIDTH */
                if (INITIAL_EN == "YES") begin : init
                /* verilator lint_on WIDTH */
                    initial $readmemh(INIT_FILE,ram);
                end
        endgenerate
 
        always @ (posedge clk)
        begin
                // Write
                if (we)
                        ram[write_addr] <= data;
 
                // Read (if read_addr == write_addr, return OLD data).  To return
                // NEW data, use = (blocking write) rather than <= (non-blocking write)
                // in the write assignment.      NOTE: NEW data may require extra bypass
                // logic around the RAM.
                q <= ram[read_addr];
        end
 
endmodule
 
 
 
 
 
 
 
/*****************************
 
        single_port_ram
 
 
*****************************/
 
// Quartus II Verilog Template
// Single port RAM with single read/write address 
 
module single_port_ram #(
    parameter Dw=8,
    parameter Aw=6,
    parameter INITIAL_EN= "NO",
    parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format
)
(
    data,
    addr,
    we,
    clk,
    q
);
 
    input [(Dw-1):0] data;
    input [(Aw-1):0] addr;
    input we, clk;
    output [(Dw-1):0] q;
 
    // Declare the RAM variable
    reg [Dw-1:0] ram[2**Aw-1:0];
 
        // initial the memory if the file is defined
        generate
            /* verilator lint_off WIDTH */
                if (INITIAL_EN == "YES") begin : init
                /* verilator lint_on WIDTH */
                    initial $readmemh(INIT_FILE,ram);
                end
        endgenerate
 
    // Variable to hold the registered read address
    reg [Aw-1:0] addr_reg;
 
    always @ (posedge clk)
    begin
        // Write
        if (we)
            ram[addr] <= data;
            addr_reg <= addr;
    end
 
    // Continuous assignment implies read returns NEW data.
    // This is the natural behavior of the TriMatrix memory
    // blocks in Single Port mode.  
    assign q = ram[addr_reg];
 
endmodule
 
 
 
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [generic_ram.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	38	alirezamon	`/**********************************************************************`
2			`** File: generic_ram.v`
3			`**`
4			`**`
5			`** Copyright (C) 2014-2017 Alireza Monemi`
6			`**`
7			`** This file is part of ProNoC`
8			`**`
9			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
10			`** you can redistribute it and/or modify it under the terms of the GNU`
11			`** Lesser General Public License as published by the Free Software Foundation,`
12			`** either version 2 of the License, or (at your option) any later version.`
13			`**`
14			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
21			`**`
22			`**`
23			`** Description:`
24			`** Generic single dual port ram`
25			`**`
26			`**`
27			`*******************************************************************/`
28
29			`timescale 1ns / 1ps
30
31
32			`/********************`
33			`* generic_dual_port_ram`
34			`********************/`
35
36			`module generic_dual_port_ram #(`
37			`parameter Dw=8,`
38			`parameter Aw=6,`
39			`parameter BYTE_WR_EN= "YES",//"YES","NO"`
40			`parameter INITIAL_EN= "NO",`
41			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
42			`)`
43			`(`
44			`data_a,`
45			`data_b,`
46			`addr_a,`
47			`addr_b,`
48			`byteena_a,`
49			`byteena_b,`
50			`we_a,`
51			`we_b,`
52			`clk,`
53			`q_a,`
54			`q_b`
55			`);`
56
57	48	alirezamon	`/* verilator lint_off WIDTH */`
58	38	alirezamon	`localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;`
59	48	alirezamon	`/* verilator lint_on WIDTH */`
60
61	38	alirezamon	`input [(Dw-1):0] data_a, data_b;`
62			`input [(Aw-1):0] addr_a, addr_b;`
63			`input [BYTE_ENw-1 : 0] byteena_a, byteena_b;`
64			`input we_a, we_b, clk;`
65			`output [(Dw-1):0] q_a, q_b;`
66
67			`generate`
68	48	alirezamon	`/* verilator lint_off WIDTH */`
69	38	alirezamon	`if ( BYTE_WR_EN == "NO") begin : no_byten`
70	48	alirezamon	`/* verilator lint_on WIDTH */`
71	38	alirezamon	`dual_port_ram #(`
72			`.Dw (Dw),`
73			`.Aw (Aw),`
74			`.INITIAL_EN(INITIAL_EN),`
75			`.INIT_FILE(INIT_FILE)`
76			`)`
77			`the_ram`
78			`(`
79			`.data_a (data_a),`
80			`.data_b (data_b),`
81			`.addr_a (addr_a),`
82			`.addr_b (addr_b),`
83			`.we_a (we_a),`
84			`.we_b (we_b),`
85			`.clk (clk),`
86			`.q_a (q_a),`
87			`.q_b (q_b)`
88			`);`
89
90			`end else begin : byten`
91
92			`byte_enabled_true_dual_port_ram #(`
93			`.BYTE_WIDTH(8),`
94			`.ADDRESS_WIDTH(Aw),`
95			`.BYTES(Dw/8),`
96			`.INITIAL_EN(INITIAL_EN),`
97			`.INIT_FILE(INIT_FILE)`
98
99			`)`
100			`the_ram`
101			`(`
102			`.addr1 (addr_a),`
103			`.addr2 (addr_b),`
104			`.be1 (byteena_a),`
105			`.be2 (byteena_b),`
106			`.data_in1 (data_a),`
107			`.data_in2 (data_b),`
108			`.we1 (we_a),`
109			`.we2 (we_b),`
110			`.clk (clk),`
111			`.data_out1 (q_a),`
112			`.data_out2 (q_b)`
113			`);`
114			`end`
115			`endgenerate`
116
117			`endmodule`
118
119
120
121
122
123
124			`/********************`
125			`* generic_single_port_ram`
126			`********************/`
127
128
129
130			`module generic_single_port_ram #(`
131			`parameter Dw=8,`
132			`parameter Aw=6,`
133			`parameter BYTE_WR_EN= "YES",//"YES","NO"`
134			`parameter INITIAL_EN= "NO",`
135			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
136			`)`
137			`(`
138			`data,`
139			`addr,`
140			`byteen,`
141			`we,`
142			`clk,`
143			`q`
144
145			`);`
146	48	alirezamon	`/* verilator lint_off WIDTH */`
147	38	alirezamon	`localparam BYTE_ENw= ( BYTE_WR_EN == "YES")? Dw/8 : 1;`
148	48	alirezamon	`/* verilator lint_on WIDTH */`
149
150	38	alirezamon	`input [(Dw-1):0] data;`
151			`input [(Aw-1):0] addr;`
152			`input [BYTE_ENw-1 : 0] byteen;`
153			`input we, clk;`
154			`output [(Dw-1):0] q;`
155
156			`generate`
157	48	alirezamon	`/* verilator lint_off WIDTH */`
158	38	alirezamon	`if ( BYTE_WR_EN == "NO") begin : no_byten`
159	48	alirezamon	`/* verilator lint_on WIDTH */`
160	38	alirezamon
161			`single_port_ram #(`
162			`.Dw (Dw),`
163			`.Aw (Aw),`
164			`.INITIAL_EN(INITIAL_EN),`
165			`.INIT_FILE(INIT_FILE)`
166			`)`
167			`the_ram`
168			`(`
169			`.data (data),`
170			`.addr (addr),`
171			`.we (we),`
172			`.clk (clk),`
173			`.q (q)`
174			`);`
175
176			`end else begin : byten`
177
178			`byte_enabled_single_port_ram #(`
179			`.BYTE_WIDTH(8),`
180			`.ADDRESS_WIDTH(Aw),`
181			`.BYTES(Dw/8),`
182			`.INITIAL_EN(INITIAL_EN),`
183			`.INIT_FILE(INIT_FILE)`
184
185			`)`
186			`the_ram`
187			`(`
188			`.addr (addr),`
189			`.be (byteen),`
190			`.data_in(data),`
191			`.we (we),`
192			`.clk (clk),`
193			`.data_out(q)`
194			`);`
195			`end`
196			`endgenerate`
197
198			`endmodule`
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216			`/*******************`
217
218			`dual_port_ram`
219
220			`********************/`
221
222
223			`// Quartus II Verilog Template`
224			`// True Dual Port RAM with single clock`
225
226
227			`module dual_port_ram`
228			`#(`
229			`parameter Dw=8,`
230			`parameter Aw=6,`
231			`parameter INITIAL_EN= "NO",`
232			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file`
233			`)`
234			`(`
235			`data_a,`
236			`data_b,`
237			`addr_a,`
238			`addr_b,`
239			`we_a,`
240			`we_b,`
241			`clk,`
242			`q_a,`
243			`q_b`
244			`);`
245
246
247			`input [(Dw-1):0] data_a, data_b;`
248			`input [(Aw-1):0] addr_a, addr_b;`
249			`input we_a, we_b, clk;`
250			`output reg [(Dw-1):0] q_a, q_b;`
251
252			`// Declare the RAM variable`
253			`reg [Dw-1:0] ram[2**Aw-1:0];`
254
255			`// initial the memory if the file is defined`
256			`generate`
257	48	alirezamon	`/* verilator lint_off WIDTH */`
258	38	alirezamon	`if (INITIAL_EN == "YES") begin : init`
259	48	alirezamon	`/* verilator lint_on WIDTH */`
260	38	alirezamon	`initial $readmemh(INIT_FILE,ram);`
261			`end`
262			`endgenerate`
263
264
265			`// Port A`
266			`always @ (posedge clk)`
267			`begin`
268			`if (we_a)`
269			`begin`
270			`ram[addr_a] <= data_a;`
271			`q_a <= data_a;`
272			`end`
273			`else`
274			`begin`
275			`q_a <= ram[addr_a];`
276			`end`
277			`end`
278
279			`// Port B`
280			`always @ (posedge clk)`
281			`begin`
282			`if (we_b)`
283			`begin`
284			`ram[addr_b] <= data_b;`
285			`q_b <= data_b;`
286			`end`
287			`else`
288			`begin`
289			`q_b <= ram[addr_b];`
290			`end`
291			`end`
292
293
294
295			`endmodule`
296
297
298
299			`/****************`
300			`*simple_dual_port_ram`
301			`*`
302			`*****************/`
303
304
305
306			`// Quartus II Verilog Template`
307			`// Simple Dual Port RAM with separate read/write addresses and`
308			`// single read/write clock`
309
310			`module simple_dual_port_ram #(`
311			`parameter Dw=8,`
312			`parameter Aw=6,`
313			`parameter INITIAL_EN= "NO",`
314			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
315			`)`
316			`(`
317			`data,`
318			`read_addr,`
319			`write_addr,`
320			`we,`
321			`clk,`
322			`q`
323			`);`
324
325			`input [Dw-1 :0] data;`
326			`input [Aw-1 :0] read_addr;`
327			`input [Aw-1 :0] write_addr;`
328			`input we;`
329			`input clk;`
330			`output reg [Dw-1 :0] q;`
331
332
333			`// Declare the RAM variable`
334			`reg [Dw-1:0] ram [2**Aw-1:0];`
335
336			`// initial the memory if the file is defined`
337			`generate`
338	48	alirezamon	`/* verilator lint_off WIDTH */`
339	38	alirezamon	`if (INITIAL_EN == "YES") begin : init`
340	48	alirezamon	`/* verilator lint_on WIDTH */`
341	38	alirezamon	`initial $readmemh(INIT_FILE,ram);`
342			`end`
343			`endgenerate`
344
345			`always @ (posedge clk)`
346			`begin`
347			`// Write`
348			`if (we)`
349			`ram[write_addr] <= data;`
350
351			`// Read (if read_addr == write_addr, return OLD data). To return`
352			`// NEW data, use = (blocking write) rather than <= (non-blocking write)`
353			`// in the write assignment. NOTE: NEW data may require extra bypass`
354			`// logic around the RAM.`
355			`q <= ram[read_addr];`
356			`end`
357
358			`endmodule`
359
360
361
362
363
364
365
366			`/*****************************`
367
368			`single_port_ram`
369
370
371			`*****************************/`
372
373			`// Quartus II Verilog Template`
374			`// Single port RAM with single read/write address`
375
376			`module single_port_ram #(`
377			`parameter Dw=8,`
378			`parameter Aw=6,`
379			`parameter INITIAL_EN= "NO",`
380			`parameter INIT_FILE= "sw/ram/ram0.txt"// ram initial file in hex ascii format`
381			`)`
382			`(`
383			`data,`
384			`addr,`
385			`we,`
386			`clk,`
387			`q`
388			`);`
389
390			`input [(Dw-1):0] data;`
391			`input [(Aw-1):0] addr;`
392			`input we, clk;`
393			`output [(Dw-1):0] q;`
394
395			`// Declare the RAM variable`
396			`reg [Dw-1:0] ram[2**Aw-1:0];`
397
398			`// initial the memory if the file is defined`
399			`generate`
400	48	alirezamon	`/* verilator lint_off WIDTH */`
401	38	alirezamon	`if (INITIAL_EN == "YES") begin : init`
402	48	alirezamon	`/* verilator lint_on WIDTH */`
403	38	alirezamon	`initial $readmemh(INIT_FILE,ram);`
404			`end`
405			`endgenerate`
406
407			`// Variable to hold the registered read address`
408			`reg [Aw-1:0] addr_reg;`
409
410			`always @ (posedge clk)`
411			`begin`
412			`// Write`
413			`if (we)`
414			`ram[addr] <= data;`
415			`addr_reg <= addr;`
416			`end`
417
418			`// Continuous assignment implies read returns NEW data.`
419			`// This is the natural behavior of the TriMatrix memory`
420			`// blocks in Single Port mode.`
421			`assign q = ram[addr_reg];`
422
423			`endmodule`
424
425
426
427