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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [jtag_wb/] [vjtag_wb.v] - Blame information for rev 38

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1 38 alirezamon 
module vjtag_wb #(
2 
        parameter VJTAG_INDEX=126,
3 
        parameter DW=32,
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        parameter AW=32,
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        parameter SW=32,
6 
 
7 
        //wishbone port parameters
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    parameter S_Aw          =   7,
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    parameter M_Aw          =   32,
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    parameter TAGw          =   3,
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    parameter SELw          =   4
12 
 
13 
 
14 
)(
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        clk,
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        reset,
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        status_i,
18 
 
19 
         //wishbone master interface signals
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        m_sel_o,
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        m_dat_o,
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        m_addr_o,
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        m_cti_o,
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        m_stb_o,
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        m_cyc_o,
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        m_we_o,
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        m_dat_i,
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        m_ack_i
29 
 
30 
);
31 
 
32 
        //IO declaration
33 
        input reset,clk;
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        input [SW-1     :       0]       status_i;
35 
 
36 
        //wishbone master interface signals
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        output  [SELw-1          :   0] m_sel_o;
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        output  [DW-1            :   0] m_dat_o;
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        output  [M_Aw-1          :   0] m_addr_o;
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        output  [TAGw-1          :   0] m_cti_o;
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        output                          m_stb_o;
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        output                          m_cyc_o;
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        output                          m_we_o;
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        input   [DW-1           :  0]   m_dat_i;
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        input                           m_ack_i;
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47 
 
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        localparam STATE_NUM=3,
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                                  IDEAL =1,
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                                  WB_WR_DATA=2,
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                                  WB_RD_DATA=4;
52 
 
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        reg [STATE_NUM-1        :       0] ps,ns;
54 
 
55 
        wire [DW-1      :0] data_out,  data_in;
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        wire  wb_wr_addr_en,  wb_wr_data_en,    wb_rd_data_en;
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        reg wr_mem_en,  rd_mem_en,  wb_cap_rd;
58 
 
59 
        reg [AW-1       :       0]       wb_addr,wb_addr_next;
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        reg [DW-1       :       0]       wb_wr_data,wb_rd_data;
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        reg wb_addr_inc;
62 
 
63 
 
64 
        assign  m_cti_o         =    3'b000;
65 
        assign  m_sel_o         =   4'b1111;
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        assign  m_cyc_o                         =       m_stb_o;
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        assign  m_stb_o                 = wr_mem_en |  rd_mem_en;
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        assign  m_we_o                          = wr_mem_en;
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        assign  m_dat_o                 = wb_wr_data;
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        assign  m_addr_o                        = wb_addr;
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        assign  data_in                         = wb_rd_data;
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//vjtag vjtag signals declaration
73 
 
74 
 
75 
localparam VJ_DW= (DW > AW)? DW : AW;
76 
 
77 
 
78 
        vjtag_ctrl #(
79 
                .DW(VJ_DW),
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                .VJTAG_INDEX(VJTAG_INDEX),
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                .STW(SW)
82 
        )
83 
        vjtag_ctrl_inst
84 
        (
85 
                .clk(clk),
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                .reset(reset),
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                .data_out(data_out),
88 
                .data_in(data_in),
89 
                .wb_wr_addr_en(wb_wr_addr_en),
90 
                .wb_wr_data_en(wb_wr_data_en),
91 
                .wb_rd_data_en(wb_rd_data_en),
92 
                .status_i(status_i)
93 
        );
94 
 
95 
 
96 
 
97 
        always @(posedge clk or posedge reset) begin
98 
                if(reset) begin
99 
                        wb_addr <= {AW{1'b0}};
100 
                        wb_wr_data  <= {DW{1'b0}};
101 
                        ps <= IDEAL;
102 
                end else begin
103 
                        wb_addr <= wb_addr_next;
104 
                        ps <= ns;
105 
                        if(wb_wr_data_en) wb_wr_data  <= data_out;
106 
                        if(wb_cap_rd) wb_rd_data <= m_dat_i;
107 
                end
108 
        end
109 
 
110 
 
111 
        always @(*)begin
112 
                wb_addr_next= wb_addr;
113 
                if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 :       0];
114 
                else if (wb_addr_inc)  wb_addr_next = wb_addr +1'b1;
115 
        end
116 
 
117 
 
118 
 
119 
        always @(*)begin
120 
                ns=ps;
121 
                wr_mem_en =1'b0;
122 
                rd_mem_en =1'b0;
123 
                wb_addr_inc=1'b0;
124 
                wb_cap_rd=1'b0;
125 
                case(ps)
126 
                IDEAL : begin
127 
                        if(wb_wr_data_en) ns= WB_WR_DATA;
128 
                        if(wb_rd_data_en) ns= WB_RD_DATA;
129 
                end
130 
                WB_WR_DATA: begin
131 
                        wr_mem_en =1'b1;
132 
                        if(m_ack_i) begin
133 
                                ns=IDEAL;
134 
                                wb_addr_inc=1'b1;
135 
                        end
136 
                end
137 
                WB_RD_DATA: begin
138 
                        rd_mem_en =1'b1;
139 
                        if(m_ack_i) begin
140 
                                wb_cap_rd=1'b1;
141 
                                ns=IDEAL;
142 
                                //wb_addr_inc=1'b1;
143 
                        end
144 
                end
145 
                endcase
146 
        end
147 
 
148 
        //assign led={wb_addr[7:0], wb_wr_data[7:0]};
149 
 
150 
endmodule
151 
 
152 
 
153 
 
154 
 
155 
module vjtag_ctrl #(
156 
        parameter DW=32,
157 
        parameter STW=2, // status width <= DW
158 
        parameter VJTAG_INDEX=126
159 
 
160 
)(
161 
        clk,
162 
        reset,
163 
        data_out,
164 
        data_in,
165 
        status_i,
166 
        wb_wr_addr_en,
167 
        wb_wr_data_en,
168 
        wb_rd_data_en
169 
);
170 
 
171 
//IO declaration
172 
        input reset,clk;
173 
        output [DW-1    :0] data_out;
174 
        input [DW-1     :0] data_in;
175 
        input [STW-1    :0] status_i;
176 
        output wb_wr_addr_en, wb_wr_data_en,    wb_rd_data_en;
177 
 
178 
 
179 
//vjtag vjtag signals declaration
180 
        wire    [2:0]  ir_out ,  ir_in;
181 
        wire      tdo, tck,       tdi;
182 
        wire      cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
183 
 
184 
 
185 
        vjtag   #(
186 
         .VJTAG_INDEX(VJTAG_INDEX)
187 
        )
188 
        vjtag_inst (
189 
        .ir_out ( ir_out ),
190 
        .tdo ( tdo ),
191 
        .ir_in ( ir_in ),
192 
        .tck ( tck ),
193 
        .tdi ( tdi ),
194 
        .virtual_state_cdr      ( cdr ),
195 
        .virtual_state_cir      ( cir ),
196 
        .virtual_state_e1dr     ( e1dr ),
197 
        .virtual_state_e2dr     ( e2dr ),
198 
        .virtual_state_pdr      ( pdr ),
199 
        .virtual_state_sdr      ( sdr ),
200 
        .virtual_state_udr      ( udr ),
201 
        .virtual_state_uir      ( uir )
202 
        );
203 
 
204 
 
205 
        // IR states
206 
        localparam [2:0]                           UPDATE_WB_ADDR  = 3'b111,
207 
                                                  UPDATE_WB_WR_DATA  = 3'b110,
208 
                                                  UPDATE_WB_RD_DATA  = 3'b101,
209 
                                                  RD_STATUS          =3'b100,
210 
                                                  BYPASS = 3'b000;
211 
 
212 
 
213 
        // internal registers
214 
        reg [2:0] ir;
215 
        reg bypass_reg;
216 
        reg [DW-1       :       0] shift_buffer,shift_buffer_next;
217 
        reg cdr_delayed,sdr_delayed;
218 
 
219 
 
220 
 
221 
        /*
222 
        always @(negedge tck)
223 
        begin
224 
                //  Delay the CDR signal by one half clock cycle
225 
                cdr_delayed = cdr;
226 
                sdr_delayed = sdr;
227 
        end
228 
        */
229 
 
230 
        assign ir_out = ir_in;  // Just pass the IR out
231 
        assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];
232 
        assign data_out = shift_buffer;
233 
 
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236 
 
237 
        always @(posedge tck or posedge reset)
238 
        begin
239 
                if (reset)begin
240 
                        ir <= 3'b000;
241 
                        bypass_reg<=1'b0;
242 
                        shift_buffer<={DW{1'b0}};
243 
 
244 
                end else begin
245 
                        if( uir ) ir <= ir_in; // Capture the instruction provided
246 
                        bypass_reg <= tdi;
247 
                        shift_buffer<=shift_buffer_next;
248 
 
249 
                end
250 
        end
251 
 
252 
 
253 
 
254 
        always @ (*)begin
255 
                shift_buffer_next=shift_buffer;
256 
 
257 
                if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer
258 
                case(ir)
259 
                        RD_STATUS:begin
260 
                                if( cdr ) shift_buffer_next[STW-1       :       0] = status_i;
261 
                        end
262 
                        default: begin
263 
                                if( cdr ) shift_buffer_next = data_in;
264 
                        end
265 
                endcase
266 
        end
267 
 
268 
 
269 
 
270 
        reg wb_wr_addr1,        wb_wr_data1,    wb_rd_data1;
271 
        //always @(posedge tck or posedge reset)
272 
        always @(*)
273 
        begin
274 
                //if( reset )   begin
275 
                //      wb_wr_addr1<=1'b0;
276 
                //      wb_wr_data1<=1'b0;
277 
                //end else begin
278 
                        wb_wr_addr1=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) &  udr;
279 
                        wb_wr_data1=(ir== UPDATE_WB_WR_DATA &&  udr );
280 
                        wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr);
281 
                //end
282 
        end
283 
 
284 
        reg wb_wr_addr2,        wb_wr_data2,    wb_rd_data2;
285 
        reg wb_wr_addr3,        wb_wr_data3,    wb_rd_data3;
286 
 
287 
        always @(posedge clk or posedge reset)
288 
        begin
289 
                if( reset )     begin
290 
                        wb_wr_addr2<=1'b0;
291 
                        wb_wr_data2<=1'b0;
292 
                        wb_wr_addr3<=1'b0;
293 
                        wb_wr_data3<=1'b0;
294 
                        wb_rd_data2<=1'b0;
295 
                        wb_rd_data3<=1'b0;
296 
                end else begin
297 
                        wb_wr_addr2<=wb_wr_addr1;
298 
                        wb_wr_data2<=wb_wr_data1;
299 
                        wb_wr_addr3<=wb_wr_addr2;
300 
                        wb_wr_data3<=wb_wr_data2;
301 
                        wb_rd_data2<=wb_rd_data1;
302 
                        wb_rd_data3<=wb_rd_data2;
303 
                end
304 
        end
305 
 
306 
        assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3);
307 
        assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3);
308 
        assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3);
309 
endmodule
310 
 
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