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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [jtag_wb/] [vjtag_wb.v] - Blame information for rev 48

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module vjtag_wb #(
        parameter VJTAG_INDEX=126,
        parameter DW=32,
        parameter AW=32,
        parameter SW=32,
 
        //wishbone port parameters
    parameter S_Aw          =   7,
    parameter M_Aw          =   32,
    parameter TAGw          =   3,
    parameter SELw          =   4
 
 
)(
        clk,
        reset,
        status_i,
 
         //wishbone master interface signals
        m_sel_o,
        m_dat_o,
        m_addr_o,
        m_cti_o,
        m_stb_o,
        m_cyc_o,
        m_we_o,
        m_dat_i,
        m_ack_i
 
);
 
        //IO declaration
        input reset,clk;
        input [SW-1     :       0]       status_i;
 
        //wishbone master interface signals
        output  [SELw-1          :   0] m_sel_o;
        output  [DW-1            :   0] m_dat_o;
        output  [M_Aw-1          :   0] m_addr_o;
        output  [TAGw-1          :   0] m_cti_o;
        output                          m_stb_o;
        output                          m_cyc_o;
        output                          m_we_o;
        input   [DW-1           :  0]   m_dat_i;
        input                           m_ack_i;
 
 
        localparam STATE_NUM=3,
                                  IDEAL =1,
                                  WB_WR_DATA=2,
                                  WB_RD_DATA=4;
 
        reg [STATE_NUM-1        :       0] ps,ns;
 
        wire [DW-1      :0] data_out,  data_in;
        wire  wb_wr_addr_en,  wb_wr_data_en,    wb_rd_data_en;
        reg wr_mem_en,  rd_mem_en,  wb_cap_rd;
 
        reg [AW-1       :       0]       wb_addr,wb_addr_next;
        reg [DW-1       :       0]       wb_wr_data,wb_rd_data;
        reg wb_addr_inc;
 
 
        assign  m_cti_o         =    3'b000;
        assign  m_sel_o         =   4'b1111;
        assign  m_cyc_o                         =       m_stb_o;
        assign  m_stb_o                 = wr_mem_en |  rd_mem_en;
        assign  m_we_o                          = wr_mem_en;
        assign  m_dat_o                 = wb_wr_data;
        assign  m_addr_o                        = wb_addr;
        assign  data_in                         = wb_rd_data;
//vjtag vjtag signals declaration
 
 
localparam VJ_DW= (DW > AW)? DW : AW;
 
 
        vjtag_ctrl #(
                .DW(VJ_DW),
                .VJTAG_INDEX(VJTAG_INDEX),
                .STW(SW)
        )
        vjtag_ctrl_inst
        (
                .clk(clk),
                .reset(reset),
                .data_out(data_out),
                .data_in(data_in),
                .wb_wr_addr_en(wb_wr_addr_en),
                .wb_wr_data_en(wb_wr_data_en),
                .wb_rd_data_en(wb_rd_data_en),
                .status_i(status_i)
        );
 
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
 
                if(reset) begin
                        wb_addr <= {AW{1'b0}};
                        wb_wr_data  <= {DW{1'b0}};
                        ps <= IDEAL;
                end else begin
                        wb_addr <= wb_addr_next;
                        ps <= ns;
                        if(wb_wr_data_en) wb_wr_data  <= data_out;
                        if(wb_cap_rd) wb_rd_data <= m_dat_i;
                end
        end
 
 
        always @(*)begin
                wb_addr_next= wb_addr;
                if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 :       0];
                else if (wb_addr_inc)  wb_addr_next = wb_addr +1'b1;
        end
 
 
 
        always @(*)begin
                ns=ps;
                wr_mem_en =1'b0;
                rd_mem_en =1'b0;
                wb_addr_inc=1'b0;
                wb_cap_rd=1'b0;
                case(ps)
                IDEAL : begin
                        if(wb_wr_data_en) ns= WB_WR_DATA;
                        if(wb_rd_data_en) ns= WB_RD_DATA;
                end
                WB_WR_DATA: begin
                        wr_mem_en =1'b1;
                        if(m_ack_i) begin
                                ns=IDEAL;
                                wb_addr_inc=1'b1;
                        end
                end
                WB_RD_DATA: begin
                        rd_mem_en =1'b1;
                        if(m_ack_i) begin
                                wb_cap_rd=1'b1;
                                ns=IDEAL;
                                //wb_addr_inc=1'b1;                     
                        end
                end
                endcase
        end
 
        //assign led={wb_addr[7:0], wb_wr_data[7:0]};
 
endmodule
 
 
 
 
module vjtag_ctrl #(
        parameter DW=32,
        parameter STW=2, // status width <= DW
        parameter VJTAG_INDEX=126
 
)(
        clk,
        reset,
        data_out,
        data_in,
        status_i,
        wb_wr_addr_en,
        wb_wr_data_en,
        wb_rd_data_en
);
 
//IO declaration
        input reset,clk;
        output [DW-1    :0] data_out;
        input [DW-1     :0] data_in;
        input [STW-1    :0] status_i;
        output wb_wr_addr_en, wb_wr_data_en,    wb_rd_data_en;
 
 
//vjtag vjtag signals declaration
        wire    [2:0]  ir_out ,  ir_in;
        wire      tdo, tck,       tdi;
        wire      cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;
 
 
        vjtag   #(
         .VJTAG_INDEX(VJTAG_INDEX)
        )
        vjtag_inst (
        .ir_out ( ir_out ),
        .tdo ( tdo ),
        .ir_in ( ir_in ),
        .tck ( tck ),
        .tdi ( tdi ),
        .virtual_state_cdr      ( cdr ),
        .virtual_state_cir      ( cir ),
        .virtual_state_e1dr     ( e1dr ),
        .virtual_state_e2dr     ( e2dr ),
        .virtual_state_pdr      ( pdr ),
        .virtual_state_sdr      ( sdr ),
        .virtual_state_udr      ( udr ),
        .virtual_state_uir      ( uir )
        );
 
 
        // IR states
        localparam [2:0]                           UPDATE_WB_ADDR  = 3'b111,
                                                  UPDATE_WB_WR_DATA  = 3'b110,
                                                  UPDATE_WB_RD_DATA  = 3'b101,
                                                  RD_STATUS          =3'b100,
                                                  BYPASS = 3'b000;
 
 
        // internal registers 
        reg [2:0] ir;
        reg bypass_reg;
        reg [DW-1       :       0] shift_buffer,shift_buffer_next;
        reg cdr_delayed,sdr_delayed;
 
 
 
        /*
        always @(negedge tck)
        begin
                //  Delay the CDR signal by one half clock cycle
                cdr_delayed = cdr;
                sdr_delayed = sdr;
        end
        */
 
        assign ir_out = ir_in;  // Just pass the IR out
        assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];
        assign data_out = shift_buffer;
 
 
`ifdef SYNC_RESET_MODE
    always @ (posedge tck )begin
`else
    always @ (posedge tck or posedge reset)begin
`endif
 
                if (reset)begin
                        ir <= 3'b000;
                        bypass_reg<=1'b0;
                        shift_buffer<={DW{1'b0}};
 
                end else begin
                        if( uir ) ir <= ir_in; // Capture the instruction provided
                        bypass_reg <= tdi;
                        shift_buffer<=shift_buffer_next;
 
                end
        end
 
 
 
        always @ (*)begin
                shift_buffer_next=shift_buffer;
 
                if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer
                case(ir)
                        RD_STATUS:begin
                                if( cdr ) shift_buffer_next[STW-1       :       0] = status_i;
                        end
                        default: begin
                                if( cdr ) shift_buffer_next = data_in;
                        end
                endcase
        end
 
 
 
        reg wb_wr_addr1,        wb_wr_data1,    wb_rd_data1;
        //always @(posedge tck or posedge reset)
        always @(*)
        begin
                //if( reset )   begin
                //      wb_wr_addr1<=1'b0;
                //      wb_wr_data1<=1'b0;
                //end else begin
                        wb_wr_addr1=(ir== UPDATE_WB_ADDR || ir== UPDATE_WB_RD_DATA) &  udr;
                        wb_wr_data1=(ir== UPDATE_WB_WR_DATA &&  udr );
                        wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr);
                //end   
        end
 
        reg wb_wr_addr2,        wb_wr_data2,    wb_rd_data2;
        reg wb_wr_addr3,        wb_wr_data3,    wb_rd_data3;
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
 
                if( reset )     begin
                        wb_wr_addr2<=1'b0;
                        wb_wr_data2<=1'b0;
                        wb_wr_addr3<=1'b0;
                        wb_wr_data3<=1'b0;
                        wb_rd_data2<=1'b0;
                        wb_rd_data3<=1'b0;
                end else begin
                        wb_wr_addr2<=wb_wr_addr1;
                        wb_wr_data2<=wb_wr_data1;
                        wb_wr_addr3<=wb_wr_addr2;
                        wb_wr_data3<=wb_wr_data2;
                        wb_rd_data2<=wb_rd_data1;
                        wb_rd_data3<=wb_rd_data2;
                end
        end
 
        assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3);
        assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3);
        assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3);
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [jtag_wb/] [vjtag_wb.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	38	alirezamon	`module vjtag_wb #(`
2			`parameter VJTAG_INDEX=126,`
3			`parameter DW=32,`
4			`parameter AW=32,`
5			`parameter SW=32,`
6
7			`//wishbone port parameters`
8			`parameter S_Aw = 7,`
9			`parameter M_Aw = 32,`
10			`parameter TAGw = 3,`
11			`parameter SELw = 4`
12
13
14			`)(`
15			`clk,`
16			`reset,`
17			`status_i,`
18
19			`//wishbone master interface signals`
20			`m_sel_o,`
21			`m_dat_o,`
22			`m_addr_o,`
23			`m_cti_o,`
24			`m_stb_o,`
25			`m_cyc_o,`
26			`m_we_o,`
27			`m_dat_i,`
28			`m_ack_i`
29
30			`);`
31
32			`//IO declaration`
33			`input reset,clk;`
34			`input [SW-1 : 0] status_i;`
35
36			`//wishbone master interface signals`
37			`output [SELw-1 : 0] m_sel_o;`
38			`output [DW-1 : 0] m_dat_o;`
39			`output [M_Aw-1 : 0] m_addr_o;`
40			`output [TAGw-1 : 0] m_cti_o;`
41			`output m_stb_o;`
42			`output m_cyc_o;`
43			`output m_we_o;`
44			`input [DW-1 : 0] m_dat_i;`
45			`input m_ack_i;`
46
47
48			`localparam STATE_NUM=3,`
49			`IDEAL =1,`
50			`WB_WR_DATA=2,`
51			`WB_RD_DATA=4;`
52
53			`reg [STATE_NUM-1 : 0] ps,ns;`
54
55			`wire [DW-1 :0] data_out, data_in;`
56			`wire wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;`
57			`reg wr_mem_en, rd_mem_en, wb_cap_rd;`
58
59			`reg [AW-1 : 0] wb_addr,wb_addr_next;`
60			`reg [DW-1 : 0] wb_wr_data,wb_rd_data;`
61			`reg wb_addr_inc;`
62
63
64			`assign m_cti_o = 3'b000;`
65			`assign m_sel_o = 4'b1111;`
66			`assign m_cyc_o = m_stb_o;`
67			`assign m_stb_o = wr_mem_en \| rd_mem_en;`
68			`assign m_we_o = wr_mem_en;`
69			`assign m_dat_o = wb_wr_data;`
70			`assign m_addr_o = wb_addr;`
71			`assign data_in = wb_rd_data;`
72			`//vjtag vjtag signals declaration`
73
74
75			`localparam VJ_DW= (DW > AW)? DW : AW;`
76
77
78			`vjtag_ctrl #(`
79			`.DW(VJ_DW),`
80			`.VJTAG_INDEX(VJTAG_INDEX),`
81			`.STW(SW)`
82			`)`
83			`vjtag_ctrl_inst`
84			`(`
85			`.clk(clk),`
86			`.reset(reset),`
87			`.data_out(data_out),`
88			`.data_in(data_in),`
89			`.wb_wr_addr_en(wb_wr_addr_en),`
90			`.wb_wr_data_en(wb_wr_data_en),`
91			`.wb_rd_data_en(wb_rd_data_en),`
92			`.status_i(status_i)`
93			`);`
94
95
96	48	alirezamon	`ifdef SYNC_RESET_MODE
97			`always @ (posedge clk )begin`
98			`else
99			`always @ (posedge clk or posedge reset)begin`
100			`endif
101	38	alirezamon
102			`if(reset) begin`
103			`wb_addr <= {AW{1'b0}};`
104			`wb_wr_data <= {DW{1'b0}};`
105			`ps <= IDEAL;`
106			`end else begin`
107			`wb_addr <= wb_addr_next;`
108			`ps <= ns;`
109			`if(wb_wr_data_en) wb_wr_data <= data_out;`
110			`if(wb_cap_rd) wb_rd_data <= m_dat_i;`
111			`end`
112			`end`
113
114
115			`always @(*)begin`
116			`wb_addr_next= wb_addr;`
117			`if(wb_wr_addr_en) wb_addr_next = data_out [AW-1 : 0];`
118			`else if (wb_addr_inc) wb_addr_next = wb_addr +1'b1;`
119			`end`
120
121
122
123			`always @(*)begin`
124			`ns=ps;`
125			`wr_mem_en =1'b0;`
126			`rd_mem_en =1'b0;`
127			`wb_addr_inc=1'b0;`
128			`wb_cap_rd=1'b0;`
129			`case(ps)`
130			`IDEAL : begin`
131			`if(wb_wr_data_en) ns= WB_WR_DATA;`
132			`if(wb_rd_data_en) ns= WB_RD_DATA;`
133			`end`
134			`WB_WR_DATA: begin`
135			`wr_mem_en =1'b1;`
136			`if(m_ack_i) begin`
137			`ns=IDEAL;`
138			`wb_addr_inc=1'b1;`
139			`end`
140			`end`
141			`WB_RD_DATA: begin`
142			`rd_mem_en =1'b1;`
143			`if(m_ack_i) begin`
144			`wb_cap_rd=1'b1;`
145			`ns=IDEAL;`
146			`//wb_addr_inc=1'b1;`
147			`end`
148			`end`
149			`endcase`
150			`end`
151
152			`//assign led={wb_addr[7:0], wb_wr_data[7:0]};`
153
154			`endmodule`
155
156
157
158
159			`module vjtag_ctrl #(`
160			`parameter DW=32,`
161			`parameter STW=2, // status width <= DW`
162			`parameter VJTAG_INDEX=126`
163
164			`)(`
165			`clk,`
166			`reset,`
167			`data_out,`
168			`data_in,`
169			`status_i,`
170			`wb_wr_addr_en,`
171			`wb_wr_data_en,`
172			`wb_rd_data_en`
173			`);`
174
175			`//IO declaration`
176			`input reset,clk;`
177			`output [DW-1 :0] data_out;`
178			`input [DW-1 :0] data_in;`
179			`input [STW-1 :0] status_i;`
180			`output wb_wr_addr_en, wb_wr_data_en, wb_rd_data_en;`
181
182
183			`//vjtag vjtag signals declaration`
184			`wire [2:0] ir_out , ir_in;`
185			`wire tdo, tck, tdi;`
186			`wire cdr ,cir,e1dr,e2dr,pdr,sdr,udr,uir;`
187
188
189			`vjtag #(`
190			`.VJTAG_INDEX(VJTAG_INDEX)`
191			`)`
192			`vjtag_inst (`
193			`.ir_out ( ir_out ),`
194			`.tdo ( tdo ),`
195			`.ir_in ( ir_in ),`
196			`.tck ( tck ),`
197			`.tdi ( tdi ),`
198			`.virtual_state_cdr ( cdr ),`
199			`.virtual_state_cir ( cir ),`
200			`.virtual_state_e1dr ( e1dr ),`
201			`.virtual_state_e2dr ( e2dr ),`
202			`.virtual_state_pdr ( pdr ),`
203			`.virtual_state_sdr ( sdr ),`
204			`.virtual_state_udr ( udr ),`
205			`.virtual_state_uir ( uir )`
206			`);`
207
208
209			`// IR states`
210			`localparam [2:0] UPDATE_WB_ADDR = 3'b111,`
211			`UPDATE_WB_WR_DATA = 3'b110,`
212			`UPDATE_WB_RD_DATA = 3'b101,`
213			`RD_STATUS =3'b100,`
214			`BYPASS = 3'b000;`
215
216
217			`// internal registers`
218			`reg [2:0] ir;`
219			`reg bypass_reg;`
220			`reg [DW-1 : 0] shift_buffer,shift_buffer_next;`
221			`reg cdr_delayed,sdr_delayed;`
222
223
224
225			`/*`
226			`always @(negedge tck)`
227			`begin`
228			`// Delay the CDR signal by one half clock cycle`
229			`cdr_delayed = cdr;`
230			`sdr_delayed = sdr;`
231			`end`
232			`*/`
233
234			`assign ir_out = ir_in; // Just pass the IR out`
235			`assign tdo = (ir == BYPASS) ? bypass_reg : shift_buffer[0];`
236			`assign data_out = shift_buffer;`
237
238
239	48	alirezamon	`ifdef SYNC_RESET_MODE
240			`always @ (posedge tck )begin`
241			`else
242			`always @ (posedge tck or posedge reset)begin`
243			`endif
244
245	38	alirezamon	`if (reset)begin`
246			`ir <= 3'b000;`
247			`bypass_reg<=1'b0;`
248			`shift_buffer<={DW{1'b0}};`
249
250			`end else begin`
251			`if( uir ) ir <= ir_in; // Capture the instruction provided`
252			`bypass_reg <= tdi;`
253			`shift_buffer<=shift_buffer_next;`
254
255			`end`
256			`end`
257
258
259
260			`always @ (*)begin`
261			`shift_buffer_next=shift_buffer;`
262
263			`if( sdr ) shift_buffer_next={tdi,shift_buffer[DW-1:1]};// shift buffer`
264			`case(ir)`
265			`RD_STATUS:begin`
266			`if( cdr ) shift_buffer_next[STW-1 : 0] = status_i;`
267			`end`
268			`default: begin`
269			`if( cdr ) shift_buffer_next = data_in;`
270			`end`
271			`endcase`
272			`end`
273
274
275
276			`reg wb_wr_addr1, wb_wr_data1, wb_rd_data1;`
277			`//always @(posedge tck or posedge reset)`
278			`always @(*)`
279			`begin`
280			`//if( reset ) begin`
281			`// wb_wr_addr1<=1'b0;`
282			`// wb_wr_data1<=1'b0;`
283			`//end else begin`
284			`wb_wr_addr1=(ir== UPDATE_WB_ADDR \|\| ir== UPDATE_WB_RD_DATA) & udr;`
285			`wb_wr_data1=(ir== UPDATE_WB_WR_DATA && udr );`
286			`wb_rd_data1=(ir==UPDATE_WB_RD_DATA && cdr);`
287			`//end`
288			`end`
289
290			`reg wb_wr_addr2, wb_wr_data2, wb_rd_data2;`
291			`reg wb_wr_addr3, wb_wr_data3, wb_rd_data3;`
292	48	alirezamon
293			`ifdef SYNC_RESET_MODE
294			`always @ (posedge clk )begin`
295			`else
296			`always @ (posedge clk or posedge reset)begin`
297			`endif
298	38	alirezamon
299			`if( reset ) begin`
300			`wb_wr_addr2<=1'b0;`
301			`wb_wr_data2<=1'b0;`
302			`wb_wr_addr3<=1'b0;`
303			`wb_wr_data3<=1'b0;`
304			`wb_rd_data2<=1'b0;`
305			`wb_rd_data3<=1'b0;`
306			`end else begin`
307			`wb_wr_addr2<=wb_wr_addr1;`
308			`wb_wr_data2<=wb_wr_data1;`
309			`wb_wr_addr3<=wb_wr_addr2;`
310			`wb_wr_data3<=wb_wr_data2;`
311			`wb_rd_data2<=wb_rd_data1;`
312			`wb_rd_data3<=wb_rd_data2;`
313			`end`
314			`end`
315
316			`assign wb_wr_addr_en =(wb_wr_addr2 & ~wb_wr_addr3);`
317			`assign wb_wr_data_en =(wb_wr_data2 & ~wb_wr_data3);`
318			`assign wb_rd_data_en =(wb_rd_data2 & ~wb_rd_data3);`
319			`endmodule`
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