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/**********************************************************************
**      File:  wishbone_bus.v
**
**
**      Copyright (C) 2014-2017  Alireza Monemi
**
**      This file is part of ProNoC
**
**      ProNoC ( stands for Prototype Network-on-chip)  is free software:
**      you can redistribute it and/or modify it under the terms of the GNU
**      Lesser General Public License as published by the Free Software Foundation,
**      either version 2 of the License, or (at your option) any later version.
**
**      ProNoC is distributed in the hope that it will be useful, but WITHOUT
**      ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
**      or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
**      Public License for more details.
**
**      You should have received a copy of the GNU Lesser General Public
**      License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
**
**
**      Description:
**      parametrizable wishbone bus
**
*******************************************************************/
 
 
 
 
 
 
 
 
`timescale   10ns/1ns
 
 
module wishbone_bus #(
 
        parameter M        =   4,               //number of master port
        parameter S        =   4,               //number of slave port
        parameter Dw       =   32,         // maximum data width
        parameter Aw       =   32,    // address width
        parameter SELw     =   2,
        parameter TAGw     =   3,    //merged  {tga,tgb,tgc}
        parameter CTIw     =   3,
        parameter BTEw     =   2
 
 
)
(
        //slaves interface
        s_adr_o_all,
        s_dat_o_all,
        s_sel_o_all,
        s_tag_o_all,
        s_we_o_all,
        s_cyc_o_all,
        s_stb_o_all,
        s_cti_o_all,
    s_bte_o_all,
 
        s_dat_i_all,
        s_ack_i_all,
        s_err_i_all,
        s_rty_i_all,
 
 
        //masters interface
        m_dat_o_all,
        m_ack_o_all,
        m_err_o_all,
        m_rty_o_all,
 
 
        m_adr_i_all,
        m_dat_i_all,
        m_sel_i_all,
        m_tag_i_all,
        m_we_i_all,
        m_stb_i_all,
        m_cyc_i_all,
        m_cti_i_all,
    m_bte_i_all,
 
        //address compar
        m_grant_addr,
    s_sel_one_hot,
 
 
        //system signals
 
        clk,
        reset
 
);
 
    function integer log2;
      input integer number; begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction // log2 
 
 
 
    localparam  DwS     =   Dw * S,
                AwS     =   Aw * S,
                SELwS   =   SELw * S,
                TAGwS   =   TAGw * S,
                CTIwS   =   CTIw * S,
                BTEwS   =   BTEw * S,
                DwM     =   Dw * M,
                AwM     =   Aw  * M,
                SELwM   =   SELw   * M,
                TAGwM   =   TAGw   * M,
                Mw      =   (M>1)? log2(M):1,
                Sw      =   (S>1)? log2(S):1,
                CTIwM   =   CTIw * M,
                BTEwM   =   BTEw * M;
 
 
 
 
 
    output  [AwS-1      :   0]   s_adr_o_all;
    output  [DwS-1      :   0]   s_dat_o_all;
    output  [SELwS-1    :   0]   s_sel_o_all;
    output  [TAGwS-1    :   0]   s_tag_o_all;
    output  [S-1        :   0]   s_we_o_all;
    output  [S-1        :   0]   s_cyc_o_all;
    output  [S-1        :   0]   s_stb_o_all;
    output  [CTIwS-1    :   0]   s_cti_o_all;
    output  [BTEwS-1    :   0]   s_bte_o_all;
 
 
    input   [DwS-1      :   0]   s_dat_i_all;
    input   [S-1        :   0]   s_ack_i_all;
    input   [S-1        :   0]   s_err_i_all;
    input   [S-1        :   0]   s_rty_i_all;
 
 
 
 
 
    //masters interface
    output  [DwM-1      :   0]   m_dat_o_all;
    output  [M-1        :   0]   m_ack_o_all;
    output  [M-1        :   0]   m_err_o_all;
    output  [M-1        :   0]   m_rty_o_all;
 
 
    input   [AwM-1      :   0]   m_adr_i_all;
    input   [DwM-1      :   0]   m_dat_i_all;
    input   [SELwM-1    :   0]   m_sel_i_all;
    input   [TAGwM-1    :   0]   m_tag_i_all;
    input   [M-1        :   0]   m_we_i_all;
    input   [M-1        :   0]   m_stb_i_all;
    input   [M-1        :   0]   m_cyc_i_all;
    input   [CTIwM-1    :   0]   m_cti_i_all;
    input   [BTEwM-1    :   0]   m_bte_i_all;
 
    //
     output [Aw-1       :   0]  m_grant_addr;
     input  [S-1        :   0]  s_sel_one_hot;
    //system signals
 
    input                           clk,     reset;
 
 
    wire                            any_s_ack,any_s_err,any_s_rty;
    wire                        m_grant_we,m_grant_stb,m_grant_cyc;
 
    wire    [Dw-1       :       0]       m_grant_dat,s_read_dat;
    wire        [SELw-1     :   0]       m_grant_sel;
    wire    [BTEw-1     :   0]  m_grant_bte;
    wire    [CTIw-1     :   0]  m_grant_cti;
    wire        [TAGw-1     :   0]       m_grant_tag;
 
 
    wire        [Sw-1       :   0]       s_sel_bin;
    wire        [M-1        :   0]       m_grant_onehot;
    wire        [Mw-1       :   0]       m_grant_bin;
 
    wire        [Aw-1      :    0]       s_adr_o;
    wire        [Dw-1      :    0]       s_dat_o;
    wire        [SELw-1    :    0]       s_sel_o;
    wire    [BTEw-1    :    0]  s_bte_o;
    wire    [CTIw-1    :    0]  s_cti_o;
 
    wire        [TAGw-1    :    0]       s_tag_o;
    wire                        s_we_o;
    wire                        s_cyc_o;
    wire        [Dw-1       :   0]       m_dat_o;
 
 
    assign      s_adr_o_all     =       {S{s_adr_o}};
    assign      s_dat_o_all     =       {S{s_dat_o}};
    assign      s_sel_o_all     =       {S{s_sel_o}};
    assign  s_cti_o_all =   {S{s_cti_o}};
    assign  s_bte_o_all =   {S{s_bte_o}};
 
    assign      s_tag_o_all     =       {S{s_tag_o}};
    assign      s_we_o_all      =       {S{s_we_o}};
    assign      s_cyc_o_all     =       {S{s_cyc_o}};
    assign      m_dat_o_all=    {M{m_dat_o}};
 
    assign      any_s_ack   =|  s_ack_i_all;
    assign      any_s_err   =|  s_err_i_all;
    assign      any_s_rty   =|  s_rty_i_all;
 
    assign      s_adr_o     =   m_grant_addr;
    assign      s_dat_o     =   m_grant_dat;
    assign      s_sel_o     =   m_grant_sel;
    assign  s_bte_o     =   m_grant_bte;
    assign  s_cti_o     =   m_grant_cti;
    assign      s_tag_o     =   m_grant_tag;
    assign      s_we_o      =   m_grant_we;
    assign      s_cyc_o     =   m_grant_cyc;
    assign      s_stb_o_all     =       s_sel_one_hot & {S{m_grant_stb & m_grant_cyc}};
 
 
//wire  [ADDR_PERFIX-1          :       0]      m_perfix_addr;
//assign m_perfix_addr          =       m_grant_addr[Aw-3       :       Aw-ADDR_PERFIX-2];
 
 
assign  m_dat_o         =       s_read_dat;
assign  m_ack_o_all     =       m_grant_onehot  & {M{any_s_ack}};
assign  m_err_o_all     =       m_grant_onehot  & {M{any_s_err}};
assign  m_rty_o_all     =       m_grant_onehot  & {M{any_s_rty}};
 
 
 
 
//convert one hot to bin 
    one_hot_to_bin #(
        .ONE_HOT_WIDTH(S)
    )
    s_sel_conv
    (
        .one_hot_code(s_sel_one_hot),
        .bin_code(s_sel_bin)
    );
 
 
 
    one_hot_to_bin #(
        .ONE_HOT_WIDTH(M)
    )
    m_grant_conv
    (
        .one_hot_code   (m_grant_onehot),
        .bin_code               (m_grant_bin)
    );
 
 
 
    //slave multiplexer 
    binary_mux #(
        .IN_WIDTH       (DwS),
        .OUT_WIDTH      (Dw)
    )
     s_read_data_mux
    (
        .mux_in         (s_dat_i_all),
        .mux_out                (s_read_dat),
        .sel                    (s_sel_bin)
 
    );
 
 
    //master ports multiplexers
 
    binary_mux #(
        .IN_WIDTH       (AwM),
        .OUT_WIDTH      (Aw)
    )
     m_adr_mux
    (
        .mux_in         (m_adr_i_all),
        .mux_out                (m_grant_addr),
        .sel                    (m_grant_bin)
 
    );
 
 
 
    binary_mux #(
        .IN_WIDTH       (DwM),
        .OUT_WIDTH      (Dw)
    )
     m_data_mux
    (
        .mux_in         (m_dat_i_all),
        .mux_out                (m_grant_dat),
        .sel                    (m_grant_bin)
 
    );
 
 
 
    binary_mux #(
        .IN_WIDTH       (SELwM),
        .OUT_WIDTH      (SELw)
    )
     m_sel_mux
    (
        .mux_in         (m_sel_i_all),
        .mux_out                (m_grant_sel),
        .sel                    (m_grant_bin)
 
    );
 
     binary_mux #(
        .IN_WIDTH   (BTEwM),
        .OUT_WIDTH  (BTEw)
    )
     m_bte_mux
    (
        .mux_in         (m_bte_i_all),
        .mux_out        (m_grant_bte),
        .sel            (m_grant_bin)
 
    );
 
    binary_mux #(
        .IN_WIDTH   (CTIwM),
        .OUT_WIDTH  (CTIw)
    )
     m_cti_mux
    (
        .mux_in         (m_cti_i_all),
        .mux_out        (m_grant_cti),
        .sel            (m_grant_bin)
 
    );
 
 
    binary_mux #(
        .IN_WIDTH       (TAGwM),
        .OUT_WIDTH      (TAGw)
    )
     m_tag_mux
    (
        .mux_in         (m_tag_i_all),
        .mux_out                (m_grant_tag),
        .sel                    (m_grant_bin)
 
    );
 
 
    binary_mux #(
        .IN_WIDTH       (M),
        .OUT_WIDTH      (1)
    )
     m_we_mux
    (
        .mux_in         (m_we_i_all),
        .mux_out                (m_grant_we),
        .sel                    (m_grant_bin)
 
    );
 
 
   /*
    binary_mux #(
        .IN_WIDTH       (M),
        .OUT_WIDTH      (1)
    )
     m_stb_mux
    (
        .mux_in         (m_stb_i_all),
        .mux_out                (m_grant_stb),
        .sel                    (m_grant_bin)
 
    );
 
 
 
    binary_mux #(
        .IN_WIDTH       (M),
        .OUT_WIDTH      (1)
    )
     m_cyc_mux
    (
        .mux_in         (m_cyc_i_all),
        .mux_out                (m_grant_cyc),
        .sel                    (m_grant_bin)
 
    );
   */
   // if m_grant_one_hot is zero the stb and cyc  must not be asserted hence have to use one-hot mux 
 
 
    one_hot_mux #(
        .IN_WIDTH(M),
        .SEL_WIDTH(M),
        .OUT_WIDTH(1)
    )
    m_stb_mux
    (
        .mux_in(m_stb_i_all),
        .mux_out(m_grant_stb),
        .sel(m_grant_onehot)
 
    );
 
 
     one_hot_mux #(
        .IN_WIDTH(M),
        .SEL_WIDTH(M),
        .OUT_WIDTH(1)
    )
     m_cyc_mux
    (
        .mux_in(m_cyc_i_all),
        .mux_out(m_grant_cyc),
        .sel(m_grant_onehot)
 
    );
 
 
 
 
 
generate
        if(M > 1) begin
                // round roubin arbiter
                bus_arbiter # (
                        .M (M)
                )
                arbiter
                (
                        .request (m_cyc_i_all),
                        .grant  (m_grant_onehot),
                        .clk (clk),
                        .reset (reset)
                );
        end else begin // if we have just one master there is no needs for arbitration
                assign m_grant_onehot = m_cyc_i_all;
        end
endgenerate
 
 
 
endmodule
 
 
 
 
/**************
 
    bus_arbiter
 
**************/
 
module bus_arbiter # (
        parameter M = 4
)
(
        request,
        grant,
        clk,
        reset
);
 
    input   [M-1    :       0]  request;
    output  [M-1    :       0]  grant;
    input                       clk, reset;
 
    wire                    comreq;
    wire    [M-1        :       0]       one_hot_arb_req, one_hot_arb_grant;
    reg     [M-1        :       0]       grant_registered;
 
    assign      one_hot_arb_req =       request  & {M{~comreq}};
    assign      grant                                   =       grant_registered;
 
    assign comreq       =       |(grant & request);
 
`ifdef SYNC_RESET_MODE
    always @ (posedge clk )begin
`else
    always @ (posedge clk or posedge reset)begin
`endif
 
           if (reset) begin
                  grant_registered      <= {M{1'b0}};
           end else begin
                  if(~comreq)   grant_registered        <=      one_hot_arb_grant;
           end
    end//always
 
 
    arbiter #(
           .ARBITER_WIDTH       (M )
    )
    the_combinational_arbiter
    (
           .request             (one_hot_arb_req),
           .grant               (one_hot_arb_grant),
           .any_grant   (),
           .clk                 (clk),
           .reset               (reset)
    );
 
 
 
 
endmodule

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_c/] [jtag/] [test_rtl/] [jtag_ram_test/] [src_verilog/] [lib/] [wishbone_bus.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	38	alirezamon	`/**********************************************************************`
2			`** File: wishbone_bus.v`
3			`**`
4			`**`
5			`** Copyright (C) 2014-2017 Alireza Monemi`
6			`**`
7			`** This file is part of ProNoC`
8			`**`
9			`** ProNoC ( stands for Prototype Network-on-chip) is free software:`
10			`** you can redistribute it and/or modify it under the terms of the GNU`
11			`** Lesser General Public License as published by the Free Software Foundation,`
12			`** either version 2 of the License, or (at your option) any later version.`
13			`**`
14			`** ProNoC is distributed in the hope that it will be useful, but WITHOUT`
15			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
16			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
17			`** Public License for more details.`
18			`**`
19			`** You should have received a copy of the GNU Lesser General Public`
20			` License along with ProNoC. If not, see <http:www.gnu.org/licenses/>.`
21			`**`
22			`**`
23			`** Description:`
24			`** parametrizable wishbone bus`
25			`**`
26			`*******************************************************************/`
27
28
29
30
31
32
33
34
35			`timescale 10ns/1ns
36
37
38			`module wishbone_bus #(`
39
40			`parameter M = 4, //number of master port`
41			`parameter S = 4, //number of slave port`
42			`parameter Dw = 32, // maximum data width`
43			`parameter Aw = 32, // address width`
44			`parameter SELw = 2,`
45			`parameter TAGw = 3, //merged {tga,tgb,tgc}`
46			`parameter CTIw = 3,`
47			`parameter BTEw = 2`
48
49
50			`)`
51			`(`
52			`//slaves interface`
53			`s_adr_o_all,`
54			`s_dat_o_all,`
55			`s_sel_o_all,`
56			`s_tag_o_all,`
57			`s_we_o_all,`
58			`s_cyc_o_all,`
59			`s_stb_o_all,`
60			`s_cti_o_all,`
61			`s_bte_o_all,`
62
63			`s_dat_i_all,`
64			`s_ack_i_all,`
65			`s_err_i_all,`
66			`s_rty_i_all,`
67
68
69			`//masters interface`
70			`m_dat_o_all,`
71			`m_ack_o_all,`
72			`m_err_o_all,`
73			`m_rty_o_all,`
74
75
76			`m_adr_i_all,`
77			`m_dat_i_all,`
78			`m_sel_i_all,`
79			`m_tag_i_all,`
80			`m_we_i_all,`
81			`m_stb_i_all,`
82			`m_cyc_i_all,`
83			`m_cti_i_all,`
84			`m_bte_i_all,`
85
86			`//address compar`
87			`m_grant_addr,`
88			`s_sel_one_hot,`
89
90
91			`//system signals`
92
93			`clk,`
94			`reset`
95
96			`);`
97
98			`function integer log2;`
99			`input integer number; begin`
100			`log2=0;`
101			`while(2**log2<number) begin`
102			`log2=log2+1;`
103			`end`
104			`end`
105			`endfunction // log2`
106
107
108
109			`localparam DwS = Dw * S,`
110			`AwS = Aw * S,`
111			`SELwS = SELw * S,`
112			`TAGwS = TAGw * S,`
113			`CTIwS = CTIw * S,`
114			`BTEwS = BTEw * S,`
115			`DwM = Dw * M,`
116			`AwM = Aw * M,`
117			`SELwM = SELw * M,`
118			`TAGwM = TAGw * M,`
119			`Mw = (M>1)? log2(M):1,`
120			`Sw = (S>1)? log2(S):1,`
121			`CTIwM = CTIw * M,`
122			`BTEwM = BTEw * M;`
123
124
125
126
127
128			`output [AwS-1 : 0] s_adr_o_all;`
129			`output [DwS-1 : 0] s_dat_o_all;`
130			`output [SELwS-1 : 0] s_sel_o_all;`
131			`output [TAGwS-1 : 0] s_tag_o_all;`
132			`output [S-1 : 0] s_we_o_all;`
133			`output [S-1 : 0] s_cyc_o_all;`
134			`output [S-1 : 0] s_stb_o_all;`
135			`output [CTIwS-1 : 0] s_cti_o_all;`
136			`output [BTEwS-1 : 0] s_bte_o_all;`
137
138
139			`input [DwS-1 : 0] s_dat_i_all;`
140			`input [S-1 : 0] s_ack_i_all;`
141			`input [S-1 : 0] s_err_i_all;`
142			`input [S-1 : 0] s_rty_i_all;`
143
144
145
146
147
148			`//masters interface`
149			`output [DwM-1 : 0] m_dat_o_all;`
150			`output [M-1 : 0] m_ack_o_all;`
151			`output [M-1 : 0] m_err_o_all;`
152			`output [M-1 : 0] m_rty_o_all;`
153
154
155			`input [AwM-1 : 0] m_adr_i_all;`
156			`input [DwM-1 : 0] m_dat_i_all;`
157			`input [SELwM-1 : 0] m_sel_i_all;`
158			`input [TAGwM-1 : 0] m_tag_i_all;`
159			`input [M-1 : 0] m_we_i_all;`
160			`input [M-1 : 0] m_stb_i_all;`
161			`input [M-1 : 0] m_cyc_i_all;`
162			`input [CTIwM-1 : 0] m_cti_i_all;`
163			`input [BTEwM-1 : 0] m_bte_i_all;`
164
165			`//`
166			`output [Aw-1 : 0] m_grant_addr;`
167			`input [S-1 : 0] s_sel_one_hot;`
168			`//system signals`
169
170			`input clk, reset;`
171
172
173			`wire any_s_ack,any_s_err,any_s_rty;`
174			`wire m_grant_we,m_grant_stb,m_grant_cyc;`
175
176			`wire [Dw-1 : 0] m_grant_dat,s_read_dat;`
177			`wire [SELw-1 : 0] m_grant_sel;`
178			`wire [BTEw-1 : 0] m_grant_bte;`
179			`wire [CTIw-1 : 0] m_grant_cti;`
180			`wire [TAGw-1 : 0] m_grant_tag;`
181
182
183			`wire [Sw-1 : 0] s_sel_bin;`
184			`wire [M-1 : 0] m_grant_onehot;`
185			`wire [Mw-1 : 0] m_grant_bin;`
186
187			`wire [Aw-1 : 0] s_adr_o;`
188			`wire [Dw-1 : 0] s_dat_o;`
189			`wire [SELw-1 : 0] s_sel_o;`
190			`wire [BTEw-1 : 0] s_bte_o;`
191			`wire [CTIw-1 : 0] s_cti_o;`
192
193			`wire [TAGw-1 : 0] s_tag_o;`
194			`wire s_we_o;`
195			`wire s_cyc_o;`
196			`wire [Dw-1 : 0] m_dat_o;`
197
198
199			`assign s_adr_o_all = {S{s_adr_o}};`
200			`assign s_dat_o_all = {S{s_dat_o}};`
201			`assign s_sel_o_all = {S{s_sel_o}};`
202			`assign s_cti_o_all = {S{s_cti_o}};`
203			`assign s_bte_o_all = {S{s_bte_o}};`
204
205			`assign s_tag_o_all = {S{s_tag_o}};`
206			`assign s_we_o_all = {S{s_we_o}};`
207			`assign s_cyc_o_all = {S{s_cyc_o}};`
208			`assign m_dat_o_all= {M{m_dat_o}};`
209
210			`assign any_s_ack =\| s_ack_i_all;`
211			`assign any_s_err =\| s_err_i_all;`
212			`assign any_s_rty =\| s_rty_i_all;`
213
214			`assign s_adr_o = m_grant_addr;`
215			`assign s_dat_o = m_grant_dat;`
216			`assign s_sel_o = m_grant_sel;`
217			`assign s_bte_o = m_grant_bte;`
218			`assign s_cti_o = m_grant_cti;`
219			`assign s_tag_o = m_grant_tag;`
220			`assign s_we_o = m_grant_we;`
221			`assign s_cyc_o = m_grant_cyc;`
222			`assign s_stb_o_all = s_sel_one_hot & {S{m_grant_stb & m_grant_cyc}};`
223
224
225			`//wire [ADDR_PERFIX-1 : 0] m_perfix_addr;`
226			`//assign m_perfix_addr = m_grant_addr[Aw-3 : Aw-ADDR_PERFIX-2];`
227
228
229			`assign m_dat_o = s_read_dat;`
230			`assign m_ack_o_all = m_grant_onehot & {M{any_s_ack}};`
231			`assign m_err_o_all = m_grant_onehot & {M{any_s_err}};`
232			`assign m_rty_o_all = m_grant_onehot & {M{any_s_rty}};`
233
234
235
236
237			`//convert one hot to bin`
238			`one_hot_to_bin #(`
239			`.ONE_HOT_WIDTH(S)`
240			`)`
241			`s_sel_conv`
242			`(`
243			`.one_hot_code(s_sel_one_hot),`
244			`.bin_code(s_sel_bin)`
245			`);`
246
247
248
249			`one_hot_to_bin #(`
250			`.ONE_HOT_WIDTH(M)`
251			`)`
252			`m_grant_conv`
253			`(`
254			`.one_hot_code (m_grant_onehot),`
255			`.bin_code (m_grant_bin)`
256			`);`
257
258
259
260			`//slave multiplexer`
261			`binary_mux #(`
262			`.IN_WIDTH (DwS),`
263			`.OUT_WIDTH (Dw)`
264			`)`
265			`s_read_data_mux`
266			`(`
267			`.mux_in (s_dat_i_all),`
268			`.mux_out (s_read_dat),`
269			`.sel (s_sel_bin)`
270
271			`);`
272
273
274			`//master ports multiplexers`
275
276			`binary_mux #(`
277			`.IN_WIDTH (AwM),`
278			`.OUT_WIDTH (Aw)`
279			`)`
280			`m_adr_mux`
281			`(`
282			`.mux_in (m_adr_i_all),`
283			`.mux_out (m_grant_addr),`
284			`.sel (m_grant_bin)`
285
286			`);`
287
288
289
290			`binary_mux #(`
291			`.IN_WIDTH (DwM),`
292			`.OUT_WIDTH (Dw)`
293			`)`
294			`m_data_mux`
295			`(`
296			`.mux_in (m_dat_i_all),`
297			`.mux_out (m_grant_dat),`
298			`.sel (m_grant_bin)`
299
300			`);`
301
302
303
304			`binary_mux #(`
305			`.IN_WIDTH (SELwM),`
306			`.OUT_WIDTH (SELw)`
307			`)`
308			`m_sel_mux`
309			`(`
310			`.mux_in (m_sel_i_all),`
311			`.mux_out (m_grant_sel),`
312			`.sel (m_grant_bin)`
313
314			`);`
315
316			`binary_mux #(`
317			`.IN_WIDTH (BTEwM),`
318			`.OUT_WIDTH (BTEw)`
319			`)`
320			`m_bte_mux`
321			`(`
322			`.mux_in (m_bte_i_all),`
323			`.mux_out (m_grant_bte),`
324			`.sel (m_grant_bin)`
325
326			`);`
327
328			`binary_mux #(`
329			`.IN_WIDTH (CTIwM),`
330			`.OUT_WIDTH (CTIw)`
331			`)`
332			`m_cti_mux`
333			`(`
334			`.mux_in (m_cti_i_all),`
335			`.mux_out (m_grant_cti),`
336			`.sel (m_grant_bin)`
337
338			`);`
339
340
341			`binary_mux #(`
342			`.IN_WIDTH (TAGwM),`
343			`.OUT_WIDTH (TAGw)`
344			`)`
345			`m_tag_mux`
346			`(`
347			`.mux_in (m_tag_i_all),`
348			`.mux_out (m_grant_tag),`
349			`.sel (m_grant_bin)`
350
351			`);`
352
353
354			`binary_mux #(`
355			`.IN_WIDTH (M),`
356			`.OUT_WIDTH (1)`
357			`)`
358			`m_we_mux`
359			`(`
360			`.mux_in (m_we_i_all),`
361			`.mux_out (m_grant_we),`
362			`.sel (m_grant_bin)`
363
364			`);`
365
366
367			`/*`
368			`binary_mux #(`
369			`.IN_WIDTH (M),`
370			`.OUT_WIDTH (1)`
371			`)`
372			`m_stb_mux`
373			`(`
374			`.mux_in (m_stb_i_all),`
375			`.mux_out (m_grant_stb),`
376			`.sel (m_grant_bin)`
377
378			`);`
379
380
381
382			`binary_mux #(`
383			`.IN_WIDTH (M),`
384			`.OUT_WIDTH (1)`
385			`)`
386			`m_cyc_mux`
387			`(`
388			`.mux_in (m_cyc_i_all),`
389			`.mux_out (m_grant_cyc),`
390			`.sel (m_grant_bin)`
391
392			`);`
393			`*/`
394			`// if m_grant_one_hot is zero the stb and cyc must not be asserted hence have to use one-hot mux`
395
396
397			`one_hot_mux #(`
398			`.IN_WIDTH(M),`
399			`.SEL_WIDTH(M),`
400			`.OUT_WIDTH(1)`
401			`)`
402			`m_stb_mux`
403			`(`
404			`.mux_in(m_stb_i_all),`
405			`.mux_out(m_grant_stb),`
406			`.sel(m_grant_onehot)`
407
408			`);`
409
410
411			`one_hot_mux #(`
412			`.IN_WIDTH(M),`
413			`.SEL_WIDTH(M),`
414			`.OUT_WIDTH(1)`
415			`)`
416			`m_cyc_mux`
417			`(`
418			`.mux_in(m_cyc_i_all),`
419			`.mux_out(m_grant_cyc),`
420			`.sel(m_grant_onehot)`
421
422			`);`
423
424
425
426
427
428			`generate`
429			`if(M > 1) begin`
430			`// round roubin arbiter`
431			`bus_arbiter # (`
432			`.M (M)`
433			`)`
434			`arbiter`
435			`(`
436			`.request (m_cyc_i_all),`
437			`.grant (m_grant_onehot),`
438			`.clk (clk),`
439			`.reset (reset)`
440			`);`
441			`end else begin // if we have just one master there is no needs for arbitration`
442			`assign m_grant_onehot = m_cyc_i_all;`
443			`end`
444			`endgenerate`
445
446
447
448			`endmodule`
449
450
451
452
453			`/**************`
454
455			`bus_arbiter`
456
457			`**************/`
458
459			`module bus_arbiter # (`
460			`parameter M = 4`
461			`)`
462			`(`
463			`request,`
464			`grant,`
465			`clk,`
466			`reset`
467			`);`
468
469			`input [M-1 : 0] request;`
470			`output [M-1 : 0] grant;`
471			`input clk, reset;`
472
473			`wire comreq;`
474			`wire [M-1 : 0] one_hot_arb_req, one_hot_arb_grant;`
475			`reg [M-1 : 0] grant_registered;`
476
477			`assign one_hot_arb_req = request & {M{~comreq}};`
478			`assign grant = grant_registered;`
479
480			`assign comreq = \|(grant & request);`
481
482	48	alirezamon	`ifdef SYNC_RESET_MODE
483			`always @ (posedge clk )begin`
484			`else
485			`always @ (posedge clk or posedge reset)begin`
486			`endif
487
488	38	alirezamon	`if (reset) begin`
489			`grant_registered <= {M{1'b0}};`
490			`end else begin`
491			`if(~comreq) grant_registered <= one_hot_arb_grant;`
492			`end`
493			`end//always`
494
495
496			`arbiter #(`
497			`.ARBITER_WIDTH (M )`
498			`)`
499			`the_combinational_arbiter`
500			`(`
501			`.request (one_hot_arb_req),`
502			`.grant (one_hot_arb_grant),`
503			`.any_grant (),`
504			`.clk (clk),`
505			`.reset (reset)`
506			`);`
507
508
509
510
511			`endmodule`