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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [sw/] [aemb/] [custom_crt/] [crtinit.s] - Blame information for rev 48

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###################################-*-asm*-
#
# Copyright (c) 2001 Xilinx, Inc.  All rights reserved.
#
# Xilinx, Inc.
#
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
# crtinit.s
#
# Default second stage of C run-time initialization
#
# $Id: crtinit.s,v 1.5.2.7 2006/07/05 18:53:54 vasanth Exp $
#
#######################################
 
 
 
        .globl _crtinit
        .align 2
        .ent _crtinit
 
_crtinit:
        addi    r1, r1, -20                     /* Save Link register    */
        swi     r15, r1, 0
 
        addi    r6, r0, __sbss_start            /* clear SBSS */
        addi    r7, r0, __sbss_end
        rsub    r18, r6, r7
        blei    r18, .Lendsbss
 
.Lloopsbss:
        swi     r0, r6, 0
        addi    r6, r6, 4
        rsub    r18, r6, r7
        bgti    r18, .Lloopsbss
.Lendsbss:
 
        addi    r6, r0, __bss_start             /* clear BSS */
        addi    r7, r0, __bss_end
        rsub    r18, r6, r7
        blei    r18, .Lendbss
.Lloopbss:
        swi     r0, r6, 0
        addi    r6, r6, 4
        rsub    r18, r6, r7
        bgti    r18, .Lloopbss
.Lendbss:
 
        brlid   r15, _program_init              /* Initialize the program  */
        nop
 
#        brlid   r15, __init                     /* Invoke language initialization functions */
#        nop
 
        addi    r6, r0, 0                       /* Initialize argc = 1 and argv = NULL and envp = NULL  */
        addi    r7, r0, 0
        brlid   r15, (__main)              /*initial_global_data first and then call main
        addi    r5, r0, 0
 
        addik   r19, r3, 0                      /* Save return value */
 
#        brlid   r15, __fini                     /* Invoke language cleanup functions */
#        nop
 
        brlid   r15, _program_clean             /* Cleanup the program  */
        nop
 
        lw      r15, r1, r0                     /* Return back to CRT   */
 
        addik   r3, r19, 0                      /* Restore return value */
        rtsd    r15, 8
        addi    r1, r1, 20
        .end _crtinit
 

Line No.	Rev	Author	Line
1	48	alirezamon	`###################################--asm-`
2			`#`
3			`# Copyright (c) 2001 Xilinx, Inc. All rights reserved.`
4			`#`
5			`# Xilinx, Inc.`
6			`#`
7			`# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A`
8			`# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS`
9			`# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR`
10			`# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION`
11			`# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE`
12			`# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.`
13			`# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO`
14			`# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO`
15			`# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE`
16			`# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY`
17			`# AND FITNESS FOR A PARTICULAR PURPOSE.`
18			`#`
19			`# crtinit.s`
20			`#`
21			`# Default second stage of C run-time initialization`
22			`#`
23			`# $Id: crtinit.s,v 1.5.2.7 2006/07/05 18:53:54 vasanth Exp $`
24			`#`
25			`#######################################`
26
27
28
29			`.globl _crtinit`
30			`.align 2`
31			`.ent _crtinit`
32
33			`_crtinit:`
34			`addi r1, r1, -20 /* Save Link register */`
35			`swi r15, r1, 0`
36
37			`addi r6, r0, __sbss_start /* clear SBSS */`
38			`addi r7, r0, __sbss_end`
39			`rsub r18, r6, r7`
40			`blei r18, .Lendsbss`
41
42			`.Lloopsbss:`
43			`swi r0, r6, 0`
44			`addi r6, r6, 4`
45			`rsub r18, r6, r7`
46			`bgti r18, .Lloopsbss`
47			`.Lendsbss:`
48
49			`addi r6, r0, __bss_start /* clear BSS */`
50			`addi r7, r0, __bss_end`
51			`rsub r18, r6, r7`
52			`blei r18, .Lendbss`
53			`.Lloopbss:`
54			`swi r0, r6, 0`
55			`addi r6, r6, 4`
56			`rsub r18, r6, r7`
57			`bgti r18, .Lloopbss`
58			`.Lendbss:`
59
60			`brlid r15, _program_init /* Initialize the program */`
61			`nop`
62
63			`# brlid r15, __init /* Invoke language initialization functions */`
64			`# nop`
65
66			`addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */`
67			`addi r7, r0, 0`
68			`brlid r15, (__main) /*initial_global_data first and then call main`
69			`addi r5, r0, 0`
70
71			`addik r19, r3, 0 /* Save return value */`
72
73			`# brlid r15, __fini /* Invoke language cleanup functions */`
74			`# nop`
75
76			`brlid r15, _program_clean /* Cleanup the program */`
77			`nop`
78
79			`lw r15, r1, r0 /* Return back to CRT */`
80
81			`addik r3, r19, 0 /* Restore return value */`
82			`rtsd r15, 8`
83			`addi r1, r1, 20`
84			`.end _crtinit`
85

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [sw/] [aemb/] [custom_crt/] [crtinit.s] - Blame information for rev 48