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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [aemb.v] - Blame information for rev 17

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Line No. Rev Author Line
1 16 alirezamon 
module aeMB_top (
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  dwb_adr_o,
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  dwb_cyc_o,
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  dwb_dat_o,
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  dwb_sel_o,
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  dwb_stb_o,
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  dwb_tag_o,
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  dwb_wre_o,
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  dwb_cti_o,
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  dwb_bte_o,
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  dwb_ack_i,
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  dwb_dat_i,
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  dwb_err_i,
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  dwb_rty_i,
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  iwb_adr_o,
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  iwb_cyc_o,
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  iwb_sel_o,
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  iwb_stb_o,
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  iwb_tag_o,
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  iwb_wre_o,
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  iwb_dat_o,
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  iwb_cti_o,
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  iwb_bte_o,
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  iwb_ack_i,
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  iwb_dat_i,
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  iwb_err_i,
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  iwb_rty_i,
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  clk,
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  reset,
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  sys_int_i,
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  sys_ena_i // input  sys_ena_i
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);
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   parameter AEMB_IWB = 32; ///< INST bus width
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   parameter AEMB_DWB = 32; ///< DATA bus width
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   parameter AEMB_XWB = 7; ///< XCEL bus width
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   // CACHE PARAMETERS
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   parameter AEMB_ICH = 11; ///< instruction cache size
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   parameter AEMB_IDX = 6; ///< cache index size
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   // OPTIONAL HARDWARE
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   parameter AEMB_BSF = 1; ///< optional barrel shift
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   parameter AEMB_MUL = 1; ///< optional multiplier
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   output [31:0] dwb_adr_o;
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   output        dwb_cyc_o;
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   output [31:0] dwb_dat_o;
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   output [3:0]  dwb_sel_o;
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   output        dwb_stb_o;
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   output  [2:0] dwb_tag_o;
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   output        dwb_wre_o;
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   output  [2:0] dwb_cti_o;
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   output  [1:0] dwb_bte_o;
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   input         dwb_ack_i;
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   input [31:0]  dwb_dat_i;
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   output [31:0] iwb_adr_o;
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   output        iwb_cyc_o;
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   output [3:0]  iwb_sel_o;
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   output        iwb_stb_o;
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   output [2:0]  iwb_tag_o;
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   output        iwb_wre_o;
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   input         iwb_ack_i;
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   input [31:0]  iwb_dat_i;
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   output[31:0]  iwb_dat_o;
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   output  [2:0] iwb_cti_o;
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   output  [1:0] iwb_bte_o;
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   input         clk;
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   input        sys_ena_i;
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   input        sys_int_i;
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   input        reset;
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   wire         i_tag,d_tag;
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90 16 alirezamon 
 // not used but added to prevent warning
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  input dwb_err_i, dwb_rty_i,  iwb_err_i, iwb_rty_i;
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aeMB2_edk63 #(
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            .AEMB_IWB (AEMB_IWB), ///< INST bus width
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            .AEMB_DWB (AEMB_DWB), ///< DATA bus width
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            .AEMB_XWB (AEMB_XWB), ///< XCEL bus width
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            .AEMB_ICH (AEMB_ICH), ///< instruction cache size
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            .AEMB_IDX (AEMB_IDX),///< cache index size
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            .AEMB_BSF (AEMB_BSF), ///< optional barrel shift
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            .AEMB_MUL (AEMB_MUL) ///< optional multiplier
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        )
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         aeMB2_edk63_inst
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        (
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            .xwb_wre_o() ,  //    xwb_wre_o
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            .xwb_tag_o() ,  //    xwb_tag_o
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            .xwb_stb_o() ,  //    xwb_stb_o
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            .xwb_sel_o() ,  //   [3:0] xwb_sel_o
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            .xwb_dat_o() ,  //   [31:0] xwb_dat_o
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            .xwb_cyc_o() ,  //    xwb_cyc_o
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            .xwb_adr_o() ,  //   [AEMB_XWB-1:2] xwb_adr_o
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            .iwb_wre_o(iwb_wre_o) ,  //    iwb_wre_o
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            .iwb_tag_o(i_tag) ,  //    iwb_tag_o
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            .iwb_stb_o(iwb_stb_o) ,  //    iwb_stb_o
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            .iwb_sel_o(iwb_sel_o) ,  //   [3:0] iwb_sel_o
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            .iwb_cyc_o(iwb_cyc_o) ,  //    iwb_cyc_o
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            .iwb_adr_o(iwb_adr_o[29:0]) ,    //   [AEMB_IWB-1:2] iwb_adr_o
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            .dwb_wre_o(dwb_wre_o) ,  //    dwb_wre_o
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            .dwb_tag_o(d_tag) ,  //    dwb_tag_o
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            .dwb_stb_o(dwb_stb_o) ,  //    dwb_stb_o
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            .dwb_sel_o(dwb_sel_o) ,  //   [3:0] dwb_sel_o
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            .dwb_dat_o(dwb_dat_o) ,  //   [31:0] dwb_dat_o
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            .dwb_cyc_o(dwb_cyc_o) ,  //    dwb_cyc_o
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            .dwb_adr_o(dwb_adr_o [29:0]) ,    //   [AEMB_DWB-1:2] dwb_adr_o
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            .xwb_dat_i(0) , // input [31:0] xwb_dat_i
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            .xwb_ack_i(1'b0) ,  // input  xwb_ack_i
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            .sys_rst_i(reset) ,   // input  sys_rst_i
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            .sys_int_i(sys_int_i) , // input  sys_int_i
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            .sys_ena_i(sys_ena_i) , // input  sys_ena_i
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            .sys_clk_i(clk  ) ,   // input  sys_clk_i
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            .iwb_dat_i(iwb_dat_i) ,  // input [31:0] iwb_dat_i
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            .iwb_ack_i(iwb_ack_i) ,  // input  iwb_ack_i
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            .dwb_dat_i(dwb_dat_i) ,  // input [31:0] dwb_dat_i
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            .dwb_ack_i(dwb_ack_i)    // input  dwb_ack_i
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        );
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        assign iwb_dat_o = 0;
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        // I have no idea which tag (a,b or c) is used in aemb. I assume it is address tag (taga)
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        assign iwb_tag_o        = {i_tag,2'b00};
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        assign dwb_tag_o        = {d_tag,2'b00};
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        assign iwb_adr_o[31:30] = 2'b00;
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        assign dwb_adr_o[31:30] = 2'b00;
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        assign dwb_cti_o        = 3'd0;
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        assign dwb_bte_o        = 2'd0;
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        assign iwb_cti_o        = 3'd0;
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        assign iwb_bte_o        = 2'd0;
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endmodule
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