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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_gprf.v] - Blame information for rev 16

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/* $Id: aeMB2_gprf.v,v 1.4 2008-04-26 17:57:43 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>
**
** This file is part of AEMB.
**
** AEMB is free software: you can redistribute it and/or modify it
** under the terms of the GNU Lesser General Public License as
** published by the Free Software Foundation, either version 3 of the
** License, or (at your option) any later version.
**
** AEMB is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
** Public License for more details.
**
** You should have received a copy of the GNU Lesser General Public
** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
*/
/**
 * General Purpose Register File
 * @aeMB2_gprf.v
 
 * Dual set of 32 general purpose registers for the core. These are
   R0-R31. A zero is written to R0 for both sets during reset and
   maintained after that.
 
 */
`timescale  1ns/1ps
module aeMB2_gprf (/*AUTOARG*/
   // Outputs
   opa_if, opb_if, opd_if,
   // Inputs
   mux_of, mux_ex, ich_dat, rd_of, rd_ex, sel_mx, rpc_mx, xwb_mx,
   dwb_mx, alu_mx, sfr_mx, mul_mx, bsf_mx, gclk, grst, dena, gpha
   );
   parameter AEMB_HTX = 1;
 
   // INTERNAL
   output [31:0] opa_if,
                 opb_if,
                 opd_if;
 
   input [2:0]    mux_of,
                 mux_ex;
   input [31:0]  ich_dat;
   input [4:0]    rd_of,
                 rd_ex;
 
   // DATA SOURCSE
   input [3:0]    sel_mx;
   input [31:2]  rpc_mx;
   input [31:0]  xwb_mx,
                 dwb_mx,
                 alu_mx,
                 sfr_mx,
                 mul_mx,
                 bsf_mx;
 
   // SYSTEM
   input         gclk,
                 grst,
                 dena,
                 gpha;
 
   /*AUTOWIRE*/
   /*AUTOREG*/
 
   wire [31:0]    opd_wr;
   reg [31:0]     rMEMA[63:0],
                 rMEMB[63:0],
                 rMEMD[63:0];
   reg [31:0]     mem_mx;
   reg [31:0]     regd;
   reg           wrb_fb;
   reg [4:0]      rd_mx;
   reg [2:0]      mux_mx;
 
   // PIPELINE
   always @(posedge gclk)
     if (grst) begin
        /*AUTORESET*/
        // Beginning of autoreset for uninitialized flops
        mux_mx <= 3'h0;
        rd_mx <= 5'h0;
        wrb_fb <= 1'h0;
        // End of automatics
     end else if (dena) begin
        wrb_fb <= #1 |rd_ex & |mux_ex; // FIXME: check mux
 
        rd_mx <= #1 rd_ex;
        mux_mx <= #1 mux_ex;
     end
 
   // LOAD SIZER   
   always @(/*AUTOSENSE*/dwb_mx or sel_mx or xwb_mx) begin
      case (sel_mx)
        // 8'bits
        4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
        4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
        4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
        4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
        // 16'bits
        4'hC: mem_mx <= #1 {16'd0, dwb_mx[31:16]};
        4'h3: mem_mx <= #1 {16'd0, dwb_mx[15:0]};
        // 32'bits
        4'hF: mem_mx <= #1 dwb_mx;
        // XSL bus
        4'h0: mem_mx <= #1 xwb_mx;
        default: mem_mx <= 32'hX;
      endcase // case (sel_mx)
   end // always @ (...
 
   // SELECT SOURCE
   localparam [2:0] MUX_SFR = 3'o7,
                    MUX_BSF = 3'o6,
                    MUX_MUL = 3'o5,
                    MUX_MEM = 3'o4,
 
                    MUX_RPC = 3'o2,
                    MUX_ALU = 3'o1,
                    MUX_NOP = 3'o0;
 
   always @(/*AUTOSENSE*/alu_mx or bsf_mx or mem_mx or mul_mx
            or mux_mx or rpc_mx or sfr_mx)
     case (mux_mx)
       MUX_ALU: regd <= #1 alu_mx; // ALU
       MUX_RPC: regd <= #1 {rpc_mx[31:2], 2'o0}; // PC Link
       MUX_MEM: regd <= #1 mem_mx; // RAM/FSL
       MUX_MUL: regd <= #1 mul_mx; // MULTIPLIER
       MUX_BSF: regd <= #1 bsf_mx; // SHIFTER
       MUX_NOP: regd <= #1 32'h0;
       MUX_SFR: regd <= #1 sfr_mx;
       default: regd <= #1 32'hX;
     endcase // case (mux_mx)
 
   // REGISTER FILE - Infer LUT memory
   wire [5:0]        wRD0 = {gpha, ich_dat[25:21]};
   wire [5:0]        wRA0 = {gpha, ich_dat[20:16]};
   wire [5:0]        wRB0 = {gpha, ich_dat[15:11]};
   wire [5:0]        wRW0 = {!gpha, rd_mx};
   wire             wWRE = grst | wrb_fb;
 
   wire [31:0]       wDA0,
                    wDB0,
                    wDD0;
 
   assign           opa_if = wDA0;
   assign           opb_if = wDB0;
   assign           opd_if = wDD0;
 
   /* aeMB2_dparam AUTO_TEMPLATE "_\([a-z,0-9]+\)" (
    .AW(6'd6),
    .DW(6'd32),
 
    .clk_i(gclk),
    .ena_i(dena),
 
    .dat_i(regd),
    .adr_i(wRW0[5:0]),
    .wre_i(wWRE),
    .dat_o(),
 
    .xwre_i(),
    .xdat_i(),
    .xadr_i(wR@[5:0]),
    .xdat_o(wD@[31:0]),
    ) */
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd6),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_A0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDA0[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW0[5:0]),              // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWRE),                  // Templated
      .xadr_i                           (wRA0[5:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd6),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_B0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDB0[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW0[5:0]),              // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWRE),                  // Templated
      .xadr_i                           (wRB0[5:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd6),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_D0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDD0[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW0[5:0]),              // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWRE),                  // Templated
      .xadr_i                           (wRD0[5:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
endmodule // aeMB2_gprf
 
/*
 $Log: not supported by cvs2svn $
 Revision 1.3  2008/04/26 01:09:06  sybreon
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 Revision 1.2  2008/04/20 16:34:32  sybreon
 Basic version with some features left out.
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 Initial import.
*/
 
`ifdef XXX
 
   wire [4:0]        wRD0 = (gpha) ? ich_dat[25:21] : 5'd0;
   wire [4:0]        wRA0 = (gpha) ? ich_dat[20:16] : 5'd0;
   wire [4:0]        wRB0 = (gpha) ? ich_dat[15:11] : 5'd0;
 
   wire [4:0]        wRD1 = (!gpha) ? ich_dat[25:21] : 5'd0;
   wire [4:0]        wRA1 = (!gpha) ? ich_dat[20:16] : 5'd0;
   wire [4:0]        wRB1 = (!gpha) ? ich_dat[15:11] : 5'd0;
 
   wire [4:0]        wRW  = rd_mx;
 
   wire             wWR0 = (!gpha & dena & wrb_fb) | grst;
   wire             wWR1 = (gpha & dena & wrb_fb) | grst;
 
   wire             wWA0 = wWR0;
   wire             wWB0 = wWR0;
   wire             wWD0 = wWR0;
   wire             wWA1 = wWR1;
   wire             wWB1 = wWR1;
   wire             wWD1 = wWR1;
 
   wire [31:0]       wDA0,
                    wDA1,
                    wDB0,
                    wDB1,
                    wDD0,
                    wDD1;
 
   assign           opa_if = wDA0 | wDA1;
   assign           opb_if = wDB0 | wDB1;
   assign           opd_if = wDD0 | wDD1;
 
   /* aeMB2_dparam AUTO_TEMPLATE "_\([a-z,0-9]+\)" (
    .AW(6'd5),
    .DW(6'd32),
 
    .clk_i(gclk),
    .ena_i(dena),
 
    .dat_i(regd),
    .adr_i(wRW[4:0]),
    .wre_i(wW@),
    .dat_o(),
 
    .xwre_i(),
    .xdat_i(),
    .xadr_i(wR@[4:0]),
    .xdat_o(wD@[31:0]),
    ) */
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd5),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_A0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDA0[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW[4:0]),               // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWA0),                  // Templated
      .xadr_i                           (wRA0[4:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd5),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_B0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDB0[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW[4:0]),               // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWB0),                  // Templated
      .xadr_i                           (wRB0[4:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd5),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_D0
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDD0[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW[4:0]),               // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWD0),                  // Templated
      .xadr_i                           (wRD0[4:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd5),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_A1
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDA1[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW[4:0]),               // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWA1),                  // Templated
      .xadr_i                           (wRA1[4:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd5),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_B1
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDB1[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW[4:0]),               // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWB1),                  // Templated
      .xadr_i                           (wRB1[4:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
 
   aeMB2_dparam
     #(/*AUTOINSTPARAM*/
       // Parameters
       .AW                              (6'd5),                  // Templated
       .DW                              (6'd32))                 // Templated
   bank_D1
     (/*AUTOINST*/
      // Outputs
      .dat_o                            (),                      // Templated
      .xdat_o                           (wDD1[31:0]),             // Templated
      // Inputs
      .adr_i                            (wRW[4:0]),               // Templated
      .dat_i                            (regd),                  // Templated
      .wre_i                            (wWD1),                  // Templated
      .xadr_i                           (wRD1[4:0]),              // Templated
      .xdat_i                           (),                      // Templated
      .xwre_i                           (),                      // Templated
      .clk_i                            (gclk),                  // Templated
      .ena_i                            (dena));                         // Templated
`endif

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [aeMB/] [verilog/] [src/] [aeMB2_gprf.v] - Blame information for rev 16

Line No.	Rev	Author	Line
1	16	alirezamon	`/* $Id: aeMB2_gprf.v,v 1.4 2008-04-26 17:57:43 sybreon Exp $`
2			`**`
3			`** AEMB2 EDK 6.2 COMPATIBLE CORE`
4			`** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@aeste.net>`
5			`**`
6			`** This file is part of AEMB.`
7			`**`
8			`** AEMB is free software: you can redistribute it and/or modify it`
9			`** under the terms of the GNU Lesser General Public License as`
10			`** published by the Free Software Foundation, either version 3 of the`
11			`** License, or (at your option) any later version.`
12			`**`
13			`** AEMB is distributed in the hope that it will be useful, but WITHOUT`
14			`** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY`
15			`** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General`
16			`** Public License for more details.`
17			`**`
18			`** You should have received a copy of the GNU Lesser General Public`
19			` License along with AEMB. If not, see <http:www.gnu.org/licenses/>.`
20			`*/`
21			`/**`
22			`* General Purpose Register File`
23			`* @aeMB2_gprf.v`
24
25			`* Dual set of 32 general purpose registers for the core. These are`
26			`R0-R31. A zero is written to R0 for both sets during reset and`
27			`maintained after that.`
28
29			`*/`
30			`timescale 1ns/1ps
31			`module aeMB2_gprf (/AUTOARG/`
32			`// Outputs`
33			`opa_if, opb_if, opd_if,`
34			`// Inputs`
35			`mux_of, mux_ex, ich_dat, rd_of, rd_ex, sel_mx, rpc_mx, xwb_mx,`
36			`dwb_mx, alu_mx, sfr_mx, mul_mx, bsf_mx, gclk, grst, dena, gpha`
37			`);`
38			`parameter AEMB_HTX = 1;`
39
40			`// INTERNAL`
41			`output [31:0] opa_if,`
42			`opb_if,`
43			`opd_if;`
44
45			`input [2:0] mux_of,`
46			`mux_ex;`
47			`input [31:0] ich_dat;`
48			`input [4:0] rd_of,`
49			`rd_ex;`
50
51			`// DATA SOURCSE`
52			`input [3:0] sel_mx;`
53			`input [31:2] rpc_mx;`
54			`input [31:0] xwb_mx,`
55			`dwb_mx,`
56			`alu_mx,`
57			`sfr_mx,`
58			`mul_mx,`
59			`bsf_mx;`
60
61			`// SYSTEM`
62			`input gclk,`
63			`grst,`
64			`dena,`
65			`gpha;`
66
67			`/AUTOWIRE/`
68			`/AUTOREG/`
69
70			`wire [31:0] opd_wr;`
71			`reg [31:0] rMEMA[63:0],`
72			`rMEMB[63:0],`
73			`rMEMD[63:0];`
74			`reg [31:0] mem_mx;`
75			`reg [31:0] regd;`
76			`reg wrb_fb;`
77			`reg [4:0] rd_mx;`
78			`reg [2:0] mux_mx;`
79
80			`// PIPELINE`
81			`always @(posedge gclk)`
82			`if (grst) begin`
83			`/AUTORESET/`
84			`// Beginning of autoreset for uninitialized flops`
85			`mux_mx <= 3'h0;`
86			`rd_mx <= 5'h0;`
87			`wrb_fb <= 1'h0;`
88			`// End of automatics`
89			`end else if (dena) begin`
90			`wrb_fb <= #1 \|rd_ex & \|mux_ex; // FIXME: check mux`
91
92			`rd_mx <= #1 rd_ex;`
93			`mux_mx <= #1 mux_ex;`
94			`end`
95
96			`// LOAD SIZER`
97			`always @(/AUTOSENSE/dwb_mx or sel_mx or xwb_mx) begin`
98			`case (sel_mx)`
99			`// 8'bits`
100			`4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};`
101			`4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};`
102			`4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};`
103			`4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};`
104			`// 16'bits`
105			`4'hC: mem_mx <= #1 {16'd0, dwb_mx[31:16]};`
106			`4'h3: mem_mx <= #1 {16'd0, dwb_mx[15:0]};`
107			`// 32'bits`
108			`4'hF: mem_mx <= #1 dwb_mx;`
109			`// XSL bus`
110			`4'h0: mem_mx <= #1 xwb_mx;`
111			`default: mem_mx <= 32'hX;`
112			`endcase // case (sel_mx)`
113			`end // always @ (...`
114
115			`// SELECT SOURCE`
116			`localparam [2:0] MUX_SFR = 3'o7,`
117			`MUX_BSF = 3'o6,`
118			`MUX_MUL = 3'o5,`
119			`MUX_MEM = 3'o4,`
120
121			`MUX_RPC = 3'o2,`
122			`MUX_ALU = 3'o1,`
123			`MUX_NOP = 3'o0;`
124
125			`always @(/AUTOSENSE/alu_mx or bsf_mx or mem_mx or mul_mx`
126			`or mux_mx or rpc_mx or sfr_mx)`
127			`case (mux_mx)`
128			`MUX_ALU: regd <= #1 alu_mx; // ALU`
129			`MUX_RPC: regd <= #1 {rpc_mx[31:2], 2'o0}; // PC Link`
130			`MUX_MEM: regd <= #1 mem_mx; // RAM/FSL`
131			`MUX_MUL: regd <= #1 mul_mx; // MULTIPLIER`
132			`MUX_BSF: regd <= #1 bsf_mx; // SHIFTER`
133			`MUX_NOP: regd <= #1 32'h0;`
134			`MUX_SFR: regd <= #1 sfr_mx;`
135			`default: regd <= #1 32'hX;`
136			`endcase // case (mux_mx)`
137
138			`// REGISTER FILE - Infer LUT memory`
139			`wire [5:0] wRD0 = {gpha, ich_dat[25:21]};`
140			`wire [5:0] wRA0 = {gpha, ich_dat[20:16]};`
141			`wire [5:0] wRB0 = {gpha, ich_dat[15:11]};`
142			`wire [5:0] wRW0 = {!gpha, rd_mx};`
143			`wire wWRE = grst \| wrb_fb;`
144
145			`wire [31:0] wDA0,`
146			`wDB0,`
147			`wDD0;`
148
149			`assign opa_if = wDA0;`
150			`assign opb_if = wDB0;`
151			`assign opd_if = wDD0;`
152
153			`/* aeMB2_dparam AUTO_TEMPLATE "_\([a-z,0-9]+\)" (`
154			`.AW(6'd6),`
155			`.DW(6'd32),`
156
157			`.clk_i(gclk),`
158			`.ena_i(dena),`
159
160			`.dat_i(regd),`
161			`.adr_i(wRW0[5:0]),`
162			`.wre_i(wWRE),`
163			`.dat_o(),`
164
165			`.xwre_i(),`
166			`.xdat_i(),`
167			`.xadr_i(wR@[5:0]),`
168			`.xdat_o(wD@[31:0]),`
169			`) */`
170
171			`aeMB2_dparam`
172			`#(/AUTOINSTPARAM/`
173			`// Parameters`
174			`.AW (6'd6), // Templated`
175			`.DW (6'd32)) // Templated`
176			`bank_A0`
177			`(/AUTOINST/`
178			`// Outputs`
179			`.dat_o (), // Templated`
180			`.xdat_o (wDA0[31:0]), // Templated`
181			`// Inputs`
182			`.adr_i (wRW0[5:0]), // Templated`
183			`.dat_i (regd), // Templated`
184			`.wre_i (wWRE), // Templated`
185			`.xadr_i (wRA0[5:0]), // Templated`
186			`.xdat_i (), // Templated`
187			`.xwre_i (), // Templated`
188			`.clk_i (gclk), // Templated`
189			`.ena_i (dena)); // Templated`
190
191			`aeMB2_dparam`
192			`#(/AUTOINSTPARAM/`
193			`// Parameters`
194			`.AW (6'd6), // Templated`
195			`.DW (6'd32)) // Templated`
196			`bank_B0`
197			`(/AUTOINST/`
198			`// Outputs`
199			`.dat_o (), // Templated`
200			`.xdat_o (wDB0[31:0]), // Templated`
201			`// Inputs`
202			`.adr_i (wRW0[5:0]), // Templated`
203			`.dat_i (regd), // Templated`
204			`.wre_i (wWRE), // Templated`
205			`.xadr_i (wRB0[5:0]), // Templated`
206			`.xdat_i (), // Templated`
207			`.xwre_i (), // Templated`
208			`.clk_i (gclk), // Templated`
209			`.ena_i (dena)); // Templated`
210
211			`aeMB2_dparam`
212			`#(/AUTOINSTPARAM/`
213			`// Parameters`
214			`.AW (6'd6), // Templated`
215			`.DW (6'd32)) // Templated`
216			`bank_D0`
217			`(/AUTOINST/`
218			`// Outputs`
219			`.dat_o (), // Templated`
220			`.xdat_o (wDD0[31:0]), // Templated`
221			`// Inputs`
222			`.adr_i (wRW0[5:0]), // Templated`
223			`.dat_i (regd), // Templated`
224			`.wre_i (wWRE), // Templated`
225			`.xadr_i (wRD0[5:0]), // Templated`
226			`.xdat_i (), // Templated`
227			`.xwre_i (), // Templated`
228			`.clk_i (gclk), // Templated`
229			`.ena_i (dena)); // Templated`
230
231			`endmodule // aeMB2_gprf`
232
233			`/*`
234			$Log: not supported by cvs2svn $
235			`Revision 1.3 2008/04/26 01:09:06 sybreon`
236			`Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.`
237
238			`Revision 1.2 2008/04/20 16:34:32 sybreon`
239			`Basic version with some features left out.`
240
241			`Revision 1.1 2008/04/18 00:21:52 sybreon`
242			`Initial import.`
243			`*/`
244
245			`ifdef XXX
246
247			`wire [4:0] wRD0 = (gpha) ? ich_dat[25:21] : 5'd0;`
248			`wire [4:0] wRA0 = (gpha) ? ich_dat[20:16] : 5'd0;`
249			`wire [4:0] wRB0 = (gpha) ? ich_dat[15:11] : 5'd0;`
250
251			`wire [4:0] wRD1 = (!gpha) ? ich_dat[25:21] : 5'd0;`
252			`wire [4:0] wRA1 = (!gpha) ? ich_dat[20:16] : 5'd0;`
253			`wire [4:0] wRB1 = (!gpha) ? ich_dat[15:11] : 5'd0;`
254
255			`wire [4:0] wRW = rd_mx;`
256
257			`wire wWR0 = (!gpha & dena & wrb_fb) \| grst;`
258			`wire wWR1 = (gpha & dena & wrb_fb) \| grst;`
259
260			`wire wWA0 = wWR0;`
261			`wire wWB0 = wWR0;`
262			`wire wWD0 = wWR0;`
263			`wire wWA1 = wWR1;`
264			`wire wWB1 = wWR1;`
265			`wire wWD1 = wWR1;`
266
267			`wire [31:0] wDA0,`
268			`wDA1,`
269			`wDB0,`
270			`wDB1,`
271			`wDD0,`
272			`wDD1;`
273
274			`assign opa_if = wDA0 \| wDA1;`
275			`assign opb_if = wDB0 \| wDB1;`
276			`assign opd_if = wDD0 \| wDD1;`
277
278			`/* aeMB2_dparam AUTO_TEMPLATE "_\([a-z,0-9]+\)" (`
279			`.AW(6'd5),`
280			`.DW(6'd32),`
281
282			`.clk_i(gclk),`
283			`.ena_i(dena),`
284
285			`.dat_i(regd),`
286			`.adr_i(wRW[4:0]),`
287			`.wre_i(wW@),`
288			`.dat_o(),`
289
290			`.xwre_i(),`
291			`.xdat_i(),`
292			`.xadr_i(wR@[4:0]),`
293			`.xdat_o(wD@[31:0]),`
294			`) */`
295
296			`aeMB2_dparam`
297			`#(/AUTOINSTPARAM/`
298			`// Parameters`
299			`.AW (6'd5), // Templated`
300			`.DW (6'd32)) // Templated`
301			`bank_A0`
302			`(/AUTOINST/`
303			`// Outputs`
304			`.dat_o (), // Templated`
305			`.xdat_o (wDA0[31:0]), // Templated`
306			`// Inputs`
307			`.adr_i (wRW[4:0]), // Templated`
308			`.dat_i (regd), // Templated`
309			`.wre_i (wWA0), // Templated`
310			`.xadr_i (wRA0[4:0]), // Templated`
311			`.xdat_i (), // Templated`
312			`.xwre_i (), // Templated`
313			`.clk_i (gclk), // Templated`
314			`.ena_i (dena)); // Templated`
315
316			`aeMB2_dparam`
317			`#(/AUTOINSTPARAM/`
318			`// Parameters`
319			`.AW (6'd5), // Templated`
320			`.DW (6'd32)) // Templated`
321			`bank_B0`
322			`(/AUTOINST/`
323			`// Outputs`
324			`.dat_o (), // Templated`
325			`.xdat_o (wDB0[31:0]), // Templated`
326			`// Inputs`
327			`.adr_i (wRW[4:0]), // Templated`
328			`.dat_i (regd), // Templated`
329			`.wre_i (wWB0), // Templated`
330			`.xadr_i (wRB0[4:0]), // Templated`
331			`.xdat_i (), // Templated`
332			`.xwre_i (), // Templated`
333			`.clk_i (gclk), // Templated`
334			`.ena_i (dena)); // Templated`
335
336			`aeMB2_dparam`
337			`#(/AUTOINSTPARAM/`
338			`// Parameters`
339			`.AW (6'd5), // Templated`
340			`.DW (6'd32)) // Templated`
341			`bank_D0`
342			`(/AUTOINST/`
343			`// Outputs`
344			`.dat_o (), // Templated`
345			`.xdat_o (wDD0[31:0]), // Templated`
346			`// Inputs`
347			`.adr_i (wRW[4:0]), // Templated`
348			`.dat_i (regd), // Templated`
349			`.wre_i (wWD0), // Templated`
350			`.xadr_i (wRD0[4:0]), // Templated`
351			`.xdat_i (), // Templated`
352			`.xwre_i (), // Templated`
353			`.clk_i (gclk), // Templated`
354			`.ena_i (dena)); // Templated`
355
356			`aeMB2_dparam`
357			`#(/AUTOINSTPARAM/`
358			`// Parameters`
359			`.AW (6'd5), // Templated`
360			`.DW (6'd32)) // Templated`
361			`bank_A1`
362			`(/AUTOINST/`
363			`// Outputs`
364			`.dat_o (), // Templated`
365			`.xdat_o (wDA1[31:0]), // Templated`
366			`// Inputs`
367			`.adr_i (wRW[4:0]), // Templated`
368			`.dat_i (regd), // Templated`
369			`.wre_i (wWA1), // Templated`
370			`.xadr_i (wRA1[4:0]), // Templated`
371			`.xdat_i (), // Templated`
372			`.xwre_i (), // Templated`
373			`.clk_i (gclk), // Templated`
374			`.ena_i (dena)); // Templated`
375
376			`aeMB2_dparam`
377			`#(/AUTOINSTPARAM/`
378			`// Parameters`
379			`.AW (6'd5), // Templated`
380			`.DW (6'd32)) // Templated`
381			`bank_B1`
382			`(/AUTOINST/`
383			`// Outputs`
384			`.dat_o (), // Templated`
385			`.xdat_o (wDB1[31:0]), // Templated`
386			`// Inputs`
387			`.adr_i (wRW[4:0]), // Templated`
388			`.dat_i (regd), // Templated`
389			`.wre_i (wWB1), // Templated`
390			`.xadr_i (wRB1[4:0]), // Templated`
391			`.xdat_i (), // Templated`
392			`.xwre_i (), // Templated`
393			`.clk_i (gclk), // Templated`
394			`.ena_i (dena)); // Templated`
395
396			`aeMB2_dparam`
397			`#(/AUTOINSTPARAM/`
398			`// Parameters`
399			`.AW (6'd5), // Templated`
400			`.DW (6'd32)) // Templated`
401			`bank_D1`
402			`(/AUTOINST/`
403			`// Outputs`
404			`.dat_o (), // Templated`
405			`.xdat_o (wDD1[31:0]), // Templated`
406			`// Inputs`
407			`.adr_i (wRW[4:0]), // Templated`
408			`.dat_i (regd), // Templated`
409			`.wre_i (wWD1), // Templated`
410			`.xadr_i (wRD1[4:0]), // Templated`
411			`.xdat_i (), // Templated`
412			`.xwre_i (), // Templated`
413			`.clk_i (gclk), // Templated`
414			`.ena_i (dena)); // Templated`
415			`endif