URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [sw/] [linkvar.ld] - Blame information for rev 48

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MEMORY
{
        rom (rx)    : ORIGIN = 0x0 , LENGTH = 0xc000  /* 48 K B- Rom space  */
        ram (wrx)   : ORIGIN = 0xc000 , LENGTH = 0x4000  /* 16 K B- Rom space  */
}
 
 

Line No.	Rev	Author	Line
1	48	alirezamon
2
3
4			`MEMORY`
5			`{`
6			`rom (rx) : ORIGIN = 0x0 , LENGTH = 0xc000 /* 48 K B- Rom space */`
7			`ram (wrx) : ORIGIN = 0xc000 , LENGTH = 0x4000 /* 16 K B- Rom space */`
8			`}`
9
10

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [sw/] [linkvar.ld] - Blame information for rev 48