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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [sw/] [lm32/] [crt0ram.S] - Blame information for rev 48

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/*
 * LatticeMico32 C startup code.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */
 
/* Exception handlers - Must be 32 bytes long. */
        .section    .text, "ax", @progbits
        .global     _start
        .global     irq_enable, irq_disable, irq_set_mask, irq_get_mask
        .global     jump, halt
        .global     get_sp, get_gp
 
_start:
_reset_handler:
        bi      _crt0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_breakpoint_handler:
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_ibuserror_handler:
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_watchpoint_handler:
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_dbuserror_handler:
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_divzero_handler:
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_interrupt_handler:
        sw      (sp+0), ra
        calli   _save_all
        rcsr    r1, IP
        calli   irq_handler
        mvhi    r1, 0xffff
        ori     r1, r1, 0xffff
        wcsr    IP, r1
        bi      _restore_all_and_eret
 
_scall_handler:
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
 
_crt0:
        /* Clear r0 */
        xor     r0, r0, r0
 
        /* Clear all other regs (needed so that simulations match) */
        mvi     r1, 0
        mvi     r2, 0
        mvi     r3, 0
        mvi     r4, 0
        mvi     r5, 0
        mvi     r6, 0
        mvi     r7, 0
        mvi     r8, 0
        mvi     r9, 0
        mvi     r10, 0
        mvi     r11, 0
        mvi     r12, 0
        mvi     r13, 0
        mvi     r14, 0
        mvi     r15, 0
        mvi     r16, 0
        mvi     r17, 0
        mvi     r18, 0
        mvi     r19, 0
        mvi     r20, 0
        mvi     r21, 0
        mvi     r22, 0
        mvi     r23, 0
        mvi     r24, 0
        mvi     r25, 0
        mvi     r26, 0
        mvi     r27, 0
        mvi     r28, 0
        mvi     r29, 0
        mvi     r30, 0
        mvi     r31, 0
 
        /* Setup stack and global pointer */
        mvhi    sp, hi(_fstack)
        ori     sp, sp, lo(_fstack)
        mvhi    gp, hi(_gp)
        ori     gp, gp, lo(_gp)
 
        /* Clear BSS */
        mvhi    r1, hi(_fbss)
        ori     r1, r1, lo(_fbss)
        mvhi    r3, hi(_ebss)
        ori     r3, r3, lo(_ebss)
.clearBSS:
        be      r1, r3, .callMain
        sw      (r1+0), r0
        addi    r1, r1, 4
        bi      .clearBSS
 
 
.callMain:
        mvi     r1, 0
        mvi     r2, 0
        mvi     r3, 0
        /*initial_global_data then run main*/
        calli   __main
 
irq_enable:
        mvi     r1, 1
        wcsr    IE, r1
        ret
 
irq_disable:
        mvi     r1, 0
        wcsr    IE, r1
        ret
 
irq_set_mask:
        wcsr    IM, r1
        ret
 
irq_get_mask:
        rcsr    r1, IM
        ret
 
jump:
        b       r1
 
halt:
        bi halt
 
        /* Save all registers onto the stack */
_save_all:
        addi    sp, sp, -128
        sw      (sp+4), r1
        sw      (sp+8), r2
        sw      (sp+12), r3
        sw      (sp+16), r4
        sw      (sp+20), r5
        sw      (sp+24), r6
        sw      (sp+28), r7
        sw      (sp+32), r8
        sw      (sp+36), r9
        sw      (sp+40), r10
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
        sw      (sp+44), r11
        sw      (sp+48), r12
        sw      (sp+52), r13
        sw      (sp+56), r14
        sw      (sp+60), r15
        sw      (sp+64), r16
        sw      (sp+68), r17
        sw      (sp+72), r18
        sw      (sp+76), r19
        sw      (sp+80), r20
        sw      (sp+84), r21
        sw      (sp+88), r22
        sw      (sp+92), r23
        sw      (sp+96), r24
        sw      (sp+100), r25
        sw      (sp+104), r26
        sw      (sp+108), r27
#endif
        sw      (sp+120), ea
        sw      (sp+124), ba
        /* ra and sp need special handling, as they have been modified */
        lw      r1, (sp+128)
        sw      (sp+116), r1
        mv      r1, sp
        addi    r1, r1, 128
        sw      (sp+112), r1
        ret
 
        /* Restore all registers and return from exception */
_restore_all_and_eret:
        lw      r1, (sp+4)
        lw      r2, (sp+8)
        lw      r3, (sp+12)
        lw      r4, (sp+16)
        lw      r5, (sp+20)
        lw      r6, (sp+24)
        lw      r7, (sp+28)
        lw      r8, (sp+32)
        lw      r9, (sp+36)
        lw      r10, (sp+40)
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
        lw      r11, (sp+44)
        lw      r12, (sp+48)
        lw      r13, (sp+52)
        lw      r14, (sp+56)
        lw      r15, (sp+60)
        lw      r16, (sp+64)
        lw      r17, (sp+68)
        lw      r18, (sp+72)
        lw      r19, (sp+76)
        lw      r20, (sp+80)
        lw      r21, (sp+84)
        lw      r22, (sp+88)
        lw      r23, (sp+92)
        lw      r24, (sp+96)
        lw      r25, (sp+100)
        lw      r26, (sp+104)
        lw      r27, (sp+108)
#endif
        lw      ra, (sp+116)
        lw      ea, (sp+120)
        lw      ba, (sp+124)
        /* Stack pointer must be restored last, in case it has been updated */
        lw      sp, (sp+112)
        eret
 
get_sp:
        mv      r1, sp
        ret
 
get_gp:
        mv      r1, gp
        ret
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [sw/] [lm32/] [crt0ram.S] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`/*`
2			`* LatticeMico32 C startup code.`
3			`*`
4			`* Redistribution and use in source and binary forms, with or without`
5			`* modification, are permitted provided that the following conditions`
6			`* are met:`
7			`* 1. Redistributions of source code must retain the above copyright`
8			`* notice, this list of conditions and the following disclaimer.`
9			`* 2. Redistributions in binary form must reproduce the above copyright`
10			`* notice, this list of conditions and the following disclaimer in the`
11			`* documentation and/or other materials provided with the distribution.`
12			`*`
13			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14			`* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
15			`* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE`
16			`* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE`
17			`* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
18			`* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
19			`* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
20			`* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT`
21			`* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY`
22			`* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF`
23			`* SUCH DAMAGE.`
24			`*/`
25
26			`/* Exception handlers - Must be 32 bytes long. */`
27			`.section .text, "ax", @progbits`
28			`.global _start`
29			`.global irq_enable, irq_disable, irq_set_mask, irq_get_mask`
30			`.global jump, halt`
31			`.global get_sp, get_gp`
32
33			`_start:`
34			`_reset_handler:`
35			`bi _crt0`
36			`nop`
37			`nop`
38			`nop`
39			`nop`
40			`nop`
41			`nop`
42			`nop`
43
44			`_breakpoint_handler:`
45			`nop`
46			`nop`
47			`nop`
48			`nop`
49			`nop`
50			`nop`
51			`nop`
52			`nop`
53
54			`_ibuserror_handler:`
55			`nop`
56			`nop`
57			`nop`
58			`nop`
59			`nop`
60			`nop`
61			`nop`
62			`nop`
63
64			`_watchpoint_handler:`
65			`nop`
66			`nop`
67			`nop`
68			`nop`
69			`nop`
70			`nop`
71			`nop`
72			`nop`
73
74			`_dbuserror_handler:`
75			`nop`
76			`nop`
77			`nop`
78			`nop`
79			`nop`
80			`nop`
81			`nop`
82			`nop`
83
84			`_divzero_handler:`
85			`nop`
86			`nop`
87			`nop`
88			`nop`
89			`nop`
90			`nop`
91			`nop`
92			`nop`
93
94			`_interrupt_handler:`
95			`sw (sp+0), ra`
96			`calli _save_all`
97			`rcsr r1, IP`
98			`calli irq_handler`
99			`mvhi r1, 0xffff`
100			`ori r1, r1, 0xffff`
101			`wcsr IP, r1`
102			`bi _restore_all_and_eret`
103
104			`_scall_handler:`
105			`nop`
106			`nop`
107			`nop`
108			`nop`
109			`nop`
110			`nop`
111			`nop`
112			`nop`
113
114			`_crt0:`
115			`/* Clear r0 */`
116			`xor r0, r0, r0`
117
118			`/* Clear all other regs (needed so that simulations match) */`
119			`mvi r1, 0`
120			`mvi r2, 0`
121			`mvi r3, 0`
122			`mvi r4, 0`
123			`mvi r5, 0`
124			`mvi r6, 0`
125			`mvi r7, 0`
126			`mvi r8, 0`
127			`mvi r9, 0`
128			`mvi r10, 0`
129			`mvi r11, 0`
130			`mvi r12, 0`
131			`mvi r13, 0`
132			`mvi r14, 0`
133			`mvi r15, 0`
134			`mvi r16, 0`
135			`mvi r17, 0`
136			`mvi r18, 0`
137			`mvi r19, 0`
138			`mvi r20, 0`
139			`mvi r21, 0`
140			`mvi r22, 0`
141			`mvi r23, 0`
142			`mvi r24, 0`
143			`mvi r25, 0`
144			`mvi r26, 0`
145			`mvi r27, 0`
146			`mvi r28, 0`
147			`mvi r29, 0`
148			`mvi r30, 0`
149			`mvi r31, 0`
150
151			`/* Setup stack and global pointer */`
152			`mvhi sp, hi(_fstack)`
153			`ori sp, sp, lo(_fstack)`
154			`mvhi gp, hi(_gp)`
155			`ori gp, gp, lo(_gp)`
156
157			`/* Clear BSS */`
158			`mvhi r1, hi(_fbss)`
159			`ori r1, r1, lo(_fbss)`
160			`mvhi r3, hi(_ebss)`
161			`ori r3, r3, lo(_ebss)`
162			`.clearBSS:`
163			`be r1, r3, .callMain`
164			`sw (r1+0), r0`
165			`addi r1, r1, 4`
166			`bi .clearBSS`
167
168
169			`.callMain:`
170			`mvi r1, 0`
171			`mvi r2, 0`
172			`mvi r3, 0`
173			`/initial_global_data then run main/`
174			`calli __main`
175
176			`irq_enable:`
177			`mvi r1, 1`
178			`wcsr IE, r1`
179			`ret`
180
181			`irq_disable:`
182			`mvi r1, 0`
183			`wcsr IE, r1`
184			`ret`
185
186			`irq_set_mask:`
187			`wcsr IM, r1`
188			`ret`
189
190			`irq_get_mask:`
191			`rcsr r1, IM`
192			`ret`
193
194			`jump:`
195			`b r1`
196
197			`halt:`
198			`bi halt`
199
200			`/* Save all registers onto the stack */`
201			`_save_all:`
202			`addi sp, sp, -128`
203			`sw (sp+4), r1`
204			`sw (sp+8), r2`
205			`sw (sp+12), r3`
206			`sw (sp+16), r4`
207			`sw (sp+20), r5`
208			`sw (sp+24), r6`
209			`sw (sp+28), r7`
210			`sw (sp+32), r8`
211			`sw (sp+36), r9`
212			`sw (sp+40), r10`
213			`#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE`
214			`sw (sp+44), r11`
215			`sw (sp+48), r12`
216			`sw (sp+52), r13`
217			`sw (sp+56), r14`
218			`sw (sp+60), r15`
219			`sw (sp+64), r16`
220			`sw (sp+68), r17`
221			`sw (sp+72), r18`
222			`sw (sp+76), r19`
223			`sw (sp+80), r20`
224			`sw (sp+84), r21`
225			`sw (sp+88), r22`
226			`sw (sp+92), r23`
227			`sw (sp+96), r24`
228			`sw (sp+100), r25`
229			`sw (sp+104), r26`
230			`sw (sp+108), r27`
231			`#endif`
232			`sw (sp+120), ea`
233			`sw (sp+124), ba`
234			`/* ra and sp need special handling, as they have been modified */`
235			`lw r1, (sp+128)`
236			`sw (sp+116), r1`
237			`mv r1, sp`
238			`addi r1, r1, 128`
239			`sw (sp+112), r1`
240			`ret`
241
242			`/* Restore all registers and return from exception */`
243			`_restore_all_and_eret:`
244			`lw r1, (sp+4)`
245			`lw r2, (sp+8)`
246			`lw r3, (sp+12)`
247			`lw r4, (sp+16)`
248			`lw r5, (sp+20)`
249			`lw r6, (sp+24)`
250			`lw r7, (sp+28)`
251			`lw r8, (sp+32)`
252			`lw r9, (sp+36)`
253			`lw r10, (sp+40)`
254			`#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE`
255			`lw r11, (sp+44)`
256			`lw r12, (sp+48)`
257			`lw r13, (sp+52)`
258			`lw r14, (sp+56)`
259			`lw r15, (sp+60)`
260			`lw r16, (sp+64)`
261			`lw r17, (sp+68)`
262			`lw r18, (sp+72)`
263			`lw r19, (sp+76)`
264			`lw r20, (sp+80)`
265			`lw r21, (sp+84)`
266			`lw r22, (sp+88)`
267			`lw r23, (sp+92)`
268			`lw r24, (sp+96)`
269			`lw r25, (sp+100)`
270			`lw r26, (sp+104)`
271			`lw r27, (sp+108)`
272			`#endif`
273			`lw ra, (sp+116)`
274			`lw ea, (sp+120)`
275			`lw ba, (sp+124)`
276			`/* Stack pointer must be restored last, in case it has been updated */`
277			`lw sp, (sp+112)`
278			`eret`
279
280			`get_sp:`
281			`mv r1, sp`
282			`ret`
283
284			`get_gp:`
285			`mv r1, gp`
286			`ret`
287