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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [JTAGB.v] - Blame information for rev 17

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module JTAGB (
         output JTCK,
         output JRTI1,
         output JRTI2,
         output JTDI,
         output JSHIFT,
         output JUPDATE,
         output JRSTN,
         output JCE1,
         output JCE2,
         input JTDO1,
         input JTDO2
      ) /*synthesis syn_black_box */;
 
endmodule

Line No.	Rev	Author	Line
1	17	alirezamon	`module JTAGB (`
2			`output JTCK,`
3			`output JRTI1,`
4			`output JRTI2,`
5			`output JTDI,`
6			`output JSHIFT,`
7			`output JUPDATE,`
8			`output JRSTN,`
9			`output JCE1,`
10			`output JCE2,`
11			`input JTDO1,`
12			`input JTDO2`
13			`) /synthesis syn_black_box /;`
14
15			`endmodule`

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [JTAGB.v] - Blame information for rev 17