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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_cpu.v] - Blame information for rev 17

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1 17 alirezamon 
// =============================================================================
2 
//                           COPYRIGHT NOTICE
3 
// Copyright 2006 (c) Lattice Semiconductor Corporation
4 
// ALL RIGHTS RESERVED
5 
// This confidential and proprietary software may be used only as authorised by
6 
// a licensing agreement from Lattice Semiconductor Corporation.
7 
// The entire notice above must be reproduced on all authorized copies and
8 
// copies may only be made to the extent permitted by a licensing agreement from
9 
// Lattice Semiconductor Corporation.
10 
//
11 
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
12 
// 5555 NE Moore Court                            408-826-6000 (other locations)
13 
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
14 
// U.S.A                                   email: techsupport@latticesemi.com
15 
// =============================================================================/
16 
//                         FILE DETAILS
17 
// Project          : LatticeMico32
18 
// File             : lm32_cpu.v
19 
// Title            : Top-level of CPU.
20 
// Dependencies     : lm32_include.v
21 
// Version          : 6.1.17
22 
// =============================================================================
23 
 
24 
`include "lm32_include.v"
25 
 
26 
/////////////////////////////////////////////////////
27 
// Module interface
28 
/////////////////////////////////////////////////////
29 
 
30 
module lm32_cpu (
31 
    // ----- Inputs -------
32 
    clk_i,
33 
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
34 
    clk_n_i,
35 
`endif
36 
    rst_i,
37 
    // From external devices
38 
`ifdef CFG_INTERRUPTS_ENABLED
39 
    interrupt_n,
40 
`endif
41 
    // From user logic
42 
`ifdef CFG_USER_ENABLED
43 
    user_result,
44 
    user_complete,
45 
`endif
46 
`ifdef CFG_JTAG_ENABLED
47 
    // From JTAG
48 
    jtag_clk,
49 
    jtag_update,
50 
    jtag_reg_q,
51 
    jtag_reg_addr_q,
52 
`endif
53 
`ifdef CFG_IWB_ENABLED
54 
    // Instruction Wishbone master
55 
    I_DAT_I,
56 
    I_ACK_I,
57 
    I_ERR_I,
58 
    I_RTY_I,
59 
`endif
60 
    // Data Wishbone master
61 
    D_DAT_I,
62 
    D_ACK_I,
63 
    D_ERR_I,
64 
    D_RTY_I,
65 
    // ----- Outputs -------
66 
`ifdef CFG_TRACE_ENABLED
67 
    trace_pc,
68 
    trace_pc_valid,
69 
    trace_exception,
70 
    trace_eid,
71 
    trace_eret,
72 
`ifdef CFG_DEBUG_ENABLED
73 
    trace_bret,
74 
`endif
75 
`endif
76 
`ifdef CFG_JTAG_ENABLED
77 
    jtag_reg_d,
78 
    jtag_reg_addr_d,
79 
`endif
80 
`ifdef CFG_USER_ENABLED
81 
    user_valid,
82 
    user_opcode,
83 
    user_operand_0,
84 
    user_operand_1,
85 
`endif
86 
`ifdef CFG_IWB_ENABLED
87 
    // Instruction Wishbone master
88 
    I_DAT_O,
89 
    I_ADR_O,
90 
    I_CYC_O,
91 
    I_SEL_O,
92 
    I_STB_O,
93 
    I_WE_O,
94 
    I_CTI_O,
95 
    I_LOCK_O,
96 
    I_BTE_O,
97 
`endif
98 
    // Data Wishbone master
99 
    D_DAT_O,
100 
    D_ADR_O,
101 
    D_CYC_O,
102 
    D_SEL_O,
103 
    D_STB_O,
104 
    D_WE_O,
105 
    D_CTI_O,
106 
    D_LOCK_O,
107 
    D_BTE_O
108 
    );
109 
 
110 
/////////////////////////////////////////////////////
111 
// Parameters
112 
/////////////////////////////////////////////////////
113 
 
114 
parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
115 
`ifdef CFG_DEBUG_ENABLED
116 
parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
117 
`endif
118 
 
119 
`ifdef CFG_ICACHE_ENABLED
120 
parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
121 
parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
122 
parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
123 
parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
124 
parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
125 
`else
126 
parameter icache_associativity = 1;
127 
parameter icache_sets = 512;
128 
parameter icache_bytes_per_line = 16;
129 
parameter icache_base_address = 0;
130 
parameter icache_limit = 0;
131 
`endif
132 
 
133 
`ifdef CFG_DCACHE_ENABLED
134 
parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
135 
parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
136 
parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
137 
parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
138 
parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
139 
`else
140 
parameter dcache_associativity = 1;
141 
parameter dcache_sets = 512;
142 
parameter dcache_bytes_per_line = 16;
143 
parameter dcache_base_address = 0;
144 
parameter dcache_limit = 0;
145 
`endif
146 
 
147 
`ifdef CFG_DEBUG_ENABLED
148 
parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
149 
`else
150 
parameter watchpoints = 4'h0;
151 
`endif
152 
`ifdef CFG_ROM_DEBUG_ENABLED
153 
parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
154 
`else
155 
parameter breakpoints = 4'h0;
156 
`endif
157 
 
158 
`ifdef CFG_INTERRUPTS_ENABLED
159 
parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
160 
`else
161 
parameter interrupts = 0;
162 
`endif
163 
 
164 
/////////////////////////////////////////////////////
165 
// Inputs
166 
/////////////////////////////////////////////////////
167 
 
168 
input clk_i;                                    // Clock
169 
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
170 
input clk_n_i;                                  // Inverted clock
171 
`endif
172 
input rst_i;                                    // Reset
173 
 
174 
`ifdef CFG_INTERRUPTS_ENABLED
175 
input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
176 
`endif
177 
 
178 
`ifdef CFG_USER_ENABLED
179 
input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
180 
input user_complete;                            // User-defined instruction execution is complete
181 
`endif
182 
 
183 
`ifdef CFG_JTAG_ENABLED
184 
input jtag_clk;                                 // JTAG clock
185 
input jtag_update;                              // JTAG state machine is in data register update state
186 
input [`LM32_BYTE_RNG] jtag_reg_q;
187 
input [2:0] jtag_reg_addr_q;
188 
`endif
189 
 
190 
`ifdef CFG_IWB_ENABLED
191 
input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
192 
input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
193 
input I_ERR_I;                                  // Instruction Wishbone interface error
194 
input I_RTY_I;                                  // Instruction Wishbone interface retry
195 
`endif
196 
 
197 
input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
198 
input D_ACK_I;                                  // Data Wishbone interface acknowledgement
199 
input D_ERR_I;                                  // Data Wishbone interface error
200 
input D_RTY_I;                                  // Data Wishbone interface retry
201 
 
202 
/////////////////////////////////////////////////////
203 
// Outputs
204 
/////////////////////////////////////////////////////
205 
 
206 
`ifdef CFG_TRACE_ENABLED
207 
output [`LM32_PC_RNG] trace_pc;                 // PC to trace
208 
reg    [`LM32_PC_RNG] trace_pc;
209 
output trace_pc_valid;                          // Indicates that a new trace PC is valid
210 
reg    trace_pc_valid;
211 
output trace_exception;                         // Indicates an exception has occured
212 
reg    trace_exception;
213 
output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
214 
reg    [`LM32_EID_RNG] trace_eid;
215 
output trace_eret;                              // Indicates an eret instruction has been executed
216 
reg    trace_eret;
217 
`ifdef CFG_DEBUG_ENABLED
218 
output trace_bret;                              // Indicates a bret instruction has been executed
219 
reg    trace_bret;
220 
`endif
221 
`endif
222 
 
223 
`ifdef CFG_JTAG_ENABLED
224 
output [`LM32_BYTE_RNG] jtag_reg_d;
225 
wire   [`LM32_BYTE_RNG] jtag_reg_d;
226 
output [2:0] jtag_reg_addr_d;
227 
wire   [2:0] jtag_reg_addr_d;
228 
`endif
229 
 
230 
`ifdef CFG_USER_ENABLED
231 
output user_valid;                              // Indicates if user_opcode is valid
232 
wire   user_valid;
233 
output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
234 
reg    [`LM32_USER_OPCODE_RNG] user_opcode;
235 
output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
236 
wire   [`LM32_WORD_RNG] user_operand_0;
237 
output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
238 
wire   [`LM32_WORD_RNG] user_operand_1;
239 
`endif
240 
 
241 
`ifdef CFG_IWB_ENABLED
242 
output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
243 
wire   [`LM32_WORD_RNG] I_DAT_O;
244 
output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
245 
wire   [`LM32_WORD_RNG] I_ADR_O;
246 
output I_CYC_O;                                 // Instruction Wishbone interface cycle
247 
wire   I_CYC_O;
248 
output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
249 
wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
250 
output I_STB_O;                                 // Instruction Wishbone interface strobe
251 
wire   I_STB_O;
252 
output I_WE_O;                                  // Instruction Wishbone interface write enable
253 
wire   I_WE_O;
254 
output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type
255 
wire   [`LM32_CTYPE_RNG] I_CTI_O;
256 
output I_LOCK_O;                                // Instruction Wishbone interface lock bus
257 
wire   I_LOCK_O;
258 
output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type
259 
wire   [`LM32_BTYPE_RNG] I_BTE_O;
260 
`endif
261 
 
262 
output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
263 
wire   [`LM32_WORD_RNG] D_DAT_O;
264 
output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
265 
wire   [`LM32_WORD_RNG] D_ADR_O;
266 
output D_CYC_O;                                 // Data Wishbone interface cycle
267 
wire   D_CYC_O;
268 
output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
269 
wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
270 
output D_STB_O;                                 // Data Wishbone interface strobe
271 
wire   D_STB_O;
272 
output D_WE_O;                                  // Data Wishbone interface write enable
273 
wire   D_WE_O;
274 
output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type
275 
wire   [`LM32_CTYPE_RNG] D_CTI_O;
276 
output D_LOCK_O;                                // Date Wishbone interface lock bus
277 
wire   D_LOCK_O;
278 
output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type
279 
wire   [`LM32_BTYPE_RNG] D_BTE_O;
280 
 
281 
/////////////////////////////////////////////////////
282 
// Internal nets and registers
283 
/////////////////////////////////////////////////////
284 
 
285 
// Pipeline registers
286 
 
287 
`ifdef LM32_CACHE_ENABLED
288 
reg valid_a;                                    // Instruction in A stage is valid
289 
`endif
290 
reg valid_f;                                    // Instruction in F stage is valid
291 
reg valid_d;                                    // Instruction in D stage is valid
292 
reg valid_x;                                    // Instruction in X stage is valid
293 
reg valid_m;                                    // Instruction in M stage is valid
294 
reg valid_w;                                    // Instruction in W stage is valid
295 
 
296 
wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
297 
wire load_d;                                    // Indicates a load instruction
298 
reg load_x;
299 
reg load_m;
300 
wire store_d;                                   // Indicates a store instruction
301 
reg store_x;
302 
reg store_m;
303 
wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
304 
reg [`LM32_SIZE_RNG] size_x;
305 
wire branch_d;                                  // Indicates a branch instruction
306 
reg branch_x;
307 
reg branch_m;
308 
wire branch_reg_d;                              // Branch to register or immediate
309 
wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
310 
reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
311 
reg [`LM32_PC_RNG] branch_target_m;
312 
wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
313 
wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
314 
 
315 
wire x_result_sel_csr_d;                        // Select X stage result from CSRs
316 
reg x_result_sel_csr_x;
317 
`ifdef LM32_MC_ARITHMETIC_ENABLED
318 
wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
319 
reg x_result_sel_mc_arith_x;
320 
`endif
321 
`ifdef LM32_NO_BARREL_SHIFT
322 
wire x_result_sel_shift_d;                      // Select X stage result from shifter
323 
reg x_result_sel_shift_x;
324 
`endif
325 
`ifdef CFG_SIGN_EXTEND_ENABLED
326 
wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
327 
reg x_result_sel_sext_x;
328 
`endif
329 
wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
330 
reg x_result_sel_logic_x;
331 
`ifdef CFG_USER_ENABLED
332 
wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
333 
reg x_result_sel_user_x;
334 
`endif
335 
wire x_result_sel_add_d;                        // Select X stage result from adder
336 
reg x_result_sel_add_x;
337 
wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
338 
reg m_result_sel_compare_x;
339 
reg m_result_sel_compare_m;
340 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
341 
wire m_result_sel_shift_d;                      // Select M stage result from shifter
342 
reg m_result_sel_shift_x;
343 
reg m_result_sel_shift_m;
344 
`endif
345 
wire w_result_sel_load_d;                       // Select W stage result from load/store unit
346 
reg w_result_sel_load_x;
347 
reg w_result_sel_load_m;
348 
reg w_result_sel_load_w;
349 
`ifdef CFG_PL_MULTIPLY_ENABLED
350 
wire w_result_sel_mul_d;                        // Select W stage result from multiplier
351 
reg w_result_sel_mul_x;
352 
reg w_result_sel_mul_m;
353 
reg w_result_sel_mul_w;
354 
`endif
355 
wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
356 
reg x_bypass_enable_x;
357 
wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
358 
reg m_bypass_enable_x;
359 
reg m_bypass_enable_m;
360 
wire sign_extend_d;                             // Whether to sign-extend or zero-extend
361 
reg sign_extend_x;
362 
wire write_enable_d;                            // Register file write enable
363 
reg write_enable_x;
364 
wire write_enable_q_x;
365 
reg write_enable_m;
366 
wire write_enable_q_m;
367 
reg write_enable_w;
368 
wire write_enable_q_w;
369 
wire read_enable_0_d;                           // Register file read enable 0
370 
wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
371 
wire read_enable_1_d;                           // Register file read enable 1
372 
wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
373 
wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
374 
reg [`LM32_REG_IDX_RNG] write_idx_x;
375 
reg [`LM32_REG_IDX_RNG] write_idx_m;
376 
reg [`LM32_REG_IDX_RNG] write_idx_w;
377 
wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
378 
reg  [`LM32_CSR_RNG] csr_x;
379 
wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
380 
reg [`LM32_CONDITION_RNG] condition_x;
381 
`ifdef CFG_DEBUG_ENABLED
382 
wire break_d;                                   // Indicates a break instruction
383 
reg break_x;
384 
`endif
385 
wire scall_d;                                   // Indicates a scall instruction
386 
reg scall_x;
387 
wire eret_d;                                    // Indicates an eret instruction
388 
reg eret_x;
389 
wire eret_q_x;
390 
reg eret_m;
391 
`ifdef CFG_TRACE_ENABLED
392 
reg eret_w;
393 
`endif
394 
`ifdef CFG_DEBUG_ENABLED
395 
wire bret_d;                                    // Indicates a bret instruction
396 
reg bret_x;
397 
wire bret_q_x;
398 
reg bret_m;
399 
`ifdef CFG_TRACE_ENABLED
400 
reg bret_w;
401 
`endif
402 
`endif
403 
wire csr_write_enable_d;                        // CSR write enable
404 
reg csr_write_enable_x;
405 
wire csr_write_enable_q_x;
406 
`ifdef CFG_USER_ENABLED
407 
wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
408 
`endif
409 
 
410 
`ifdef CFG_BUS_ERRORS_ENABLED
411 
wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
412 
reg bus_error_x;
413 
`endif
414 
 
415 
reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
416 
reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
417 
reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
418 
reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
419 
reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
420 
 
421 
reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
422 
reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
423 
reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
424 
reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
425 
reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
426 
 
427 
// To/from register file
428 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
429 
wire [`LM32_WORD_RNG] reg_data_live_0;
430 
wire [`LM32_WORD_RNG] reg_data_live_1;
431 
reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
432 
reg [`LM32_WORD_RNG] reg_data_buf_0;
433 
reg [`LM32_WORD_RNG] reg_data_buf_1;
434 
`endif
435 
`ifdef LM32_EBR_REGISTER_FILE
436 
`else
437 
reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
438 
`endif
439 
wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data
440 
wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
441 
reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
442 
reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
443 
wire reg_write_enable_q_w;
444 
 
445 
reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
446 
 
447 
wire stall_a;                                   // Stall instruction in A pipeline stage
448 
wire stall_f;                                   // Stall instruction in F pipeline stage
449 
wire stall_d;                                   // Stall instruction in D pipeline stage
450 
wire stall_x;                                   // Stall instruction in X pipeline stage
451 
wire stall_m;                                   // Stall instruction in M pipeline stage
452 
 
453 
// To/from adder
454 
wire adder_op_d;                                // Whether to add or subtract
455 
reg adder_op_x;
456 
reg adder_op_x_n;                               // Inverted version of adder_op_x
457 
wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
458 
wire adder_overflow_x;                          // Whether a signed overflow occured
459 
wire adder_carry_n_x;                           // Whether a carry was generated
460 
 
461 
// To/from logical operations unit
462 
wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
463 
reg [`LM32_LOGIC_OP_RNG] logic_op_x;
464 
wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
465 
 
466 
`ifdef CFG_SIGN_EXTEND_ENABLED
467 
// From sign-extension unit
468 
wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
469 
wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
470 
wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
471 
`endif
472 
 
473 
// To/from shifter
474 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
475 
`ifdef CFG_ROTATE_ENABLED
476 
wire rotate_d;                                  // Whether we should rotate or shift
477 
reg rotate_x;
478 
`endif
479 
wire direction_d;                               // Which direction to shift in
480 
reg direction_x;
481 
reg direction_m;
482 
wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
483 
`endif
484 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
485 
wire shift_left_d;                              // Indicates whether to perform a left shift or not
486 
wire shift_left_q_d;
487 
wire shift_right_d;                             // Indicates whether to perform a right shift or not
488 
wire shift_right_q_d;
489 
`endif
490 
`ifdef LM32_NO_BARREL_SHIFT
491 
wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
492 
`endif
493 
 
494 
// To/from multiplier
495 
`ifdef LM32_MULTIPLY_ENABLED
496 
wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
497 
`endif
498 
`ifdef CFG_MC_MULTIPLY_ENABLED
499 
wire multiply_d;                                // Indicates whether to perform a multiply or not
500 
wire multiply_q_d;
501 
`endif
502 
 
503 
// To/from divider
504 
`ifdef CFG_MC_DIVIDE_ENABLED
505 
wire divide_d;                                  // Indicates whether to perform a divider or not
506 
wire divide_q_d;
507 
wire modulus_d;
508 
wire modulus_q_d;
509 
wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
510 
`endif
511 
 
512 
// To from multi-cycle arithmetic unit
513 
`ifdef LM32_MC_ARITHMETIC_ENABLED
514 
wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
515 
wire [`LM32_WORD_RNG] mc_result_x;
516 
`endif
517 
 
518 
// From CSRs
519 
`ifdef CFG_INTERRUPTS_ENABLED
520 
wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
521 
`endif
522 
wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
523 
`ifdef CFG_CYCLE_COUNTER_ENABLED
524 
reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
525 
`endif
526 
reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
527 
 
528 
// To/from instruction unit
529 
wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
530 
wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
531 
wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
532 
wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
533 
wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
534 
`ifdef CFG_TRACE_ENABLED
535 
reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
536 
`endif
537 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
538 
wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
539 
`endif
540 
wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
541 
`ifdef CFG_ICACHE_ENABLED
542 
wire iflush;                                    // Flush instruction cache
543 
wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
544 
wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
545 
wire icache_refill_request;                     // Request to refill instruction cache
546 
wire icache_refilling;                          // Indicates the instruction cache is being refilled
547 
`endif
548 
 
549 
// To/from load/store unit
550 
`ifdef CFG_DCACHE_ENABLED
551 
wire dflush_x;                                  // Flush data cache
552 
reg dflush_m;
553 
wire dcache_stall_request;                      // Stall pipeline because data cache is busy
554 
wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
555 
wire dcache_refill_request;                     // Request to refill data cache
556 
wire dcache_refilling;                          // Indicates the data cache is being refilled
557 
`endif
558 
wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
559 
wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
560 
 
561 
// To/from JTAG interface
562 
`ifdef CFG_JTAG_ENABLED
563 
`ifdef CFG_JTAG_UART_ENABLED
564 
wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
565 
wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
566 
`endif
567 
`ifdef CFG_HW_DEBUG_ENABLED
568 
wire jtag_csr_write_enable;                     // Debugger CSR write enable
569 
wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
570 
wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
571 
wire jtag_read_enable;
572 
wire [`LM32_BYTE_RNG] jtag_read_data;
573 
wire jtag_write_enable;
574 
wire [`LM32_BYTE_RNG] jtag_write_data;
575 
wire [`LM32_WORD_RNG] jtag_address;
576 
wire jtag_access_complete;
577 
`endif
578 
`ifdef CFG_DEBUG_ENABLED
579 
wire jtag_break;                                // Request from debugger to raise a breakpoint
580 
`endif
581 
`endif
582 
 
583 
// Hazzard detection
584 
wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
585 
wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
586 
wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
587 
wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
588 
wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
589 
wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
590 
 
591 
// Control flow
592 
wire cmp_zero;                                  // Result of comparison is zero
593 
wire cmp_negative;                              // Result of comparison is negative
594 
wire cmp_overflow;                              // Comparison produced an overflow
595 
wire cmp_carry_n;                               // Comparison produced a carry, inverted
596 
reg condition_met_x;                            // Condition of branch instruction is met
597 
reg condition_met_m;
598 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
599 
wire branch_taken_x;                            // Branch is taken in X stage
600 
`endif
601 
wire branch_taken_m;                            // Branch is taken in M stage
602 
 
603 
wire kill_f;                                    // Kill instruction in F stage
604 
wire kill_d;                                    // Kill instruction in D stage
605 
wire kill_x;                                    // Kill instruction in X stage
606 
wire kill_m;                                    // Kill instruction in M stage
607 
wire kill_w;                                    // Kill instruction in W stage
608 
 
609 
reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
610 
`ifdef CFG_DEBUG_ENABLED
611 
reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
612 
`endif
613 
reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
614 
`ifdef CFG_TRACE_ENABLED
615 
reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
616 
reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
617 
`endif
618 
 
619 
`ifdef CFG_DEBUG_ENABLED
620 
`ifdef LM32_SINGLE_STEP_ENABLED
621 
wire dc_ss;                                     // Is single-step enabled
622 
`endif
623 
wire dc_re;                                     // Remap all exceptions
624 
wire exception_x;                               // An exception occured in the X stage
625 
reg exception_m;                                // An instruction that caused an exception is in the M stage
626 
wire debug_exception_x;                         // Indicates if a debug exception has occured
627 
reg debug_exception_m;
628 
reg debug_exception_w;
629 
wire debug_exception_q_w;
630 
wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
631 
reg non_debug_exception_m;
632 
reg non_debug_exception_w;
633 
wire non_debug_exception_q_w;
634 
`else
635 
wire exception_x;                               // Indicates if a debug exception has occured
636 
reg exception_m;
637 
reg exception_w;
638 
wire exception_q_w;
639 
`endif
640 
 
641 
`ifdef CFG_DEBUG_ENABLED
642 
`ifdef CFG_JTAG_ENABLED
643 
wire reset_exception;                           // Indicates if a reset exception has occured
644 
`endif
645 
`endif
646 
`ifdef CFG_INTERRUPTS_ENABLED
647 
wire interrupt_exception;                       // Indicates if an interrupt exception has occured
648 
`endif
649 
`ifdef CFG_DEBUG_ENABLED
650 
wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
651 
wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
652 
`endif
653 
`ifdef CFG_BUS_ERRORS_ENABLED
654 
wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
655 
wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
656 
`endif
657 
`ifdef CFG_MC_DIVIDE_ENABLED
658 
wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
659 
`endif
660 
wire system_call_exception;                     // Indicates if a system call exception has occured
661 
 
662 
`ifdef CFG_BUS_ERRORS_ENABLED
663 
reg data_bus_error_seen;                        // Indicates if a data bus error was seen
664 
`endif
665 
 
666 
/////////////////////////////////////////////////////
667 
// Functions
668 
/////////////////////////////////////////////////////
669 
`define  INCLUDE_FUNCTION
670 
`include "lm32_functions.v"
671 
 
672 
/////////////////////////////////////////////////////
673 
// Instantiations
674 
/////////////////////////////////////////////////////
675 
 
676 
// Instruction unit
677 
lm32_instruction_unit #(
678 
    .associativity          (icache_associativity),
679 
    .sets                   (icache_sets),
680 
    .bytes_per_line         (icache_bytes_per_line),
681 
    .base_address           (icache_base_address),
682 
    .limit                  (icache_limit)
683 
  ) instruction_unit (
684 
    // ----- Inputs -------
685 
    .clk_i                  (clk_i),
686 
    .rst_i                  (rst_i),
687 
    // From pipeline
688 
    .stall_a                (stall_a),
689 
    .stall_f                (stall_f),
690 
    .stall_d                (stall_d),
691 
    .stall_x                (stall_x),
692 
    .stall_m                (stall_m),
693 
    .valid_f                (valid_f),
694 
    .kill_f                 (kill_f),
695 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
696 
    .branch_taken_x         (branch_taken_x),
697 
    .branch_target_x        (branch_target_x),
698 
`endif
699 
    .branch_taken_m         (branch_taken_m),
700 
    .branch_target_m        (branch_target_m),
701 
`ifdef CFG_ICACHE_ENABLED
702 
    .iflush                 (iflush),
703 
`endif
704 
`ifdef CFG_DCACHE_ENABLED
705 
    .dcache_restart_request (dcache_restart_request),
706 
    .dcache_refill_request  (dcache_refill_request),
707 
    .dcache_refilling       (dcache_refilling),
708 
`endif
709 
`ifdef CFG_IWB_ENABLED
710 
    // From Wishbone
711 
    .i_dat_i                (I_DAT_I),
712 
    .i_ack_i                (I_ACK_I),
713 
    .i_err_i                (I_ERR_I),
714 
    .i_rty_i                (I_RTY_I),
715 
`endif
716 
`ifdef CFG_HW_DEBUG_ENABLED
717 
    .jtag_read_enable       (jtag_read_enable),
718 
    .jtag_write_enable      (jtag_write_enable),
719 
    .jtag_write_data        (jtag_write_data),
720 
    .jtag_address           (jtag_address),
721 
`endif
722 
    // ----- Outputs -------
723 
    // To pipeline
724 
    .pc_f                   (pc_f),
725 
    .pc_d                   (pc_d),
726 
    .pc_x                   (pc_x),
727 
    .pc_m                   (pc_m),
728 
    .pc_w                   (pc_w),
729 
`ifdef CFG_ICACHE_ENABLED
730 
    .icache_stall_request   (icache_stall_request),
731 
    .icache_restart_request (icache_restart_request),
732 
    .icache_refill_request  (icache_refill_request),
733 
    .icache_refilling       (icache_refilling),
734 
`endif
735 
`ifdef CFG_IWB_ENABLED
736 
    // To Wishbone
737 
    .i_dat_o                (I_DAT_O),
738 
    .i_adr_o                (I_ADR_O),
739 
    .i_cyc_o                (I_CYC_O),
740 
    .i_sel_o                (I_SEL_O),
741 
    .i_stb_o                (I_STB_O),
742 
    .i_we_o                 (I_WE_O),
743 
    .i_cti_o                (I_CTI_O),
744 
    .i_lock_o               (I_LOCK_O),
745 
    .i_bte_o                (I_BTE_O),
746 
`endif
747 
`ifdef CFG_HW_DEBUG_ENABLED
748 
    .jtag_read_data         (jtag_read_data),
749 
    .jtag_access_complete   (jtag_access_complete),
750 
`endif
751 
`ifdef CFG_BUS_ERRORS_ENABLED
752 
    .bus_error_d            (bus_error_d),
753 
`endif
754 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
755 
    .instruction_f          (instruction_f),
756 
`endif
757 
    .instruction_d          (instruction_d)
758 
    );
759 
 
760 
// Trace instructions in simulation
761 
lm32_simtrace simtrace (
762 
    .clk_i                  (clk_i),
763 
    .rst_i                  (rst_i),
764 
    .stall_x                (stall_x),
765 
    .stall_m                (stall_m),
766 
    .valid_w                (valid_w),
767 
    .kill_w                 (kill_w),
768 
    .instruction_d          (instruction_d),
769 
    .pc_w                   (pc_w)
770 
    );
771 
 
772 
// Instruction decoder
773 
lm32_decoder decoder (
774 
    // ----- Inputs -------
775 
    .instruction            (instruction_d),
776 
    // ----- Outputs -------
777 
    .d_result_sel_0         (d_result_sel_0_d),
778 
    .d_result_sel_1         (d_result_sel_1_d),
779 
    .x_result_sel_csr       (x_result_sel_csr_d),
780 
`ifdef LM32_MC_ARITHMETIC_ENABLED
781 
    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
782 
`endif
783 
`ifdef LM32_NO_BARREL_SHIFT
784 
    .x_result_sel_shift     (x_result_sel_shift_d),
785 
`endif
786 
`ifdef CFG_SIGN_EXTEND_ENABLED
787 
    .x_result_sel_sext      (x_result_sel_sext_d),
788 
`endif
789 
    .x_result_sel_logic     (x_result_sel_logic_d),
790 
`ifdef CFG_USER_ENABLED
791 
    .x_result_sel_user      (x_result_sel_user_d),
792 
`endif
793 
    .x_result_sel_add       (x_result_sel_add_d),
794 
    .m_result_sel_compare   (m_result_sel_compare_d),
795 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
796 
    .m_result_sel_shift     (m_result_sel_shift_d),
797 
`endif
798 
    .w_result_sel_load      (w_result_sel_load_d),
799 
`ifdef CFG_PL_MULTIPLY_ENABLED
800 
    .w_result_sel_mul       (w_result_sel_mul_d),
801 
`endif
802 
    .x_bypass_enable        (x_bypass_enable_d),
803 
    .m_bypass_enable        (m_bypass_enable_d),
804 
    .read_enable_0          (read_enable_0_d),
805 
    .read_idx_0             (read_idx_0_d),
806 
    .read_enable_1          (read_enable_1_d),
807 
    .read_idx_1             (read_idx_1_d),
808 
    .write_enable           (write_enable_d),
809 
    .write_idx              (write_idx_d),
810 
    .immediate              (immediate_d),
811 
    .branch_offset          (branch_offset_d),
812 
    .load                   (load_d),
813 
    .store                  (store_d),
814 
    .size                   (size_d),
815 
    .sign_extend            (sign_extend_d),
816 
    .adder_op               (adder_op_d),
817 
    .logic_op               (logic_op_d),
818 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
819 
    .direction              (direction_d),
820 
`endif
821 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
822 
    .shift_left             (shift_left_d),
823 
    .shift_right            (shift_right_d),
824 
`endif
825 
`ifdef CFG_MC_MULTIPLY_ENABLED
826 
    .multiply               (multiply_d),
827 
`endif
828 
`ifdef CFG_MC_DIVIDE_ENABLED
829 
    .divide                 (divide_d),
830 
    .modulus                (modulus_d),
831 
`endif
832 
    .branch                 (branch_d),
833 
    .branch_reg             (branch_reg_d),
834 
    .condition              (condition_d),
835 
`ifdef CFG_DEBUG_ENABLED
836 
    .break                  (break_d),
837 
`endif
838 
    .scall                  (scall_d),
839 
    .eret                   (eret_d),
840 
`ifdef CFG_DEBUG_ENABLED
841 
    .bret                   (bret_d),
842 
`endif
843 
`ifdef CFG_USER_ENABLED
844 
    .user_opcode            (user_opcode_d),
845 
`endif
846 
    .csr_write_enable       (csr_write_enable_d)
847 
    );
848 
wire load_q_x,load_q_m,store_q_m;
849 
 
850 
// Load/store unit
851 
lm32_load_store_unit #(
852 
    .associativity          (dcache_associativity),
853 
    .sets                   (dcache_sets),
854 
    .bytes_per_line         (dcache_bytes_per_line),
855 
    .base_address           (dcache_base_address),
856 
    .limit                  (dcache_limit)
857 
  ) load_store_unit (
858 
    // ----- Inputs -------
859 
    .clk_i                  (clk_i),
860 
    .rst_i                  (rst_i),
861 
    // From pipeline
862 
    .stall_a                (stall_a),
863 
    .stall_x                (stall_x),
864 
    .stall_m                (stall_m),
865 
    .kill_x                 (kill_x),
866 
    .kill_m                 (kill_m),
867 
    .exception_m            (exception_m),
868 
    .store_operand_x        (store_operand_x),
869 
    .load_store_address_x   (adder_result_x),
870 
    .load_store_address_m   (operand_m),
871 
    .load_store_address_w   (operand_w[1:0]),
872 
    .load_q_x               (load_q_x),
873 
    .load_q_m               (load_q_m),
874 
    .store_q_m              (store_q_m),
875 
    .sign_extend_x          (sign_extend_x),
876 
    .size_x                 (size_x),
877 
`ifdef CFG_DCACHE_ENABLED
878 
    .dflush                 (dflush_m),
879 
`endif
880 
    // From Wishbone
881 
    .d_dat_i                (D_DAT_I),
882 
    .d_ack_i                (D_ACK_I),
883 
    .d_err_i                (D_ERR_I),
884 
    .d_rty_i                (D_RTY_I),
885 
    // ----- Outputs -------
886 
    // To pipeline
887 
`ifdef CFG_DCACHE_ENABLED
888 
    .dcache_refill_request  (dcache_refill_request),
889 
    .dcache_restart_request (dcache_restart_request),
890 
    .dcache_stall_request   (dcache_stall_request),
891 
    .dcache_refilling       (dcache_refilling),
892 
`endif
893 
    .load_data_w            (load_data_w),
894 
    .stall_wb_load          (stall_wb_load),
895 
    // To Wishbone
896 
    .d_dat_o                (D_DAT_O),
897 
    .d_adr_o                (D_ADR_O),
898 
    .d_cyc_o                (D_CYC_O),
899 
    .d_sel_o                (D_SEL_O),
900 
    .d_stb_o                (D_STB_O),
901 
    .d_we_o                 (D_WE_O),
902 
    .d_cti_o                (D_CTI_O),
903 
    .d_lock_o               (D_LOCK_O),
904 
    .d_bte_o                (D_BTE_O)
905 
    );
906 
 
907 
// Adder
908 
lm32_adder adder (
909 
    // ----- Inputs -------
910 
    .adder_op_x             (adder_op_x),
911 
    .adder_op_x_n           (adder_op_x_n),
912 
    .operand_0_x            (operand_0_x),
913 
    .operand_1_x            (operand_1_x),
914 
    // ----- Outputs -------
915 
    .adder_result_x         (adder_result_x),
916 
    .adder_carry_n_x        (adder_carry_n_x),
917 
    .adder_overflow_x       (adder_overflow_x)
918 
    );
919 
 
920 
// Logic operations
921 
lm32_logic_op logic_op (
922 
    // ----- Inputs -------
923 
    .logic_op_x             (logic_op_x),
924 
    .operand_0_x            (operand_0_x),
925 
 
926 
    .operand_1_x            (operand_1_x),
927 
    // ----- Outputs -------
928 
    .logic_result_x         (logic_result_x)
929 
    );
930 
 
931 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
932 
// Pipelined barrel-shifter
933 
lm32_shifter shifter (
934 
    // ----- Inputs -------
935 
    .clk_i                  (clk_i),
936 
    .rst_i                  (rst_i),
937 
    .stall_x                (stall_x),
938 
    .direction_x            (direction_x),
939 
    .sign_extend_x          (sign_extend_x),
940 
    .operand_0_x            (operand_0_x),
941 
    .operand_1_x            (operand_1_x),
942 
    // ----- Outputs -------
943 
    .shifter_result_m       (shifter_result_m)
944 
    );
945 
`endif
946 
 
947 
`ifdef CFG_PL_MULTIPLY_ENABLED
948 
// Pipeline fixed-point multiplier
949 
lm32_multiplier multiplier (
950 
    // ----- Inputs -------
951 
    .clk_i                  (clk_i),
952 
    .rst_i                  (rst_i),
953 
    .stall_x                (stall_x),
954 
    .stall_m                (stall_m),
955 
    .operand_0              (d_result_0),
956 
    .operand_1              (d_result_1),
957 
    // ----- Outputs -------
958 
    .result                 (multiplier_result_w)
959 
    );
960 
`endif
961 
 
962 
`ifdef LM32_MC_ARITHMETIC_ENABLED
963 
// Multi-cycle arithmetic
964 
lm32_mc_arithmetic mc_arithmetic (
965 
    // ----- Inputs -------
966 
    .clk_i                  (clk_i),
967 
    .rst_i                  (rst_i),
968 
    .stall_d                (stall_d),
969 
    .kill_x                 (kill_x),
970 
`ifdef CFG_MC_DIVIDE_ENABLED
971 
    .divide_d               (divide_q_d),
972 
    .modulus_d              (modulus_q_d),
973 
`endif
974 
`ifdef CFG_MC_MULTIPLY_ENABLED
975 
    .multiply_d             (multiply_q_d),
976 
`endif
977 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
978 
    .shift_left_d           (shift_left_q_d),
979 
    .shift_right_d          (shift_right_q_d),
980 
    .sign_extend_d          (sign_extend_d),
981 
`endif
982 
    .operand_0_d            (d_result_0),
983 
    .operand_1_d            (d_result_1),
984 
    // ----- Outputs -------
985 
    .result_x               (mc_result_x),
986 
`ifdef CFG_MC_DIVIDE_ENABLED
987 
    .divide_by_zero_x       (divide_by_zero_x),
988 
`endif
989 
    .stall_request_x        (mc_stall_request_x)
990 
    );
991 
`endif
992 
 
993 
`ifdef CFG_INTERRUPTS_ENABLED
994 
// Interrupt unit
995 
lm32_interrupt interrupt (
996 
    // ----- Inputs -------
997 
    .clk_i                  (clk_i),
998 
    .rst_i                  (rst_i),
999 
    // From external devices
1000 
    .interrupt_n            (interrupt_n),
1001 
    // From pipeline
1002 
    .stall_x                (stall_x),
1003 
`ifdef CFG_DEBUG_ENABLED
1004 
    .non_debug_exception    (non_debug_exception_q_w),
1005 
    .debug_exception        (debug_exception_q_w),
1006 
`else
1007 
    .exception              (exception_q_w),
1008 
`endif
1009 
    .eret_q_x               (eret_q_x),
1010 
`ifdef CFG_DEBUG_ENABLED
1011 
    .bret_q_x               (bret_q_x),
1012 
`endif
1013 
    .csr                    (csr_x),
1014 
    .csr_write_data         (operand_1_x),
1015 
    .csr_write_enable       (csr_write_enable_q_x),
1016 
    // ----- Outputs -------
1017 
    .interrupt_exception    (interrupt_exception),
1018 
    // To pipeline
1019 
    .csr_read_data          (interrupt_csr_read_data_x)
1020 
    );
1021 
`endif
1022 
 
1023 
`ifdef CFG_JTAG_ENABLED
1024 
// JTAG interface
1025 
lm32_jtag jtag (
1026 
    // ----- Inputs -------
1027 
    .clk_i                  (clk_i),
1028 
    .rst_i                  (rst_i),
1029 
    // From JTAG
1030 
    .jtag_clk               (jtag_clk),
1031 
    .jtag_update            (jtag_update),
1032 
    .jtag_reg_q             (jtag_reg_q),
1033 
    .jtag_reg_addr_q        (jtag_reg_addr_q),
1034 
    // From pipeline
1035 
`ifdef CFG_JTAG_UART_ENABLED
1036 
    .csr                    (csr_x),
1037 
    .csr_write_data         (operand_1_x),
1038 
    .csr_write_enable       (csr_write_enable_q_x),
1039 
    .stall_x                (stall_x),
1040 
`endif
1041 
`ifdef CFG_HW_DEBUG_ENABLED
1042 
    .jtag_read_data         (jtag_read_data),
1043 
    .jtag_access_complete   (jtag_access_complete),
1044 
`endif
1045 
`ifdef CFG_DEBUG_ENABLED
1046 
    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
1047 
`endif
1048 
    // ----- Outputs -------
1049 
    // To pipeline
1050 
`ifdef CFG_JTAG_UART_ENABLED
1051 
    .jtx_csr_read_data      (jtx_csr_read_data),
1052 
    .jrx_csr_read_data      (jrx_csr_read_data),
1053 
`endif
1054 
`ifdef CFG_HW_DEBUG_ENABLED
1055 
    .jtag_csr_write_enable  (jtag_csr_write_enable),
1056 
    .jtag_csr_write_data    (jtag_csr_write_data),
1057 
    .jtag_csr               (jtag_csr),
1058 
    .jtag_read_enable       (jtag_read_enable),
1059 
    .jtag_write_enable      (jtag_write_enable),
1060 
    .jtag_write_data        (jtag_write_data),
1061 
    .jtag_address           (jtag_address),
1062 
`endif
1063 
`ifdef CFG_DEBUG_ENABLED
1064 
    .jtag_break             (jtag_break),
1065 
    .jtag_reset             (reset_exception),
1066 
`endif
1067 
    // To JTAG
1068 
    .jtag_reg_d             (jtag_reg_d),
1069 
    .jtag_reg_addr_d        (jtag_reg_addr_d)
1070 
    );
1071 
`endif
1072 
 
1073 
`ifdef CFG_DEBUG_ENABLED
1074 
// Debug unit
1075 
lm32_debug #(
1076 
    .breakpoints            (breakpoints),
1077 
    .watchpoints            (watchpoints)
1078 
  ) hw_debug (
1079 
    // ----- Inputs -------
1080 
    .clk_i                  (clk_i),
1081 
    .rst_i                  (rst_i),
1082 
    .pc_x                   (pc_x),
1083 
    .load_x                 (load_x),
1084 
    .store_x                (store_x),
1085 
    .load_store_address_x   (adder_result_x),
1086 
    .csr_write_enable_x     (csr_write_enable_q_x),
1087 
    .csr_write_data         (operand_1_x),
1088 
    .csr_x                  (csr_x),
1089 
`ifdef CFG_HW_DEBUG_ENABLED
1090 
    .jtag_csr_write_enable  (jtag_csr_write_enable),
1091 
    .jtag_csr_write_data    (jtag_csr_write_data),
1092 
    .jtag_csr               (jtag_csr),
1093 
`endif
1094 
`ifdef LM32_SINGLE_STEP_ENABLED
1095 
    .eret_q_x               (eret_q_x),
1096 
    .bret_q_x               (bret_q_x),
1097 
    .stall_x                (stall_x),
1098 
    .exception_x            (exception_x),
1099 
    .q_x                    (q_x),
1100 
`ifdef CFG_DCACHE_ENABLED
1101 
    .dcache_refill_request  (dcache_refill_request),
1102 
`endif
1103 
`endif
1104 
    // ----- Outputs -------
1105 
`ifdef LM32_SINGLE_STEP_ENABLED
1106 
    .dc_ss                  (dc_ss),
1107 
`endif
1108 
    .dc_re                  (dc_re),
1109 
    .bp_match               (bp_match),
1110 
    .wp_match               (wp_match)
1111 
    );
1112 
`endif
1113 
 
1114 
// Register file
1115 
 
1116 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1117 
 
1118 
lm32_ram #(
1119 
    // ----- Parameters -------
1120 
    .data_width             (`LM32_WORD_WIDTH),
1121 
    .address_width          (`LM32_REG_IDX_WIDTH)
1122 
  ) reg_0 (
1123 
    // ----- Inputs -------
1124 
    .read_clk               (clk_i),
1125 
    .write_clk              (clk_i),
1126 
    .reset                  (rst_i),
1127 
    .enable_read            (stall_d == `FALSE),
1128 
    .read_address           (instruction_f[25:21]),
1129 
    .enable_write           (`TRUE),
1130 
    .write_address          (write_idx_w),
1131 
    .write_data             (w_result),
1132 
    .write_enable           (reg_write_enable_q_w),
1133 
    // ----- Outputs -------
1134 
    .read_data              (reg_data_live_0)
1135 
    );
1136 
 
1137 
lm32_ram #(
1138 
    // ----- Parameters -------
1139 
    .data_width             (`LM32_WORD_WIDTH),
1140 
    .address_width          (`LM32_REG_IDX_WIDTH)
1141 
  ) reg_1 (
1142 
    // ----- Inputs -------
1143 
    .read_clk               (clk_i),
1144 
    .write_clk              (clk_i),
1145 
    .reset                  (rst_i),
1146 
    .enable_read            (stall_d == `FALSE),
1147 
    .read_address           (instruction_f[20:16]),
1148 
    .enable_write           (`TRUE),
1149 
    .write_address          (write_idx_w),
1150 
    .write_data             (w_result),
1151 
    .write_enable           (reg_write_enable_q_w),
1152 
    // ----- Outputs -------
1153 
    .read_data              (reg_data_live_1)
1154 
    );
1155 
 
1156 
`endif
1157 
 
1158 
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1159 
 
1160 
lm32_ram #(
1161 
    // ----- Parameters -------
1162 
    .data_width             (`LM32_WORD_WIDTH),
1163 
    .address_width          (`LM32_REG_IDX_WIDTH)
1164 
  ) reg_0 (
1165 
    // ----- Inputs -------
1166 
    .read_clk               (clk_n_i),
1167 
    .write_clk              (clk_i),
1168 
    .reset                  (rst_i),
1169 
    .enable_read            (stall_f == `FALSE),
1170 
    .read_address           (read_idx_0_d),
1171 
    .enable_write           (`TRUE),
1172 
    .write_address          (write_idx_w),
1173 
    .write_data             (w_result),
1174 
    .write_enable           (reg_write_enable_q_w),
1175 
    // ----- Outputs -------
1176 
    .read_data              (reg_data_0)
1177 
    );
1178 
 
1179 
lm32_ram #(
1180 
    // ----- Parameters -------
1181 
    .data_width             (`LM32_WORD_WIDTH),
1182 
    .address_width          (`LM32_REG_IDX_WIDTH)
1183 
  ) reg_1 (
1184 
    // ----- Inputs -------
1185 
    .read_clk               (clk_n_i),
1186 
    .write_clk              (clk_i),
1187 
    .reset                  (rst_i),
1188 
    .enable_read            (stall_f == `FALSE),
1189 
    .read_address           (read_idx_1_d),
1190 
    .enable_write           (`TRUE),
1191 
    .write_address          (write_idx_w),
1192 
    .write_data             (w_result),
1193 
    .write_enable           (reg_write_enable_q_w),
1194 
    // ----- Outputs -------
1195 
    .read_data              (reg_data_1)
1196 
    );
1197 
 
1198 
`endif
1199 
 
1200 
 
1201 
/////////////////////////////////////////////////////
1202 
// Combinational Logic
1203 
/////////////////////////////////////////////////////
1204 
 
1205 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1206 
// Select between buffered and live data from register file
1207 
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1208 
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1209 
`endif
1210 
`ifdef LM32_EBR_REGISTER_FILE
1211 
`else
1212 
// Register file read ports
1213 
assign reg_data_0 = registers[read_idx_0_d];
1214 
assign reg_data_1 = registers[read_idx_1_d];
1215 
`endif
1216 
 
1217 
// Detect read-after-write hazzards
1218 
assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1219 
assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1220 
assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1221 
assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1222 
assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1223 
assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1224 
 
1225 
// Interlock detection - Raise an interlock for RAW hazzards
1226 
always @*
1227 
begin
1228 
    if (   (   (x_bypass_enable_x == `FALSE)
1229 
            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1230 
                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1231 
               )
1232 
           )
1233 
        || (   (m_bypass_enable_m == `FALSE)
1234 
            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1235 
                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1236 
               )
1237 
           )
1238 
       )
1239 
        interlock = `TRUE;
1240 
    else
1241 
        interlock = `FALSE;
1242 
end
1243 
 
1244 
// Bypass for reg port 0
1245 
always @*
1246 
begin
1247 
    if (raw_x_0 == `TRUE)
1248 
        bypass_data_0 = x_result;
1249 
    else if (raw_m_0 == `TRUE)
1250 
        bypass_data_0 = m_result;
1251 
    else if (raw_w_0 == `TRUE)
1252 
        bypass_data_0 = w_result;
1253 
    else
1254 
        bypass_data_0 = reg_data_0;
1255 
end
1256 
 
1257 
// Bypass for reg port 1
1258 
always @*
1259 
begin
1260 
    if (raw_x_1 == `TRUE)
1261 
        bypass_data_1 = x_result;
1262 
    else if (raw_m_1 == `TRUE)
1263 
        bypass_data_1 = m_result;
1264 
    else if (raw_w_1 == `TRUE)
1265 
        bypass_data_1 = w_result;
1266 
    else
1267 
        bypass_data_1 = reg_data_1;
1268 
end
1269 
 
1270 
// D stage result selection
1271 
always @*
1272 
begin
1273 
    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1274 
    case (d_result_sel_1_d)
1275 
    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1276 
    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
1277 
    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1278 
    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1279 
    endcase
1280 
end
1281 
 
1282 
`ifdef CFG_USER_ENABLED
1283 
// Operands for user-defined instructions
1284 
assign user_operand_0 = operand_0_x;
1285 
assign user_operand_1 = operand_1_x;
1286 
`endif
1287 
 
1288 
`ifdef CFG_SIGN_EXTEND_ENABLED
1289 
// Sign-extension
1290 
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1291 
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1292 
assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1293 
`endif
1294 
 
1295 
`ifdef LM32_NO_BARREL_SHIFT
1296 
// Only single bit shift operations are supported when barrel-shifter isn't implemented
1297 
assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1298 
`endif
1299 
 
1300 
// Condition evaluation
1301 
assign cmp_zero = operand_0_x == operand_1_x;
1302 
assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1303 
assign cmp_overflow = adder_overflow_x;
1304 
assign cmp_carry_n = adder_carry_n_x;
1305 
always @*
1306 
begin
1307 
    case (condition_x)
1308 
    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
1309 
    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
1310 
    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
1311 
    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
1312 
    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1313 
    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
1314 
    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
1315 
    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
1316 
    default:              condition_met_x = 1'bx;
1317 
    endcase
1318 
end
1319 
 
1320 
// X stage result selection
1321 
always @*
1322 
begin
1323 
    x_result =   x_result_sel_add_x ? adder_result_x
1324 
               : x_result_sel_csr_x ? csr_read_data_x
1325 
`ifdef CFG_SIGN_EXTEND_ENABLED
1326 
               : x_result_sel_sext_x ? sext_result_x
1327 
`endif
1328 
`ifdef CFG_USER_ENABLED
1329 
               : x_result_sel_user_x ? user_result
1330 
`endif
1331 
`ifdef LM32_NO_BARREL_SHIFT
1332 
               : x_result_sel_shift_x ? shifter_result_x
1333 
`endif
1334 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1335 
               : x_result_sel_mc_arith_x ? mc_result_x
1336 
`endif
1337 
               : logic_result_x;
1338 
end
1339 
 
1340 
// M stage result selection
1341 
always @*
1342 
begin
1343 
    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1344 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1345 
               : m_result_sel_shift_m ? shifter_result_m
1346 
`endif
1347 
               : operand_m;
1348 
end
1349 
 
1350 
// W stage result selection
1351 
always @*
1352 
begin
1353 
    w_result =    w_result_sel_load_w ? load_data_w
1354 
`ifdef CFG_PL_MULTIPLY_ENABLED
1355 
                : w_result_sel_mul_w ? multiplier_result_w
1356 
`endif
1357 
                : operand_w;
1358 
end
1359 
 
1360 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1361 
// Indicate when a branch should be taken in X stage
1362 
assign branch_taken_x =      (stall_x == `FALSE)
1363 
                          && (   (branch_x == `TRUE)
1364 
                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
1365 
                              && (valid_x == `TRUE)
1366 
                             );
1367 
`endif
1368 
 
1369 
// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1370 
assign branch_taken_m =      (stall_m == `FALSE)
1371 
                          && (   (   (branch_m == `TRUE)
1372 
                                  && (condition_met_m == `TRUE)
1373 
                                  && (valid_m == `TRUE)
1374 
                                 )
1375 
                              || (exception_m == `TRUE)
1376 
                             );
1377 
 
1378 
// Generate signal that will kill instructions in each pipeline stage when necessary
1379 
assign kill_f =    (branch_taken_m == `TRUE)
1380 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1381 
                || (branch_taken_x == `TRUE)
1382 
`endif
1383 
`ifdef CFG_ICACHE_ENABLED
1384 
                || (icache_refill_request == `TRUE)
1385 
`endif
1386 
`ifdef CFG_DCACHE_ENABLED
1387 
                || (dcache_refill_request == `TRUE)
1388 
`endif
1389 
                ;
1390 
assign kill_d =    (branch_taken_m == `TRUE)
1391 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1392 
                || (branch_taken_x == `TRUE)
1393 
`endif
1394 
`ifdef CFG_ICACHE_ENABLED
1395 
                || (icache_refill_request == `TRUE)
1396 
`endif
1397 
`ifdef CFG_DCACHE_ENABLED
1398 
                || (dcache_refill_request == `TRUE)
1399 
`endif
1400 
                ;
1401 
assign kill_x =    (branch_taken_m == `TRUE)
1402 
`ifdef CFG_DCACHE_ENABLED
1403 
                || (dcache_refill_request == `TRUE)
1404 
`endif
1405 
                ;
1406 
assign kill_m =    `FALSE
1407 
`ifdef CFG_DCACHE_ENABLED
1408 
                || (dcache_refill_request == `TRUE)
1409 
`endif
1410 
                ;
1411 
assign kill_w =    `FALSE
1412 
`ifdef CFG_DCACHE_ENABLED
1413 
                || (dcache_refill_request == `TRUE)
1414 
`endif
1415 
                ;
1416 
 
1417 
// Exceptions
1418 
 
1419 
`ifdef CFG_DEBUG_ENABLED
1420 
assign breakpoint_exception =    (break_x == `TRUE)
1421 
                              || (bp_match == `TRUE)
1422 
`ifdef CFG_JTAG_ENABLED
1423 
                              || (jtag_break == `TRUE)
1424 
`endif
1425 
                              ;
1426 
assign watchpoint_exception = wp_match == `TRUE;
1427 
`endif
1428 
`ifdef CFG_BUS_ERRORS_ENABLED
1429 
assign instruction_bus_error_exception = bus_error_x == `TRUE;
1430 
assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1431 
`endif
1432 
`ifdef CFG_MC_DIVIDE_ENABLED
1433 
assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1434 
`endif
1435 
assign system_call_exception = scall_x == `TRUE;
1436 
 
1437 
`ifdef CFG_DEBUG_ENABLED
1438 
assign debug_exception_x =  (breakpoint_exception == `TRUE)
1439 
                         || (watchpoint_exception == `TRUE)
1440 
                         ;
1441 
 
1442 
assign non_debug_exception_x = (system_call_exception == `TRUE)
1443 
`ifdef CFG_JTAG_ENABLED
1444 
                            || (reset_exception == `TRUE)
1445 
`endif
1446 
`ifdef CFG_BUS_ERRORS_ENABLED
1447 
                            || (instruction_bus_error_exception == `TRUE)
1448 
                            || (data_bus_error_exception == `TRUE)
1449 
`endif
1450 
`ifdef CFG_MC_DIVIDE_ENABLED
1451 
                            || (divide_by_zero_exception == `TRUE)
1452 
`endif
1453 
`ifdef CFG_INTERRUPTS_ENABLED
1454 
                            || (   (interrupt_exception == `TRUE)
1455 
`ifdef LM32_SINGLE_STEP_ENABLED
1456 
                                && (dc_ss == `FALSE)
1457 
`endif
1458 
                               )
1459 
`endif
1460 
                            ;
1461 
 
1462 
assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
1463 
`else
1464 
assign exception_x =           (system_call_exception == `TRUE)
1465 
`ifdef CFG_BUS_ERRORS_ENABLED
1466 
                            || (instruction_bus_error_exception == `TRUE)
1467 
                            || (data_bus_error_exception == `TRUE)
1468 
`endif
1469 
`ifdef CFG_MC_DIVIDE_ENABLED
1470 
                            || (divide_by_zero_exception == `TRUE)
1471 
`endif
1472 
`ifdef CFG_INTERRUPTS_ENABLED
1473 
                            || (   (interrupt_exception == `TRUE)
1474 
`ifdef LM32_SINGLE_STEP_ENABLED
1475 
                                && (dc_ss == `FALSE)
1476 
`endif
1477 
                               )
1478 
`endif
1479 
                            ;
1480 
`endif
1481 
 
1482 
// Exception ID
1483 
always @*
1484 
begin
1485 
`ifdef CFG_DEBUG_ENABLED
1486 
`ifdef CFG_JTAG_ENABLED
1487 
    if (reset_exception == `TRUE)
1488 
        eid_x = `LM32_EID_RESET;
1489 
    else
1490 
`endif
1491 
         if (breakpoint_exception == `TRUE)
1492 
        eid_x = `LM32_EID_BREAKPOINT;
1493 
    else
1494 
`endif
1495 
`ifdef CFG_BUS_ERRORS_ENABLED
1496 
         if (instruction_bus_error_exception == `TRUE)
1497 
        eid_x = `LM32_EID_INST_BUS_ERROR;
1498 
    else
1499 
`endif
1500 
`ifdef CFG_DEBUG_ENABLED
1501 
         if (watchpoint_exception == `TRUE)
1502 
        eid_x = `LM32_EID_WATCHPOINT;
1503 
    else
1504 
`endif
1505 
`ifdef CFG_BUS_ERRORS_ENABLED
1506 
         if (data_bus_error_exception == `TRUE)
1507 
        eid_x = `LM32_EID_DATA_BUS_ERROR;
1508 
    else
1509 
`endif
1510 
`ifdef CFG_MC_DIVIDE_ENABLED
1511 
         if (divide_by_zero_exception == `TRUE)
1512 
        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1513 
    else
1514 
`endif
1515 
`ifdef CFG_INTERRUPTS_ENABLED
1516 
         if (   (interrupt_exception == `TRUE)
1517 
`ifdef LM32_SINGLE_STEP_ENABLED
1518 
             && (dc_ss == `FALSE)
1519 
`endif
1520 
            )
1521 
        eid_x = `LM32_EID_INTERRUPT;
1522 
    else
1523 
`endif
1524 
        eid_x = `LM32_EID_SCALL;
1525 
end
1526 
 
1527 
// Stall generation
1528 
 
1529 
assign stall_a = (stall_f == `TRUE);
1530 
 
1531 
assign stall_f = (stall_d == `TRUE);
1532 
 
1533 
assign stall_d =   (stall_x == `TRUE)
1534 
                || (   (interlock == `TRUE)
1535 
                    && (kill_d == `FALSE)
1536 
                   )
1537 
                || (   (eret_d == `TRUE)
1538 
                    && (load_q_x == `TRUE)
1539 
                   )
1540 
`ifdef CFG_DEBUG_ENABLED
1541 
                || (   (bret_d == `TRUE)
1542 
                    && (load_q_x == `TRUE)
1543 
                   )
1544 
`endif
1545 
                || (   (csr_write_enable_d == `TRUE)
1546 
                    && (load_q_x == `TRUE)
1547 
                   )
1548 
                ;
1549 
 
1550 
assign stall_x =    (stall_m == `TRUE)
1551 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1552 
                 || (   (mc_stall_request_x == `TRUE)
1553 
                     && (kill_x == `FALSE)
1554 
                    )
1555 
`endif
1556 
                 ;
1557 
 
1558 
assign stall_m =    (stall_wb_load == `TRUE)
1559 
`ifdef CFG_SIZE_OVER_SPEED
1560 
                 || (D_CYC_O == `TRUE)
1561 
`else
1562 
                 || (   (D_CYC_O == `TRUE)
1563 
                     && (   (store_m == `TRUE)
1564 
                         || (load_m == `TRUE)
1565 
                         || (load_x == `TRUE)
1566 
                        )
1567 
                    )
1568 
`endif
1569 
`ifdef CFG_DCACHE_ENABLED
1570 
                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1571 
`endif
1572 
`ifdef CFG_ICACHE_ENABLED
1573 
                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
1574 
                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
1575 
`else
1576 
`ifdef CFG_IWB_ENABLED
1577 
                 || (I_CYC_O == `TRUE)
1578 
`endif
1579 
`endif
1580 
`ifdef CFG_USER_ENABLED
1581 
                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1582 
                     && (user_complete == `FALSE)
1583 
                    )
1584 
`endif
1585 
                 ;
1586 
 
1587 
// Qualify state changing control signals
1588 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1589 
wire   q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1590 
`endif
1591 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
1592 
assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1593 
assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1594 
`endif
1595 
`ifdef CFG_MC_MULTIPLY_ENABLED
1596 
assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1597 
`endif
1598 
`ifdef CFG_MC_DIVIDE_ENABLED
1599 
assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1600 
assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1601 
`endif
1602 
wire   q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1603 
assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1604 
assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1605 
`ifdef CFG_DEBUG_ENABLED
1606 
assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1607 
`endif
1608 
assign load_q_x = (load_x == `TRUE)
1609 
               && (q_x == `TRUE)
1610 
`ifdef CFG_DEBUG_ENABLED
1611 
               && (bp_match == `FALSE)
1612 
`endif
1613 
                  ;
1614 
`ifdef CFG_USER_ENABLED
1615 
assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1616 
`endif
1617 
wire   q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1618 
assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1619 
assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1620 
`ifdef CFG_DEBUG_ENABLED
1621 
assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1622 
assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1623 
`else
1624 
assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1625 
`endif
1626 
// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1627 
assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE);
1628 
assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1629 
assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1630 
// The enable that actually does write the registers needs to be qualified with kill
1631 
assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
1632 
 
1633 
// Configuration (CFG) CSR
1634 
assign cfg = {
1635 
              `LM32_REVISION,
1636 
              watchpoints[3:0],
1637 
              breakpoints[3:0],
1638 
              interrupts[5:0],
1639 
`ifdef CFG_JTAG_UART_ENABLED
1640 
              `TRUE,
1641 
`else
1642 
              `FALSE,
1643 
`endif
1644 
`ifdef CFG_ROM_DEBUG_ENABLED
1645 
              `TRUE,
1646 
`else
1647 
              `FALSE,
1648 
`endif
1649 
`ifdef CFG_HW_DEBUG_ENABLED
1650 
              `TRUE,
1651 
`else
1652 
              `FALSE,
1653 
`endif
1654 
`ifdef CFG_DEBUG_ENABLED
1655 
              `TRUE,
1656 
`else
1657 
              `FALSE,
1658 
`endif
1659 
`ifdef CFG_ICACHE_ENABLED
1660 
              `TRUE,
1661 
`else
1662 
              `FALSE,
1663 
`endif
1664 
`ifdef CFG_DCACHE_ENABLED
1665 
              `TRUE,
1666 
`else
1667 
              `FALSE,
1668 
`endif
1669 
`ifdef CFG_CYCLE_COUNTER_ENABLED
1670 
              `TRUE,
1671 
`else
1672 
              `FALSE,
1673 
`endif
1674 
`ifdef CFG_USER_ENABLED
1675 
              `TRUE,
1676 
`else
1677 
              `FALSE,
1678 
`endif
1679 
`ifdef CFG_SIGN_EXTEND_ENABLED
1680 
              `TRUE,
1681 
`else
1682 
              `FALSE,
1683 
`endif
1684 
`ifdef LM32_BARREL_SHIFT_ENABLED
1685 
              `TRUE,
1686 
`else
1687 
              `FALSE,
1688 
`endif
1689 
`ifdef CFG_MC_DIVIDE_ENABLED
1690 
              `TRUE,
1691 
`else
1692 
              `FALSE,
1693 
`endif
1694 
`ifdef LM32_MULTIPLY_ENABLED
1695 
              `TRUE
1696 
`else
1697 
              `FALSE
1698 
`endif
1699 
              };
1700 
 
1701 
// Cache flush
1702 
`ifdef CFG_ICACHE_ENABLED
1703 
assign iflush =    (csr_write_enable_d == `TRUE)
1704 
                && (csr_d == `LM32_CSR_ICC)
1705 
                && (stall_d == `FALSE)
1706 
                && (kill_d == `FALSE)
1707 
                && (valid_d == `TRUE);
1708 
`endif
1709 
`ifdef CFG_DCACHE_ENABLED
1710 
assign dflush_x =  (csr_write_enable_q_x == `TRUE)
1711 
                && (csr_x == `LM32_CSR_DCC);
1712 
`endif
1713 
 
1714 
// Extract CSR index
1715 
assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
1716 
 
1717 
// CSR reads
1718 
always @*
1719 
begin
1720 
    case (csr_x)
1721 
`ifdef CFG_INTERRUPTS_ENABLED
1722 
    `LM32_CSR_IE,
1723 
    `LM32_CSR_IM,
1724 
    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;
1725 
`endif
1726 
`ifdef CFG_CYCLE_COUNTER_ENABLED
1727 
    `LM32_CSR_CC:   csr_read_data_x = cc;
1728 
`endif
1729 
    `LM32_CSR_CFG:  csr_read_data_x = cfg;
1730 
    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
1731 
`ifdef CFG_DEBUG_ENABLED
1732 
    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
1733 
`endif
1734 
`ifdef CFG_JTAG_UART_ENABLED
1735 
    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;
1736 
    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
1737 
`endif
1738 
    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
1739 
    endcase
1740 
end
1741 
 
1742 
/////////////////////////////////////////////////////
1743 
// Sequential Logic
1744 
/////////////////////////////////////////////////////
1745 
 
1746 
// Exception Base Address (EBA) CSR
1747 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1748 
begin
1749 
    if (rst_i == `TRUE)
1750 
        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
1751 
    else
1752 
    begin
1753 
        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
1754 
            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
1755 
`ifdef CFG_HW_DEBUG_ENABLED
1756 
        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
1757 
            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
1758 
`endif
1759 
    end
1760 
end
1761 
 
1762 
`ifdef CFG_DEBUG_ENABLED
1763 
// Debug Exception Base Address (DEBA) CSR
1764 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1765 
begin
1766 
    if (rst_i == `TRUE)
1767 
        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
1768 
    else
1769 
    begin
1770 
        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
1771 
            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
1772 
`ifdef CFG_HW_DEBUG_ENABLED
1773 
        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
1774 
            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
1775 
`endif
1776 
    end
1777 
end
1778 
`endif
1779 
 
1780 
// Cycle Counter (CC) CSR
1781 
`ifdef CFG_CYCLE_COUNTER_ENABLED
1782 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1783 
begin
1784 
    if (rst_i == `TRUE)
1785 
        cc <= {`LM32_WORD_WIDTH{1'b0}};
1786 
    else
1787 
        cc <= cc + 1'b1;
1788 
end
1789 
`endif
1790 
 
1791 
`ifdef CFG_BUS_ERRORS_ENABLED
1792 
// Watch for data bus errors
1793 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1794 
begin
1795 
    if (rst_i == `TRUE)
1796 
        data_bus_error_seen <= `FALSE;
1797 
    else
1798 
    begin
1799 
        // Set flag when bus error is detected
1800 
        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
1801 
            data_bus_error_seen <= `TRUE;
1802 
        // Clear flag when exception is taken
1803 
        if ((exception_m == `TRUE) && (kill_m == `FALSE))
1804 
            data_bus_error_seen <= `FALSE;
1805 
    end
1806 
end
1807 
`endif
1808 
 
1809 
// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
1810 
 
1811 
`ifdef CFG_ICACHE_ENABLED
1812 
`ifdef CFG_DCACHE_ENABLED
1813 
always @*
1814 
begin
1815 
    if (   (icache_refill_request == `TRUE)
1816 
        || (dcache_refill_request == `TRUE)
1817 
       )
1818 
        valid_a = `FALSE;
1819 
    else if (   (icache_restart_request == `TRUE)
1820 
             || (dcache_restart_request == `TRUE)
1821 
            )
1822 
        valid_a = `TRUE;
1823 
    else
1824 
        valid_a = !icache_refilling && !dcache_refilling;
1825 
end
1826 
`else
1827 
always @*
1828 
begin
1829 
    if (icache_refill_request == `TRUE)
1830 
        valid_a = `FALSE;
1831 
    else if (icache_restart_request == `TRUE)
1832 
        valid_a = `TRUE;
1833 
    else
1834 
        valid_a = !icache_refilling;
1835 
end
1836 
`endif
1837 
`else
1838 
`ifdef CFG_DCACHE_ENABLED
1839 
always @*
1840 
begin
1841 
    if (dcache_refill_request == `TRUE)
1842 
        valid_a = `FALSE;
1843 
    else if (dcache_restart_request == `TRUE)
1844 
        valid_a = `TRUE;
1845 
    else
1846 
        valid_a = !dcache_refilling;
1847 
end
1848 
`endif
1849 
`endif
1850 
 
1851 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1852 
begin
1853 
    if (rst_i == `TRUE)
1854 
    begin
1855 
        valid_f <= `FALSE;
1856 
        valid_d <= `FALSE;
1857 
        valid_x <= `FALSE;
1858 
        valid_m <= `FALSE;
1859 
        valid_w <= `FALSE;
1860 
    end
1861 
    else
1862 
    begin
1863 
        if ((kill_f == `TRUE) || (stall_a == `FALSE))
1864 
`ifdef LM32_CACHE_ENABLED
1865 
            valid_f <= valid_a;
1866 
`else
1867 
            valid_f <= `TRUE;
1868 
`endif
1869 
        else if (stall_f == `FALSE)
1870 
            valid_f <= `FALSE;
1871 
        if (kill_d == `TRUE)
1872 
            valid_d <= `FALSE;
1873 
        else if (stall_f == `FALSE)
1874 
            valid_d <= valid_f & !kill_f;
1875 
        else if (stall_d == `FALSE)
1876 
            valid_d <= `FALSE;
1877 
        if (kill_x == `TRUE)
1878 
            valid_x <= `FALSE;
1879 
        else if (stall_d == `FALSE)
1880 
            valid_x <= valid_d & !kill_d;
1881 
        else if (stall_x == `FALSE)
1882 
            valid_x <= `FALSE;
1883 
        if (kill_m == `TRUE)
1884 
            valid_m <= `FALSE;
1885 
        else if (stall_x == `FALSE)
1886 
            valid_m <= valid_x & !kill_x;
1887 
        else if (stall_m == `FALSE)
1888 
            valid_m <= `FALSE;
1889 
        if (stall_m == `FALSE)
1890 
            valid_w <= valid_m & !kill_m;
1891 
        else
1892 
            valid_w <= `FALSE;
1893 
    end
1894 
end
1895 
 
1896 
// Microcode pipeline registers
1897 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1898 
begin
1899 
    if (rst_i == `TRUE)
1900 
    begin
1901 
`ifdef CFG_USER_ENABLED
1902 
        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
1903 
`endif
1904 
        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
1905 
        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
1906 
        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
1907 
        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
1908 
        x_result_sel_csr_x <= `FALSE;
1909 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1910 
        x_result_sel_mc_arith_x <= `FALSE;
1911 
`endif
1912 
`ifdef LM32_NO_BARREL_SHIFT
1913 
        x_result_sel_shift_x <= `FALSE;
1914 
`endif
1915 
`ifdef CFG_SIGN_EXTEND_ENABLED
1916 
        x_result_sel_sext_x <= `FALSE;
1917 
`endif
1918 
        x_result_sel_logic_x <= `FALSE;
1919 
`ifdef CFG_USER_ENABLED
1920 
        x_result_sel_user_x <= `FALSE;
1921 
`endif
1922 
        x_result_sel_add_x <= `FALSE;
1923 
        m_result_sel_compare_x <= `FALSE;
1924 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1925 
        m_result_sel_shift_x <= `FALSE;
1926 
`endif
1927 
        w_result_sel_load_x <= `FALSE;
1928 
`ifdef CFG_PL_MULTIPLY_ENABLED
1929 
        w_result_sel_mul_x <= `FALSE;
1930 
`endif
1931 
        x_bypass_enable_x <= `FALSE;
1932 
        m_bypass_enable_x <= `FALSE;
1933 
        write_enable_x <= `FALSE;
1934 
        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
1935 
        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
1936 
        load_x <= `FALSE;
1937 
        store_x <= `FALSE;
1938 
        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
1939 
        sign_extend_x <= `FALSE;
1940 
        adder_op_x <= `FALSE;
1941 
        adder_op_x_n <= `FALSE;
1942 
        logic_op_x <= 4'h0;
1943 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1944 
        direction_x <= `FALSE;
1945 
`endif
1946 
`ifdef CFG_ROTATE_ENABLED
1947 
        rotate_x <= `FALSE;
1948 
 
1949 
`endif
1950 
        branch_x <= `FALSE;
1951 
        condition_x <= `LM32_CONDITION_U1;
1952 
`ifdef CFG_DEBUG_ENABLED
1953 
        break_x <= `FALSE;
1954 
`endif
1955 
        scall_x <= `FALSE;
1956 
        eret_x <= `FALSE;
1957 
`ifdef CFG_DEBUG_ENABLED
1958 
        bret_x <= `FALSE;
1959 
`endif
1960 
`ifdef CFG_BUS_ERRORS_ENABLED
1961 
        bus_error_x <= `FALSE;
1962 
`endif
1963 
        csr_write_enable_x <= `FALSE;
1964 
        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
1965 
        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
1966 
        m_result_sel_compare_m <= `FALSE;
1967 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1968 
        m_result_sel_shift_m <= `FALSE;
1969 
`endif
1970 
        w_result_sel_load_m <= `FALSE;
1971 
`ifdef CFG_PL_MULTIPLY_ENABLED
1972 
        w_result_sel_mul_m <= `FALSE;
1973 
`endif
1974 
        m_bypass_enable_m <= `FALSE;
1975 
        branch_m <= `FALSE;
1976 
        exception_m <= `FALSE;
1977 
        load_m <= `FALSE;
1978 
        store_m <= `FALSE;
1979 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1980 
        direction_m <= `FALSE;
1981 
`endif
1982 
        write_enable_m <= `FALSE;
1983 
        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
1984 
        condition_met_m <= `FALSE;
1985 
`ifdef CFG_DCACHE_ENABLED
1986 
        dflush_m <= `FALSE;
1987 
`endif
1988 
`ifdef CFG_DEBUG_ENABLED
1989 
        debug_exception_m <= `FALSE;
1990 
        non_debug_exception_m <= `FALSE;
1991 
`endif
1992 
        operand_w <= {`LM32_WORD_WIDTH{1'b0}};
1993 
        w_result_sel_load_w <= `FALSE;
1994 
`ifdef CFG_PL_MULTIPLY_ENABLED
1995 
        w_result_sel_mul_w <= `FALSE;
1996 
`endif
1997 
        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
1998 
        write_enable_w <= `FALSE;
1999 
`ifdef CFG_DEBUG_ENABLED
2000 
        debug_exception_w <= `FALSE;
2001 
        non_debug_exception_w <= `FALSE;
2002 
`else
2003 
        exception_w <= `FALSE;
2004 
`endif
2005 
    end
2006 
    else
2007 
    begin
2008 
        // D/X stage registers
2009 
 
2010 
        if (stall_x == `FALSE)
2011 
        begin
2012 
`ifdef CFG_USER_ENABLED
2013 
            user_opcode <= user_opcode_d;
2014 
`endif
2015 
            operand_0_x <= d_result_0;
2016 
            operand_1_x <= d_result_1;
2017 
            store_operand_x <= bypass_data_1;
2018 
            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : pc_d + branch_offset_d;
2019 
            x_result_sel_csr_x <= x_result_sel_csr_d;
2020 
`ifdef LM32_MC_ARITHMETIC_ENABLED
2021 
            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2022 
`endif
2023 
`ifdef LM32_NO_BARREL_SHIFT
2024 
            x_result_sel_shift_x <= x_result_sel_shift_d;
2025 
`endif
2026 
`ifdef CFG_SIGN_EXTEND_ENABLED
2027 
            x_result_sel_sext_x <= x_result_sel_sext_d;
2028 
`endif
2029 
            x_result_sel_logic_x <= x_result_sel_logic_d;
2030 
`ifdef CFG_USER_ENABLED
2031 
            x_result_sel_user_x <= x_result_sel_user_d;
2032 
`endif
2033 
            x_result_sel_add_x <= x_result_sel_add_d;
2034 
            m_result_sel_compare_x <= m_result_sel_compare_d;
2035 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2036 
            m_result_sel_shift_x <= m_result_sel_shift_d;
2037 
`endif
2038 
            w_result_sel_load_x <= w_result_sel_load_d;
2039 
`ifdef CFG_PL_MULTIPLY_ENABLED
2040 
            w_result_sel_mul_x <= w_result_sel_mul_d;
2041 
`endif
2042 
            x_bypass_enable_x <= x_bypass_enable_d;
2043 
            m_bypass_enable_x <= m_bypass_enable_d;
2044 
            load_x <= load_d;
2045 
            store_x <= store_d;
2046 
            branch_x <= branch_d;
2047 
            write_idx_x <= write_idx_d;
2048 
            csr_x <= csr_d;
2049 
            size_x <= size_d;
2050 
            sign_extend_x <= sign_extend_d;
2051 
            adder_op_x <= adder_op_d;
2052 
            adder_op_x_n <= ~adder_op_d;
2053 
            logic_op_x <= logic_op_d;
2054 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2055 
            direction_x <= direction_d;
2056 
`endif
2057 
`ifdef CFG_ROTATE_ENABLED
2058 
            rotate_x <= rotate_d;
2059 
`endif
2060 
            condition_x <= condition_d;
2061 
            csr_write_enable_x <= csr_write_enable_d;
2062 
`ifdef CFG_DEBUG_ENABLED
2063 
            break_x <= break_d;
2064 
`endif
2065 
            scall_x <= scall_d;
2066 
`ifdef CFG_BUS_ERRORS_ENABLED
2067 
            bus_error_x <= bus_error_d;
2068 
`endif
2069 
            eret_x <= eret_d;
2070 
`ifdef CFG_DEBUG_ENABLED
2071 
            bret_x <= bret_d;
2072 
`endif
2073 
            write_enable_x <= write_enable_d;
2074 
        end
2075 
 
2076 
        // X/M stage registers
2077 
 
2078 
        if (stall_m == `FALSE)
2079 
        begin
2080 
            operand_m <= x_result;
2081 
            m_result_sel_compare_m <= m_result_sel_compare_x;
2082 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2083 
            m_result_sel_shift_m <= m_result_sel_shift_x;
2084 
`endif
2085 
            if (exception_x == `TRUE)
2086 
            begin
2087 
                w_result_sel_load_m <= `FALSE;
2088 
`ifdef CFG_PL_MULTIPLY_ENABLED
2089 
                w_result_sel_mul_m <= `FALSE;
2090 
`endif
2091 
            end
2092 
            else
2093 
            begin
2094 
                w_result_sel_load_m <= w_result_sel_load_x;
2095 
`ifdef CFG_PL_MULTIPLY_ENABLED
2096 
                w_result_sel_mul_m <= w_result_sel_mul_x;
2097 
`endif
2098 
            end
2099 
            m_bypass_enable_m <= m_bypass_enable_x;
2100 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2101 
            direction_m <= direction_x;
2102 
`endif
2103 
            load_m <= load_x;
2104 
            store_m <= store_x;
2105 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2106 
            branch_m <= branch_x && !branch_taken_x;
2107 
`else
2108 
            branch_m <= branch_x;
2109 
`endif
2110 
`ifdef CFG_DEBUG_ENABLED
2111 
            if (debug_exception_x == `TRUE)
2112 
                write_idx_m <= `LM32_BA_REG;
2113 
            else if (non_debug_exception_x == `TRUE)
2114 
                write_idx_m <= `LM32_EA_REG;
2115 
            else
2116 
                write_idx_m <= write_idx_x;
2117 
`else
2118 
            if (exception_x == `TRUE)
2119 
                write_idx_m <= `LM32_EA_REG;
2120 
            else
2121 
                write_idx_m <= write_idx_x;
2122 
`endif
2123 
            condition_met_m <= condition_met_x;
2124 
`ifdef CFG_DEBUG_ENABLED
2125 
            branch_target_m <= exception_x == `TRUE ? {(debug_exception_x == `TRUE) || (dc_re == `TRUE) ? deba : eba, eid_x, {3{1'b0}}} : branch_target_x;
2126 
`else
2127 
            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2128 
`endif
2129 
`ifdef CFG_TRACE_ENABLED
2130 
            eid_m <= eid_x;
2131 
`endif
2132 
`ifdef CFG_DCACHE_ENABLED
2133 
            dflush_m <= dflush_x;
2134 
`endif
2135 
            eret_m <= eret_q_x;
2136 
`ifdef CFG_DEBUG_ENABLED
2137 
            bret_m <= bret_q_x;
2138 
`endif
2139 
            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2140 
`ifdef CFG_DEBUG_ENABLED
2141 
            debug_exception_m <= debug_exception_x;
2142 
            non_debug_exception_m <= non_debug_exception_x;
2143 
`endif
2144 
        end
2145 
 
2146 
        // State changing regs
2147 
        if (stall_m == `FALSE)
2148 
        begin
2149 
            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2150 
                exception_m <= `TRUE;
2151 
            else
2152 
                exception_m <= `FALSE;
2153 
        end
2154 
 
2155 
        // M/W stage registers
2156 
 
2157 
        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2158 
        w_result_sel_load_w <= w_result_sel_load_m;
2159 
`ifdef CFG_PL_MULTIPLY_ENABLED
2160 
        w_result_sel_mul_w <= w_result_sel_mul_m;
2161 
`endif
2162 
        write_idx_w <= write_idx_m;
2163 
`ifdef CFG_TRACE_ENABLED
2164 
        eid_w <= eid_m;
2165 
        eret_w <= eret_m;
2166 
`ifdef CFG_DEBUG_ENABLED
2167 
        bret_w <= bret_m;
2168 
`endif
2169 
`endif
2170 
        write_enable_w <= write_enable_m;
2171 
`ifdef CFG_DEBUG_ENABLED
2172 
        debug_exception_w <= debug_exception_m;
2173 
        non_debug_exception_w <= non_debug_exception_m;
2174 
`else
2175 
        exception_w <= exception_m;
2176 
`endif
2177 
    end
2178 
end
2179 
 
2180 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2181 
// Buffer data read from register file, in case a stall occurs, and watch for
2182 
// any writes to the modified registers
2183 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2184 
begin
2185 
    if (rst_i == `TRUE)
2186 
    begin
2187 
        use_buf <= `FALSE;
2188 
        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2189 
        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2190 
    end
2191 
    else
2192 
    begin
2193 
        if (stall_d == `FALSE)
2194 
            use_buf <= `FALSE;
2195 
        else if (use_buf == `FALSE)
2196 
        begin
2197 
            reg_data_buf_0 <= reg_data_live_0;
2198 
            reg_data_buf_1 <= reg_data_live_1;
2199 
            use_buf <= `TRUE;
2200 
        end
2201 
        if (reg_write_enable_q_w == `TRUE)
2202 
        begin
2203 
            if (write_idx_w == read_idx_0_d)
2204 
                reg_data_buf_0 <= w_result;
2205 
            if (write_idx_w == read_idx_1_d)
2206 
                reg_data_buf_1 <= w_result;
2207 
        end
2208 
    end
2209 
end
2210 
`endif
2211 
 
2212 
`ifdef LM32_EBR_REGISTER_FILE
2213 
`else
2214 
// Register file write port
2215 
// Adding a reset causes a huge slowdown and requires lots of extra LUTs
2216 
always @(posedge clk_i)
2217 
begin
2218 
    if (reg_write_enable_q_w == `TRUE)
2219 
        registers[write_idx_w] <= w_result;
2220 
end
2221 
`endif
2222 
 
2223 
`ifdef CFG_TRACE_ENABLED
2224 
// PC tracing logic
2225 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2226 
begin
2227 
    if (rst_i == `TRUE)
2228 
    begin
2229 
        trace_pc_valid <= `FALSE;
2230 
        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2231 
        trace_exception <= `FALSE;
2232 
        trace_eid <= `LM32_EID_RESET;
2233 
        trace_eret <= `FALSE;
2234 
`ifdef CFG_DEBUG_ENABLED
2235 
        trace_bret <= `FALSE;
2236 
`endif
2237 
        pc_c <= `CFG_EBA_RESET/4;
2238 
    end
2239 
    else
2240 
    begin
2241 
        trace_pc_valid <= `FALSE;
2242 
 
2243 
        // Has an exception occured
2244 
`ifdef CFG_DEBUG_ENABLED
2245 
        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
2246 
`else
2247 
        if (exception_q_w == `TRUE)
2248 
`endif
2249 
        begin
2250 
            trace_exception <= `TRUE;
2251 
            trace_pc_valid <= `TRUE;
2252 
            trace_pc <= pc_w;
2253 
            trace_eid <= eid_w;
2254 
        end
2255 
        else
2256 
            trace_exception <= `FALSE;
2257 
 
2258 
        if ((valid_w == `TRUE) && (!kill_w))
2259 
        begin
2260 
            // An instruction is commiting. Determine if it is non-sequential
2261 
            if (pc_c + 1'b1 != pc_w)
2262 
            begin
2263 
                // Non-sequential instruction
2264 
                trace_pc_valid <= `TRUE;
2265 
                trace_pc <= pc_w;
2266 
            end
2267 
            // Record PC so we can determine if next instruction is sequential or not
2268 
            pc_c <= pc_w;
2269 
            // Indicate if it was an eret/bret instruction
2270 
            trace_eret <= eret_w;
2271 
`ifdef CFG_DEBUG_ENABLED
2272 
            trace_bret <= bret_w;
2273 
`endif
2274 
        end
2275 
        else
2276 
        begin
2277 
            trace_eret <= `FALSE;
2278 
`ifdef CFG_DEBUG_ENABLED
2279 
            trace_bret <= `FALSE;
2280 
`endif
2281 
        end
2282 
    end
2283 
end
2284 
`endif
2285 
 
2286 
/////////////////////////////////////////////////////
2287 
// Behavioural Logic
2288 
/////////////////////////////////////////////////////
2289 
 
2290 
// synthesis translate_off
2291 
 
2292 
// Reset register 0. Only needed for simulation.
2293 
initial
2294 
begin
2295 
`ifdef LM32_EBR_REGISTER_FILE
2296 
    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2297 
    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2298 
`else
2299 
    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
2300 
`endif
2301 
end
2302 
 
2303 
// synthesis translate_on
2304 
 
2305 
endmodule

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