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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_cpu.v] - Blame information for rev 48

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1 17 alirezamon 
// =============================================================================
2 
//                           COPYRIGHT NOTICE
3 
// Copyright 2006 (c) Lattice Semiconductor Corporation
4 
// ALL RIGHTS RESERVED
5 
// This confidential and proprietary software may be used only as authorised by
6 
// a licensing agreement from Lattice Semiconductor Corporation.
7 
// The entire notice above must be reproduced on all authorized copies and
8 
// copies may only be made to the extent permitted by a licensing agreement from
9 
// Lattice Semiconductor Corporation.
10 
//
11 
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
12 
// 5555 NE Moore Court                            408-826-6000 (other locations)
13 
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
14 
// U.S.A                                   email: techsupport@latticesemi.com
15 
// =============================================================================/
16 
//                         FILE DETAILS
17 
// Project          : LatticeMico32
18 
// File             : lm32_cpu.v
19 
// Title            : Top-level of CPU.
20 
// Dependencies     : lm32_include.v
21 
// Version          : 6.1.17
22 
// =============================================================================
23 
 
24 
`include "lm32_include.v"
25 
 
26 
/////////////////////////////////////////////////////
27 
// Module interface
28 
/////////////////////////////////////////////////////
29 
 
30 
module lm32_cpu (
31 
    // ----- Inputs -------
32 
    clk_i,
33 
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
34 
    clk_n_i,
35 
`endif
36 
    rst_i,
37 
    // From external devices
38 
`ifdef CFG_INTERRUPTS_ENABLED
39 
    interrupt_n,
40 
`endif
41 
    // From user logic
42 
`ifdef CFG_USER_ENABLED
43 
    user_result,
44 
    user_complete,
45 
`endif
46 
`ifdef CFG_JTAG_ENABLED
47 
    // From JTAG
48 
    jtag_clk,
49 
    jtag_update,
50 
    jtag_reg_q,
51 
    jtag_reg_addr_q,
52 
`endif
53 
`ifdef CFG_IWB_ENABLED
54 
    // Instruction Wishbone master
55 
    I_DAT_I,
56 
    I_ACK_I,
57 
    I_ERR_I,
58 
    I_RTY_I,
59 
`endif
60 
    // Data Wishbone master
61 
    D_DAT_I,
62 
    D_ACK_I,
63 
    D_ERR_I,
64 
    D_RTY_I,
65 
    // ----- Outputs -------
66 
`ifdef CFG_TRACE_ENABLED
67 
    trace_pc,
68 
    trace_pc_valid,
69 
    trace_exception,
70 
    trace_eid,
71 
    trace_eret,
72 
`ifdef CFG_DEBUG_ENABLED
73 
    trace_bret,
74 
`endif
75 
`endif
76 
`ifdef CFG_JTAG_ENABLED
77 
    jtag_reg_d,
78 
    jtag_reg_addr_d,
79 
`endif
80 
`ifdef CFG_USER_ENABLED
81 
    user_valid,
82 
    user_opcode,
83 
    user_operand_0,
84 
    user_operand_1,
85 
`endif
86 
`ifdef CFG_IWB_ENABLED
87 
    // Instruction Wishbone master
88 
    I_DAT_O,
89 
    I_ADR_O,
90 
    I_CYC_O,
91 
    I_SEL_O,
92 
    I_STB_O,
93 
    I_WE_O,
94 
    I_CTI_O,
95 
    I_LOCK_O,
96 
    I_BTE_O,
97 
`endif
98 
    // Data Wishbone master
99 
    D_DAT_O,
100 
    D_ADR_O,
101 
    D_CYC_O,
102 
    D_SEL_O,
103 
    D_STB_O,
104 
    D_WE_O,
105 
    D_CTI_O,
106 
    D_LOCK_O,
107 48 alirezamon 
    D_BTE_O,
108 
 
109 
    snoop_adr_i,
110 
    d_snoop_valid
111 
 
112 
 
113 17 alirezamon 
    );
114 
 
115 
/////////////////////////////////////////////////////
116 
// Parameters
117 
/////////////////////////////////////////////////////
118 
 
119 
parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
120 
`ifdef CFG_DEBUG_ENABLED
121 
parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
122 
`endif
123 
 
124 
`ifdef CFG_ICACHE_ENABLED
125 
parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
126 
parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
127 
parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
128 
parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
129 
parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
130 
`else
131 
parameter icache_associativity = 1;
132 
parameter icache_sets = 512;
133 
parameter icache_bytes_per_line = 16;
134 
parameter icache_base_address = 0;
135 
parameter icache_limit = 0;
136 
`endif
137 
 
138 
`ifdef CFG_DCACHE_ENABLED
139 
parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
140 
parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
141 
parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
142 
parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
143 
parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
144 
`else
145 
parameter dcache_associativity = 1;
146 
parameter dcache_sets = 512;
147 
parameter dcache_bytes_per_line = 16;
148 
parameter dcache_base_address = 0;
149 
parameter dcache_limit = 0;
150 
`endif
151 
 
152 
`ifdef CFG_DEBUG_ENABLED
153 
parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
154 
`else
155 
parameter watchpoints = 4'h0;
156 
`endif
157 
`ifdef CFG_ROM_DEBUG_ENABLED
158 
parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
159 
`else
160 
parameter breakpoints = 4'h0;
161 
`endif
162 
 
163 
`ifdef CFG_INTERRUPTS_ENABLED
164 
parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
165 
`else
166 
parameter interrupts = 0;
167 
`endif
168 
 
169 
/////////////////////////////////////////////////////
170 
// Inputs
171 
/////////////////////////////////////////////////////
172 
 
173 
input clk_i;                                    // Clock
174 
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
175 
input clk_n_i;                                  // Inverted clock
176 
`endif
177 
input rst_i;                                    // Reset
178 
 
179 
`ifdef CFG_INTERRUPTS_ENABLED
180 
input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
181 
`endif
182 
 
183 
`ifdef CFG_USER_ENABLED
184 
input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
185 
input user_complete;                            // User-defined instruction execution is complete
186 
`endif
187 
 
188 
`ifdef CFG_JTAG_ENABLED
189 
input jtag_clk;                                 // JTAG clock
190 
input jtag_update;                              // JTAG state machine is in data register update state
191 
input [`LM32_BYTE_RNG] jtag_reg_q;
192 
input [2:0] jtag_reg_addr_q;
193 
`endif
194 
 
195 
`ifdef CFG_IWB_ENABLED
196 
input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
197 
input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
198 
input I_ERR_I;                                  // Instruction Wishbone interface error
199 
input I_RTY_I;                                  // Instruction Wishbone interface retry
200 
`endif
201 
 
202 
input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
203 
input D_ACK_I;                                  // Data Wishbone interface acknowledgement
204 
input D_ERR_I;                                  // Data Wishbone interface error
205 
input D_RTY_I;                                  // Data Wishbone interface retry
206 
 
207 
/////////////////////////////////////////////////////
208 
// Outputs
209 
/////////////////////////////////////////////////////
210 
 
211 
`ifdef CFG_TRACE_ENABLED
212 
output [`LM32_PC_RNG] trace_pc;                 // PC to trace
213 
reg    [`LM32_PC_RNG] trace_pc;
214 
output trace_pc_valid;                          // Indicates that a new trace PC is valid
215 
reg    trace_pc_valid;
216 
output trace_exception;                         // Indicates an exception has occured
217 
reg    trace_exception;
218 
output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
219 
reg    [`LM32_EID_RNG] trace_eid;
220 
output trace_eret;                              // Indicates an eret instruction has been executed
221 
reg    trace_eret;
222 
`ifdef CFG_DEBUG_ENABLED
223 
output trace_bret;                              // Indicates a bret instruction has been executed
224 
reg    trace_bret;
225 
`endif
226 
`endif
227 
 
228 
`ifdef CFG_JTAG_ENABLED
229 
output [`LM32_BYTE_RNG] jtag_reg_d;
230 
wire   [`LM32_BYTE_RNG] jtag_reg_d;
231 
output [2:0] jtag_reg_addr_d;
232 
wire   [2:0] jtag_reg_addr_d;
233 
`endif
234 
 
235 
`ifdef CFG_USER_ENABLED
236 
output user_valid;                              // Indicates if user_opcode is valid
237 
wire   user_valid;
238 
output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
239 
reg    [`LM32_USER_OPCODE_RNG] user_opcode;
240 
output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
241 
wire   [`LM32_WORD_RNG] user_operand_0;
242 
output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
243 
wire   [`LM32_WORD_RNG] user_operand_1;
244 
`endif
245 
 
246 
`ifdef CFG_IWB_ENABLED
247 
output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
248 
wire   [`LM32_WORD_RNG] I_DAT_O;
249 
output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
250 
wire   [`LM32_WORD_RNG] I_ADR_O;
251 
output I_CYC_O;                                 // Instruction Wishbone interface cycle
252 
wire   I_CYC_O;
253 
output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
254 
wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
255 
output I_STB_O;                                 // Instruction Wishbone interface strobe
256 
wire   I_STB_O;
257 
output I_WE_O;                                  // Instruction Wishbone interface write enable
258 
wire   I_WE_O;
259 
output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type
260 
wire   [`LM32_CTYPE_RNG] I_CTI_O;
261 
output I_LOCK_O;                                // Instruction Wishbone interface lock bus
262 
wire   I_LOCK_O;
263 
output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type
264 
wire   [`LM32_BTYPE_RNG] I_BTE_O;
265 
`endif
266 
 
267 
output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
268 
wire   [`LM32_WORD_RNG] D_DAT_O;
269 
output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
270 
wire   [`LM32_WORD_RNG] D_ADR_O;
271 
output D_CYC_O;                                 // Data Wishbone interface cycle
272 
wire   D_CYC_O;
273 
output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
274 
wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
275 
output D_STB_O;                                 // Data Wishbone interface strobe
276 
wire   D_STB_O;
277 
output D_WE_O;                                  // Data Wishbone interface write enable
278 
wire   D_WE_O;
279 
output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type
280 
wire   [`LM32_CTYPE_RNG] D_CTI_O;
281 
output D_LOCK_O;                                // Date Wishbone interface lock bus
282 
wire   D_LOCK_O;
283 
output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type
284 
wire   [`LM32_BTYPE_RNG] D_BTE_O;
285 
 
286 48 alirezamon 
 
287 
input [31:0]          snoop_adr_i;
288 
input d_snoop_valid;
289 
 
290 17 alirezamon 
/////////////////////////////////////////////////////
291 
// Internal nets and registers
292 
/////////////////////////////////////////////////////
293 
 
294 
// Pipeline registers
295 
 
296 
`ifdef LM32_CACHE_ENABLED
297 
reg valid_a;                                    // Instruction in A stage is valid
298 
`endif
299 
reg valid_f;                                    // Instruction in F stage is valid
300 
reg valid_d;                                    // Instruction in D stage is valid
301 
reg valid_x;                                    // Instruction in X stage is valid
302 
reg valid_m;                                    // Instruction in M stage is valid
303 
reg valid_w;                                    // Instruction in W stage is valid
304 
 
305 
wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
306 
wire load_d;                                    // Indicates a load instruction
307 
reg load_x;
308 
reg load_m;
309 
wire store_d;                                   // Indicates a store instruction
310 
reg store_x;
311 
reg store_m;
312 
wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
313 
reg [`LM32_SIZE_RNG] size_x;
314 
wire branch_d;                                  // Indicates a branch instruction
315 
reg branch_x;
316 
reg branch_m;
317 
wire branch_reg_d;                              // Branch to register or immediate
318 
wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
319 
reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
320 
reg [`LM32_PC_RNG] branch_target_m;
321 
wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
322 
wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
323 
 
324 
wire x_result_sel_csr_d;                        // Select X stage result from CSRs
325 
reg x_result_sel_csr_x;
326 
`ifdef LM32_MC_ARITHMETIC_ENABLED
327 
wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
328 
reg x_result_sel_mc_arith_x;
329 
`endif
330 
`ifdef LM32_NO_BARREL_SHIFT
331 
wire x_result_sel_shift_d;                      // Select X stage result from shifter
332 
reg x_result_sel_shift_x;
333 
`endif
334 
`ifdef CFG_SIGN_EXTEND_ENABLED
335 
wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
336 
reg x_result_sel_sext_x;
337 
`endif
338 
wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
339 
reg x_result_sel_logic_x;
340 
`ifdef CFG_USER_ENABLED
341 
wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
342 
reg x_result_sel_user_x;
343 
`endif
344 
wire x_result_sel_add_d;                        // Select X stage result from adder
345 
reg x_result_sel_add_x;
346 
wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
347 
reg m_result_sel_compare_x;
348 
reg m_result_sel_compare_m;
349 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
350 
wire m_result_sel_shift_d;                      // Select M stage result from shifter
351 
reg m_result_sel_shift_x;
352 
reg m_result_sel_shift_m;
353 
`endif
354 
wire w_result_sel_load_d;                       // Select W stage result from load/store unit
355 
reg w_result_sel_load_x;
356 
reg w_result_sel_load_m;
357 
reg w_result_sel_load_w;
358 
`ifdef CFG_PL_MULTIPLY_ENABLED
359 
wire w_result_sel_mul_d;                        // Select W stage result from multiplier
360 
reg w_result_sel_mul_x;
361 
reg w_result_sel_mul_m;
362 
reg w_result_sel_mul_w;
363 
`endif
364 
wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
365 
reg x_bypass_enable_x;
366 
wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
367 
reg m_bypass_enable_x;
368 
reg m_bypass_enable_m;
369 
wire sign_extend_d;                             // Whether to sign-extend or zero-extend
370 
reg sign_extend_x;
371 
wire write_enable_d;                            // Register file write enable
372 
reg write_enable_x;
373 
wire write_enable_q_x;
374 
reg write_enable_m;
375 
wire write_enable_q_m;
376 
reg write_enable_w;
377 
wire write_enable_q_w;
378 
wire read_enable_0_d;                           // Register file read enable 0
379 
wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
380 
wire read_enable_1_d;                           // Register file read enable 1
381 
wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
382 
wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
383 
reg [`LM32_REG_IDX_RNG] write_idx_x;
384 
reg [`LM32_REG_IDX_RNG] write_idx_m;
385 
reg [`LM32_REG_IDX_RNG] write_idx_w;
386 
wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
387 
reg  [`LM32_CSR_RNG] csr_x;
388 
wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
389 
reg [`LM32_CONDITION_RNG] condition_x;
390 
`ifdef CFG_DEBUG_ENABLED
391 
wire break_d;                                   // Indicates a break instruction
392 
reg break_x;
393 
`endif
394 
wire scall_d;                                   // Indicates a scall instruction
395 
reg scall_x;
396 
wire eret_d;                                    // Indicates an eret instruction
397 
reg eret_x;
398 
wire eret_q_x;
399 
reg eret_m;
400 
`ifdef CFG_TRACE_ENABLED
401 
reg eret_w;
402 
`endif
403 
`ifdef CFG_DEBUG_ENABLED
404 
wire bret_d;                                    // Indicates a bret instruction
405 
reg bret_x;
406 
wire bret_q_x;
407 
reg bret_m;
408 
`ifdef CFG_TRACE_ENABLED
409 
reg bret_w;
410 
`endif
411 
`endif
412 
wire csr_write_enable_d;                        // CSR write enable
413 
reg csr_write_enable_x;
414 
wire csr_write_enable_q_x;
415 
`ifdef CFG_USER_ENABLED
416 
wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
417 
`endif
418 
 
419 
`ifdef CFG_BUS_ERRORS_ENABLED
420 
wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
421 
reg bus_error_x;
422 
`endif
423 
 
424 
reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
425 
reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
426 
reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
427 
reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
428 
reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
429 
 
430 
reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
431 
reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
432 
reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
433 
reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
434 
reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
435 
 
436 
// To/from register file
437 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
438 
wire [`LM32_WORD_RNG] reg_data_live_0;
439 
wire [`LM32_WORD_RNG] reg_data_live_1;
440 
reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
441 
reg [`LM32_WORD_RNG] reg_data_buf_0;
442 
reg [`LM32_WORD_RNG] reg_data_buf_1;
443 
`endif
444 
`ifdef LM32_EBR_REGISTER_FILE
445 
`else
446 
reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
447 
`endif
448 
wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data
449 
wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
450 
reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
451 
reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
452 
wire reg_write_enable_q_w;
453 
 
454 
reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
455 
 
456 
wire stall_a;                                   // Stall instruction in A pipeline stage
457 
wire stall_f;                                   // Stall instruction in F pipeline stage
458 
wire stall_d;                                   // Stall instruction in D pipeline stage
459 
wire stall_x;                                   // Stall instruction in X pipeline stage
460 
wire stall_m;                                   // Stall instruction in M pipeline stage
461 
 
462 
// To/from adder
463 
wire adder_op_d;                                // Whether to add or subtract
464 
reg adder_op_x;
465 
reg adder_op_x_n;                               // Inverted version of adder_op_x
466 
wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
467 
wire adder_overflow_x;                          // Whether a signed overflow occured
468 
wire adder_carry_n_x;                           // Whether a carry was generated
469 
 
470 
// To/from logical operations unit
471 
wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
472 
reg [`LM32_LOGIC_OP_RNG] logic_op_x;
473 
wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
474 
 
475 
`ifdef CFG_SIGN_EXTEND_ENABLED
476 
// From sign-extension unit
477 
wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
478 
wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
479 
wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
480 
`endif
481 
 
482 
// To/from shifter
483 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
484 
`ifdef CFG_ROTATE_ENABLED
485 
wire rotate_d;                                  // Whether we should rotate or shift
486 
reg rotate_x;
487 
`endif
488 
wire direction_d;                               // Which direction to shift in
489 
reg direction_x;
490 
reg direction_m;
491 
wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
492 
`endif
493 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
494 
wire shift_left_d;                              // Indicates whether to perform a left shift or not
495 
wire shift_left_q_d;
496 
wire shift_right_d;                             // Indicates whether to perform a right shift or not
497 
wire shift_right_q_d;
498 
`endif
499 
`ifdef LM32_NO_BARREL_SHIFT
500 
wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
501 
`endif
502 
 
503 
// To/from multiplier
504 
`ifdef LM32_MULTIPLY_ENABLED
505 
wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
506 
`endif
507 
`ifdef CFG_MC_MULTIPLY_ENABLED
508 
wire multiply_d;                                // Indicates whether to perform a multiply or not
509 
wire multiply_q_d;
510 
`endif
511 
 
512 
// To/from divider
513 
`ifdef CFG_MC_DIVIDE_ENABLED
514 
wire divide_d;                                  // Indicates whether to perform a divider or not
515 
wire divide_q_d;
516 
wire modulus_d;
517 
wire modulus_q_d;
518 
wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
519 
`endif
520 
 
521 
// To from multi-cycle arithmetic unit
522 
`ifdef LM32_MC_ARITHMETIC_ENABLED
523 
wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
524 
wire [`LM32_WORD_RNG] mc_result_x;
525 
`endif
526 
 
527 
// From CSRs
528 
`ifdef CFG_INTERRUPTS_ENABLED
529 
wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
530 
`endif
531 
wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
532 
`ifdef CFG_CYCLE_COUNTER_ENABLED
533 
reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
534 
`endif
535 
reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
536 
 
537 
// To/from instruction unit
538 
wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
539 
wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
540 
wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
541 
wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
542 
wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
543 
`ifdef CFG_TRACE_ENABLED
544 
reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
545 
`endif
546 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
547 
wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
548 
`endif
549 
wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
550 
`ifdef CFG_ICACHE_ENABLED
551 
wire iflush;                                    // Flush instruction cache
552 
wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
553 
wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
554 
wire icache_refill_request;                     // Request to refill instruction cache
555 
wire icache_refilling;                          // Indicates the instruction cache is being refilled
556 
`endif
557 
 
558 
// To/from load/store unit
559 
`ifdef CFG_DCACHE_ENABLED
560 
wire dflush_x;                                  // Flush data cache
561 
reg dflush_m;
562 
wire dcache_stall_request;                      // Stall pipeline because data cache is busy
563 
wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
564 
wire dcache_refill_request;                     // Request to refill data cache
565 
wire dcache_refilling;                          // Indicates the data cache is being refilled
566 
`endif
567 
wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
568 
wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
569 
 
570 
// To/from JTAG interface
571 
`ifdef CFG_JTAG_ENABLED
572 
`ifdef CFG_JTAG_UART_ENABLED
573 
wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
574 
wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
575 
`endif
576 
`ifdef CFG_HW_DEBUG_ENABLED
577 
wire jtag_csr_write_enable;                     // Debugger CSR write enable
578 
wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
579 
wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
580 
wire jtag_read_enable;
581 
wire [`LM32_BYTE_RNG] jtag_read_data;
582 
wire jtag_write_enable;
583 
wire [`LM32_BYTE_RNG] jtag_write_data;
584 
wire [`LM32_WORD_RNG] jtag_address;
585 
wire jtag_access_complete;
586 
`endif
587 
`ifdef CFG_DEBUG_ENABLED
588 
wire jtag_break;                                // Request from debugger to raise a breakpoint
589 
`endif
590 
`endif
591 
 
592 
// Hazzard detection
593 
wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
594 
wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
595 
wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
596 
wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
597 
wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
598 
wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
599 
 
600 
// Control flow
601 
wire cmp_zero;                                  // Result of comparison is zero
602 
wire cmp_negative;                              // Result of comparison is negative
603 
wire cmp_overflow;                              // Comparison produced an overflow
604 
wire cmp_carry_n;                               // Comparison produced a carry, inverted
605 
reg condition_met_x;                            // Condition of branch instruction is met
606 
reg condition_met_m;
607 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
608 
wire branch_taken_x;                            // Branch is taken in X stage
609 
`endif
610 
wire branch_taken_m;                            // Branch is taken in M stage
611 
 
612 
wire kill_f;                                    // Kill instruction in F stage
613 
wire kill_d;                                    // Kill instruction in D stage
614 
wire kill_x;                                    // Kill instruction in X stage
615 
wire kill_m;                                    // Kill instruction in M stage
616 
wire kill_w;                                    // Kill instruction in W stage
617 
 
618 
reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
619 
`ifdef CFG_DEBUG_ENABLED
620 
reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
621 
`endif
622 
reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
623 
`ifdef CFG_TRACE_ENABLED
624 
reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
625 
reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
626 
`endif
627 
 
628 
`ifdef CFG_DEBUG_ENABLED
629 
`ifdef LM32_SINGLE_STEP_ENABLED
630 
wire dc_ss;                                     // Is single-step enabled
631 
`endif
632 
wire dc_re;                                     // Remap all exceptions
633 
wire exception_x;                               // An exception occured in the X stage
634 
reg exception_m;                                // An instruction that caused an exception is in the M stage
635 
wire debug_exception_x;                         // Indicates if a debug exception has occured
636 
reg debug_exception_m;
637 
reg debug_exception_w;
638 
wire debug_exception_q_w;
639 
wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
640 
reg non_debug_exception_m;
641 
reg non_debug_exception_w;
642 
wire non_debug_exception_q_w;
643 
`else
644 
wire exception_x;                               // Indicates if a debug exception has occured
645 
reg exception_m;
646 
reg exception_w;
647 
wire exception_q_w;
648 
`endif
649 
 
650 
`ifdef CFG_DEBUG_ENABLED
651 
`ifdef CFG_JTAG_ENABLED
652 
wire reset_exception;                           // Indicates if a reset exception has occured
653 
`endif
654 
`endif
655 
`ifdef CFG_INTERRUPTS_ENABLED
656 
wire interrupt_exception;                       // Indicates if an interrupt exception has occured
657 
`endif
658 
`ifdef CFG_DEBUG_ENABLED
659 
wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
660 
wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
661 
`endif
662 
`ifdef CFG_BUS_ERRORS_ENABLED
663 
wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
664 
wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
665 
`endif
666 
`ifdef CFG_MC_DIVIDE_ENABLED
667 
wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
668 
`endif
669 
wire system_call_exception;                     // Indicates if a system call exception has occured
670 
 
671 
`ifdef CFG_BUS_ERRORS_ENABLED
672 
reg data_bus_error_seen;                        // Indicates if a data bus error was seen
673 
`endif
674 
 
675 
/////////////////////////////////////////////////////
676 
// Functions
677 
/////////////////////////////////////////////////////
678 
`define  INCLUDE_FUNCTION
679 
`include "lm32_functions.v"
680 
 
681 
/////////////////////////////////////////////////////
682 
// Instantiations
683 
/////////////////////////////////////////////////////
684 
 
685 
// Instruction unit
686 
lm32_instruction_unit #(
687 
    .associativity          (icache_associativity),
688 
    .sets                   (icache_sets),
689 
    .bytes_per_line         (icache_bytes_per_line),
690 
    .base_address           (icache_base_address),
691 
    .limit                  (icache_limit)
692 
  ) instruction_unit (
693 
    // ----- Inputs -------
694 
    .clk_i                  (clk_i),
695 
    .rst_i                  (rst_i),
696 
    // From pipeline
697 
    .stall_a                (stall_a),
698 
    .stall_f                (stall_f),
699 
    .stall_d                (stall_d),
700 
    .stall_x                (stall_x),
701 
    .stall_m                (stall_m),
702 
    .valid_f                (valid_f),
703 
    .kill_f                 (kill_f),
704 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
705 
    .branch_taken_x         (branch_taken_x),
706 
    .branch_target_x        (branch_target_x),
707 
`endif
708 
    .branch_taken_m         (branch_taken_m),
709 
    .branch_target_m        (branch_target_m),
710 
`ifdef CFG_ICACHE_ENABLED
711 
    .iflush                 (iflush),
712 
`endif
713 
`ifdef CFG_DCACHE_ENABLED
714 
    .dcache_restart_request (dcache_restart_request),
715 
    .dcache_refill_request  (dcache_refill_request),
716 
    .dcache_refilling       (dcache_refilling),
717 
`endif
718 
`ifdef CFG_IWB_ENABLED
719 
    // From Wishbone
720 
    .i_dat_i                (I_DAT_I),
721 
    .i_ack_i                (I_ACK_I),
722 
    .i_err_i                (I_ERR_I),
723 
    .i_rty_i                (I_RTY_I),
724 
`endif
725 
`ifdef CFG_HW_DEBUG_ENABLED
726 
    .jtag_read_enable       (jtag_read_enable),
727 
    .jtag_write_enable      (jtag_write_enable),
728 
    .jtag_write_data        (jtag_write_data),
729 
    .jtag_address           (jtag_address),
730 
`endif
731 
    // ----- Outputs -------
732 
    // To pipeline
733 
    .pc_f                   (pc_f),
734 
    .pc_d                   (pc_d),
735 
    .pc_x                   (pc_x),
736 
    .pc_m                   (pc_m),
737 
    .pc_w                   (pc_w),
738 
`ifdef CFG_ICACHE_ENABLED
739 
    .icache_stall_request   (icache_stall_request),
740 
    .icache_restart_request (icache_restart_request),
741 
    .icache_refill_request  (icache_refill_request),
742 
    .icache_refilling       (icache_refilling),
743 
`endif
744 
`ifdef CFG_IWB_ENABLED
745 
    // To Wishbone
746 
    .i_dat_o                (I_DAT_O),
747 
    .i_adr_o                (I_ADR_O),
748 
    .i_cyc_o                (I_CYC_O),
749 
    .i_sel_o                (I_SEL_O),
750 
    .i_stb_o                (I_STB_O),
751 
    .i_we_o                 (I_WE_O),
752 
    .i_cti_o                (I_CTI_O),
753 
    .i_lock_o               (I_LOCK_O),
754 
    .i_bte_o                (I_BTE_O),
755 
`endif
756 
`ifdef CFG_HW_DEBUG_ENABLED
757 
    .jtag_read_data         (jtag_read_data),
758 
    .jtag_access_complete   (jtag_access_complete),
759 
`endif
760 
`ifdef CFG_BUS_ERRORS_ENABLED
761 
    .bus_error_d            (bus_error_d),
762 
`endif
763 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
764 
    .instruction_f          (instruction_f),
765 
`endif
766 
    .instruction_d          (instruction_d)
767 
    );
768 
 
769 
// Trace instructions in simulation
770 
lm32_simtrace simtrace (
771 
    .clk_i                  (clk_i),
772 
    .rst_i                  (rst_i),
773 
    .stall_x                (stall_x),
774 
    .stall_m                (stall_m),
775 
    .valid_w                (valid_w),
776 
    .kill_w                 (kill_w),
777 
    .instruction_d          (instruction_d),
778 
    .pc_w                   (pc_w)
779 
    );
780 
 
781 
// Instruction decoder
782 
lm32_decoder decoder (
783 
    // ----- Inputs -------
784 
    .instruction            (instruction_d),
785 
    // ----- Outputs -------
786 
    .d_result_sel_0         (d_result_sel_0_d),
787 
    .d_result_sel_1         (d_result_sel_1_d),
788 
    .x_result_sel_csr       (x_result_sel_csr_d),
789 
`ifdef LM32_MC_ARITHMETIC_ENABLED
790 
    .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
791 
`endif
792 
`ifdef LM32_NO_BARREL_SHIFT
793 
    .x_result_sel_shift     (x_result_sel_shift_d),
794 
`endif
795 
`ifdef CFG_SIGN_EXTEND_ENABLED
796 
    .x_result_sel_sext      (x_result_sel_sext_d),
797 
`endif
798 
    .x_result_sel_logic     (x_result_sel_logic_d),
799 
`ifdef CFG_USER_ENABLED
800 
    .x_result_sel_user      (x_result_sel_user_d),
801 
`endif
802 
    .x_result_sel_add       (x_result_sel_add_d),
803 
    .m_result_sel_compare   (m_result_sel_compare_d),
804 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
805 
    .m_result_sel_shift     (m_result_sel_shift_d),
806 
`endif
807 
    .w_result_sel_load      (w_result_sel_load_d),
808 
`ifdef CFG_PL_MULTIPLY_ENABLED
809 
    .w_result_sel_mul       (w_result_sel_mul_d),
810 
`endif
811 
    .x_bypass_enable        (x_bypass_enable_d),
812 
    .m_bypass_enable        (m_bypass_enable_d),
813 
    .read_enable_0          (read_enable_0_d),
814 
    .read_idx_0             (read_idx_0_d),
815 
    .read_enable_1          (read_enable_1_d),
816 
    .read_idx_1             (read_idx_1_d),
817 
    .write_enable           (write_enable_d),
818 
    .write_idx              (write_idx_d),
819 
    .immediate              (immediate_d),
820 
    .branch_offset          (branch_offset_d),
821 
    .load                   (load_d),
822 
    .store                  (store_d),
823 
    .size                   (size_d),
824 
    .sign_extend            (sign_extend_d),
825 
    .adder_op               (adder_op_d),
826 
    .logic_op               (logic_op_d),
827 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
828 
    .direction              (direction_d),
829 
`endif
830 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
831 
    .shift_left             (shift_left_d),
832 
    .shift_right            (shift_right_d),
833 
`endif
834 
`ifdef CFG_MC_MULTIPLY_ENABLED
835 
    .multiply               (multiply_d),
836 
`endif
837 
`ifdef CFG_MC_DIVIDE_ENABLED
838 
    .divide                 (divide_d),
839 
    .modulus                (modulus_d),
840 
`endif
841 
    .branch                 (branch_d),
842 
    .branch_reg             (branch_reg_d),
843 
    .condition              (condition_d),
844 
`ifdef CFG_DEBUG_ENABLED
845 
    .break                  (break_d),
846 
`endif
847 
    .scall                  (scall_d),
848 
    .eret                   (eret_d),
849 
`ifdef CFG_DEBUG_ENABLED
850 
    .bret                   (bret_d),
851 
`endif
852 
`ifdef CFG_USER_ENABLED
853 
    .user_opcode            (user_opcode_d),
854 
`endif
855 
    .csr_write_enable       (csr_write_enable_d)
856 
    );
857 
wire load_q_x,load_q_m,store_q_m;
858 
 
859 
// Load/store unit
860 
lm32_load_store_unit #(
861 
    .associativity          (dcache_associativity),
862 
    .sets                   (dcache_sets),
863 
    .bytes_per_line         (dcache_bytes_per_line),
864 
    .base_address           (dcache_base_address),
865 
    .limit                  (dcache_limit)
866 
  ) load_store_unit (
867 
    // ----- Inputs -------
868 
    .clk_i                  (clk_i),
869 
    .rst_i                  (rst_i),
870 
    // From pipeline
871 
    .stall_a                (stall_a),
872 
    .stall_x                (stall_x),
873 
    .stall_m                (stall_m),
874 
    .kill_x                 (kill_x),
875 
    .kill_m                 (kill_m),
876 
    .exception_m            (exception_m),
877 
    .store_operand_x        (store_operand_x),
878 
    .load_store_address_x   (adder_result_x),
879 
    .load_store_address_m   (operand_m),
880 
    .load_store_address_w   (operand_w[1:0]),
881 
    .load_q_x               (load_q_x),
882 
    .load_q_m               (load_q_m),
883 
    .store_q_m              (store_q_m),
884 
    .sign_extend_x          (sign_extend_x),
885 
    .size_x                 (size_x),
886 
`ifdef CFG_DCACHE_ENABLED
887 
    .dflush                 (dflush_m),
888 
`endif
889 
    // From Wishbone
890 
    .d_dat_i                (D_DAT_I),
891 
    .d_ack_i                (D_ACK_I),
892 
    .d_err_i                (D_ERR_I),
893 
    .d_rty_i                (D_RTY_I),
894 
    // ----- Outputs -------
895 
    // To pipeline
896 
`ifdef CFG_DCACHE_ENABLED
897 
    .dcache_refill_request  (dcache_refill_request),
898 
    .dcache_restart_request (dcache_restart_request),
899 
    .dcache_stall_request   (dcache_stall_request),
900 
    .dcache_refilling       (dcache_refilling),
901 
`endif
902 
    .load_data_w            (load_data_w),
903 
    .stall_wb_load          (stall_wb_load),
904 
    // To Wishbone
905 
    .d_dat_o                (D_DAT_O),
906 
    .d_adr_o                (D_ADR_O),
907 
    .d_cyc_o                (D_CYC_O),
908 
    .d_sel_o                (D_SEL_O),
909 
    .d_stb_o                (D_STB_O),
910 
    .d_we_o                 (D_WE_O),
911 
    .d_cti_o                (D_CTI_O),
912 
    .d_lock_o               (D_LOCK_O),
913 48 alirezamon 
    .d_bte_o                (D_BTE_O),
914 
 
915 
    .snoop_adr_i            (snoop_adr_i),
916 
    .d_snoop_valid          (d_snoop_valid)
917 
 
918 17 alirezamon 
    );
919 
 
920 
// Adder
921 
lm32_adder adder (
922 
    // ----- Inputs -------
923 
    .adder_op_x             (adder_op_x),
924 
    .adder_op_x_n           (adder_op_x_n),
925 
    .operand_0_x            (operand_0_x),
926 
    .operand_1_x            (operand_1_x),
927 
    // ----- Outputs -------
928 
    .adder_result_x         (adder_result_x),
929 
    .adder_carry_n_x        (adder_carry_n_x),
930 
    .adder_overflow_x       (adder_overflow_x)
931 
    );
932 
 
933 
// Logic operations
934 
lm32_logic_op logic_op (
935 
    // ----- Inputs -------
936 
    .logic_op_x             (logic_op_x),
937 
    .operand_0_x            (operand_0_x),
938 
 
939 
    .operand_1_x            (operand_1_x),
940 
    // ----- Outputs -------
941 
    .logic_result_x         (logic_result_x)
942 
    );
943 
 
944 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
945 
// Pipelined barrel-shifter
946 
lm32_shifter shifter (
947 
    // ----- Inputs -------
948 
    .clk_i                  (clk_i),
949 
    .rst_i                  (rst_i),
950 
    .stall_x                (stall_x),
951 
    .direction_x            (direction_x),
952 
    .sign_extend_x          (sign_extend_x),
953 
    .operand_0_x            (operand_0_x),
954 
    .operand_1_x            (operand_1_x),
955 
    // ----- Outputs -------
956 
    .shifter_result_m       (shifter_result_m)
957 
    );
958 
`endif
959 
 
960 
`ifdef CFG_PL_MULTIPLY_ENABLED
961 
// Pipeline fixed-point multiplier
962 
lm32_multiplier multiplier (
963 
    // ----- Inputs -------
964 
    .clk_i                  (clk_i),
965 
    .rst_i                  (rst_i),
966 
    .stall_x                (stall_x),
967 
    .stall_m                (stall_m),
968 
    .operand_0              (d_result_0),
969 
    .operand_1              (d_result_1),
970 
    // ----- Outputs -------
971 
    .result                 (multiplier_result_w)
972 
    );
973 
`endif
974 
 
975 
`ifdef LM32_MC_ARITHMETIC_ENABLED
976 
// Multi-cycle arithmetic
977 
lm32_mc_arithmetic mc_arithmetic (
978 
    // ----- Inputs -------
979 
    .clk_i                  (clk_i),
980 
    .rst_i                  (rst_i),
981 
    .stall_d                (stall_d),
982 
    .kill_x                 (kill_x),
983 
`ifdef CFG_MC_DIVIDE_ENABLED
984 
    .divide_d               (divide_q_d),
985 
    .modulus_d              (modulus_q_d),
986 
`endif
987 
`ifdef CFG_MC_MULTIPLY_ENABLED
988 
    .multiply_d             (multiply_q_d),
989 
`endif
990 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
991 
    .shift_left_d           (shift_left_q_d),
992 
    .shift_right_d          (shift_right_q_d),
993 
    .sign_extend_d          (sign_extend_d),
994 
`endif
995 
    .operand_0_d            (d_result_0),
996 
    .operand_1_d            (d_result_1),
997 
    // ----- Outputs -------
998 
    .result_x               (mc_result_x),
999 
`ifdef CFG_MC_DIVIDE_ENABLED
1000 
    .divide_by_zero_x       (divide_by_zero_x),
1001 
`endif
1002 
    .stall_request_x        (mc_stall_request_x)
1003 
    );
1004 
`endif
1005 
 
1006 
`ifdef CFG_INTERRUPTS_ENABLED
1007 
// Interrupt unit
1008 
lm32_interrupt interrupt (
1009 
    // ----- Inputs -------
1010 
    .clk_i                  (clk_i),
1011 
    .rst_i                  (rst_i),
1012 
    // From external devices
1013 
    .interrupt_n            (interrupt_n),
1014 
    // From pipeline
1015 
    .stall_x                (stall_x),
1016 
`ifdef CFG_DEBUG_ENABLED
1017 
    .non_debug_exception    (non_debug_exception_q_w),
1018 
    .debug_exception        (debug_exception_q_w),
1019 
`else
1020 
    .exception              (exception_q_w),
1021 
`endif
1022 
    .eret_q_x               (eret_q_x),
1023 
`ifdef CFG_DEBUG_ENABLED
1024 
    .bret_q_x               (bret_q_x),
1025 
`endif
1026 
    .csr                    (csr_x),
1027 
    .csr_write_data         (operand_1_x),
1028 
    .csr_write_enable       (csr_write_enable_q_x),
1029 
    // ----- Outputs -------
1030 
    .interrupt_exception    (interrupt_exception),
1031 
    // To pipeline
1032 
    .csr_read_data          (interrupt_csr_read_data_x)
1033 
    );
1034 
`endif
1035 
 
1036 
`ifdef CFG_JTAG_ENABLED
1037 
// JTAG interface
1038 
lm32_jtag jtag (
1039 
    // ----- Inputs -------
1040 
    .clk_i                  (clk_i),
1041 
    .rst_i                  (rst_i),
1042 
    // From JTAG
1043 
    .jtag_clk               (jtag_clk),
1044 
    .jtag_update            (jtag_update),
1045 
    .jtag_reg_q             (jtag_reg_q),
1046 
    .jtag_reg_addr_q        (jtag_reg_addr_q),
1047 
    // From pipeline
1048 
`ifdef CFG_JTAG_UART_ENABLED
1049 
    .csr                    (csr_x),
1050 
    .csr_write_data         (operand_1_x),
1051 
    .csr_write_enable       (csr_write_enable_q_x),
1052 
    .stall_x                (stall_x),
1053 
`endif
1054 
`ifdef CFG_HW_DEBUG_ENABLED
1055 
    .jtag_read_data         (jtag_read_data),
1056 
    .jtag_access_complete   (jtag_access_complete),
1057 
`endif
1058 
`ifdef CFG_DEBUG_ENABLED
1059 
    .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
1060 
`endif
1061 
    // ----- Outputs -------
1062 
    // To pipeline
1063 
`ifdef CFG_JTAG_UART_ENABLED
1064 
    .jtx_csr_read_data      (jtx_csr_read_data),
1065 
    .jrx_csr_read_data      (jrx_csr_read_data),
1066 
`endif
1067 
`ifdef CFG_HW_DEBUG_ENABLED
1068 
    .jtag_csr_write_enable  (jtag_csr_write_enable),
1069 
    .jtag_csr_write_data    (jtag_csr_write_data),
1070 
    .jtag_csr               (jtag_csr),
1071 
    .jtag_read_enable       (jtag_read_enable),
1072 
    .jtag_write_enable      (jtag_write_enable),
1073 
    .jtag_write_data        (jtag_write_data),
1074 
    .jtag_address           (jtag_address),
1075 
`endif
1076 
`ifdef CFG_DEBUG_ENABLED
1077 
    .jtag_break             (jtag_break),
1078 
    .jtag_reset             (reset_exception),
1079 
`endif
1080 
    // To JTAG
1081 
    .jtag_reg_d             (jtag_reg_d),
1082 
    .jtag_reg_addr_d        (jtag_reg_addr_d)
1083 
    );
1084 
`endif
1085 
 
1086 
`ifdef CFG_DEBUG_ENABLED
1087 
// Debug unit
1088 
lm32_debug #(
1089 
    .breakpoints            (breakpoints),
1090 
    .watchpoints            (watchpoints)
1091 
  ) hw_debug (
1092 
    // ----- Inputs -------
1093 
    .clk_i                  (clk_i),
1094 
    .rst_i                  (rst_i),
1095 
    .pc_x                   (pc_x),
1096 
    .load_x                 (load_x),
1097 
    .store_x                (store_x),
1098 
    .load_store_address_x   (adder_result_x),
1099 
    .csr_write_enable_x     (csr_write_enable_q_x),
1100 
    .csr_write_data         (operand_1_x),
1101 
    .csr_x                  (csr_x),
1102 
`ifdef CFG_HW_DEBUG_ENABLED
1103 
    .jtag_csr_write_enable  (jtag_csr_write_enable),
1104 
    .jtag_csr_write_data    (jtag_csr_write_data),
1105 
    .jtag_csr               (jtag_csr),
1106 
`endif
1107 
`ifdef LM32_SINGLE_STEP_ENABLED
1108 
    .eret_q_x               (eret_q_x),
1109 
    .bret_q_x               (bret_q_x),
1110 
    .stall_x                (stall_x),
1111 
    .exception_x            (exception_x),
1112 
    .q_x                    (q_x),
1113 
`ifdef CFG_DCACHE_ENABLED
1114 
    .dcache_refill_request  (dcache_refill_request),
1115 
`endif
1116 
`endif
1117 
    // ----- Outputs -------
1118 
`ifdef LM32_SINGLE_STEP_ENABLED
1119 
    .dc_ss                  (dc_ss),
1120 
`endif
1121 
    .dc_re                  (dc_re),
1122 
    .bp_match               (bp_match),
1123 
    .wp_match               (wp_match)
1124 
    );
1125 
`endif
1126 
 
1127 
// Register file
1128 
 
1129 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1130 
 
1131 
lm32_ram #(
1132 
    // ----- Parameters -------
1133 
    .data_width             (`LM32_WORD_WIDTH),
1134 
    .address_width          (`LM32_REG_IDX_WIDTH)
1135 
  ) reg_0 (
1136 
    // ----- Inputs -------
1137 
    .read_clk               (clk_i),
1138 
    .write_clk              (clk_i),
1139 
    .reset                  (rst_i),
1140 
    .enable_read            (stall_d == `FALSE),
1141 
    .read_address           (instruction_f[25:21]),
1142 
    .enable_write           (`TRUE),
1143 
    .write_address          (write_idx_w),
1144 
    .write_data             (w_result),
1145 
    .write_enable           (reg_write_enable_q_w),
1146 
    // ----- Outputs -------
1147 
    .read_data              (reg_data_live_0)
1148 
    );
1149 
 
1150 
lm32_ram #(
1151 
    // ----- Parameters -------
1152 
    .data_width             (`LM32_WORD_WIDTH),
1153 
    .address_width          (`LM32_REG_IDX_WIDTH)
1154 
  ) reg_1 (
1155 
    // ----- Inputs -------
1156 
    .read_clk               (clk_i),
1157 
    .write_clk              (clk_i),
1158 
    .reset                  (rst_i),
1159 
    .enable_read            (stall_d == `FALSE),
1160 
    .read_address           (instruction_f[20:16]),
1161 
    .enable_write           (`TRUE),
1162 
    .write_address          (write_idx_w),
1163 
    .write_data             (w_result),
1164 
    .write_enable           (reg_write_enable_q_w),
1165 
    // ----- Outputs -------
1166 
    .read_data              (reg_data_live_1)
1167 
    );
1168 
 
1169 
`endif
1170 
 
1171 
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1172 
 
1173 
lm32_ram #(
1174 
    // ----- Parameters -------
1175 
    .data_width             (`LM32_WORD_WIDTH),
1176 
    .address_width          (`LM32_REG_IDX_WIDTH)
1177 
  ) reg_0 (
1178 
    // ----- Inputs -------
1179 
    .read_clk               (clk_n_i),
1180 
    .write_clk              (clk_i),
1181 
    .reset                  (rst_i),
1182 
    .enable_read            (stall_f == `FALSE),
1183 
    .read_address           (read_idx_0_d),
1184 
    .enable_write           (`TRUE),
1185 
    .write_address          (write_idx_w),
1186 
    .write_data             (w_result),
1187 
    .write_enable           (reg_write_enable_q_w),
1188 
    // ----- Outputs -------
1189 
    .read_data              (reg_data_0)
1190 
    );
1191 
 
1192 
lm32_ram #(
1193 
    // ----- Parameters -------
1194 
    .data_width             (`LM32_WORD_WIDTH),
1195 
    .address_width          (`LM32_REG_IDX_WIDTH)
1196 
  ) reg_1 (
1197 
    // ----- Inputs -------
1198 
    .read_clk               (clk_n_i),
1199 
    .write_clk              (clk_i),
1200 
    .reset                  (rst_i),
1201 
    .enable_read            (stall_f == `FALSE),
1202 
    .read_address           (read_idx_1_d),
1203 
    .enable_write           (`TRUE),
1204 
    .write_address          (write_idx_w),
1205 
    .write_data             (w_result),
1206 
    .write_enable           (reg_write_enable_q_w),
1207 
    // ----- Outputs -------
1208 
    .read_data              (reg_data_1)
1209 
    );
1210 
 
1211 
`endif
1212 
 
1213 
 
1214 
/////////////////////////////////////////////////////
1215 
// Combinational Logic
1216 
/////////////////////////////////////////////////////
1217 
 
1218 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1219 
// Select between buffered and live data from register file
1220 
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1221 
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1222 
`endif
1223 
`ifdef LM32_EBR_REGISTER_FILE
1224 
`else
1225 
// Register file read ports
1226 
assign reg_data_0 = registers[read_idx_0_d];
1227 
assign reg_data_1 = registers[read_idx_1_d];
1228 
`endif
1229 
 
1230 
// Detect read-after-write hazzards
1231 
assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1232 
assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1233 
assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1234 
assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1235 
assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1236 
assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1237 
 
1238 
// Interlock detection - Raise an interlock for RAW hazzards
1239 
always @*
1240 
begin
1241 
    if (   (   (x_bypass_enable_x == `FALSE)
1242 
            && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1243 
                || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1244 
               )
1245 
           )
1246 
        || (   (m_bypass_enable_m == `FALSE)
1247 
            && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1248 
                || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1249 
               )
1250 
           )
1251 
       )
1252 
        interlock = `TRUE;
1253 
    else
1254 
        interlock = `FALSE;
1255 
end
1256 
 
1257 
// Bypass for reg port 0
1258 
always @*
1259 
begin
1260 
    if (raw_x_0 == `TRUE)
1261 
        bypass_data_0 = x_result;
1262 
    else if (raw_m_0 == `TRUE)
1263 
        bypass_data_0 = m_result;
1264 
    else if (raw_w_0 == `TRUE)
1265 
        bypass_data_0 = w_result;
1266 
    else
1267 
        bypass_data_0 = reg_data_0;
1268 
end
1269 
 
1270 
// Bypass for reg port 1
1271 
always @*
1272 
begin
1273 
    if (raw_x_1 == `TRUE)
1274 
        bypass_data_1 = x_result;
1275 
    else if (raw_m_1 == `TRUE)
1276 
        bypass_data_1 = m_result;
1277 
    else if (raw_w_1 == `TRUE)
1278 
        bypass_data_1 = w_result;
1279 
    else
1280 
        bypass_data_1 = reg_data_1;
1281 
end
1282 
 
1283 
// D stage result selection
1284 
always @*
1285 
begin
1286 
    d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1287 
    case (d_result_sel_1_d)
1288 
    `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1289 
    `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
1290 
    `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1291 
    default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1292 
    endcase
1293 
end
1294 
 
1295 
`ifdef CFG_USER_ENABLED
1296 
// Operands for user-defined instructions
1297 
assign user_operand_0 = operand_0_x;
1298 
assign user_operand_1 = operand_1_x;
1299 
`endif
1300 
 
1301 
`ifdef CFG_SIGN_EXTEND_ENABLED
1302 
// Sign-extension
1303 
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1304 
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1305 
assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1306 
`endif
1307 
 
1308 
`ifdef LM32_NO_BARREL_SHIFT
1309 
// Only single bit shift operations are supported when barrel-shifter isn't implemented
1310 
assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1311 
`endif
1312 
 
1313 
// Condition evaluation
1314 
assign cmp_zero = operand_0_x == operand_1_x;
1315 
assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1316 
assign cmp_overflow = adder_overflow_x;
1317 
assign cmp_carry_n = adder_carry_n_x;
1318 
always @*
1319 
begin
1320 
    case (condition_x)
1321 
    `LM32_CONDITION_U1:   condition_met_x = `TRUE;
1322 
    `LM32_CONDITION_U2:   condition_met_x = `TRUE;
1323 
    `LM32_CONDITION_E:    condition_met_x = cmp_zero;
1324 
    `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
1325 
    `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1326 
    `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
1327 
    `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
1328 
    `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
1329 
    default:              condition_met_x = 1'bx;
1330 
    endcase
1331 
end
1332 
 
1333 
// X stage result selection
1334 
always @*
1335 
begin
1336 
    x_result =   x_result_sel_add_x ? adder_result_x
1337 
               : x_result_sel_csr_x ? csr_read_data_x
1338 
`ifdef CFG_SIGN_EXTEND_ENABLED
1339 
               : x_result_sel_sext_x ? sext_result_x
1340 
`endif
1341 
`ifdef CFG_USER_ENABLED
1342 
               : x_result_sel_user_x ? user_result
1343 
`endif
1344 
`ifdef LM32_NO_BARREL_SHIFT
1345 
               : x_result_sel_shift_x ? shifter_result_x
1346 
`endif
1347 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1348 
               : x_result_sel_mc_arith_x ? mc_result_x
1349 
`endif
1350 
               : logic_result_x;
1351 
end
1352 
 
1353 
// M stage result selection
1354 
always @*
1355 
begin
1356 
    m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1357 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1358 
               : m_result_sel_shift_m ? shifter_result_m
1359 
`endif
1360 
               : operand_m;
1361 
end
1362 
 
1363 
// W stage result selection
1364 
always @*
1365 
begin
1366 
    w_result =    w_result_sel_load_w ? load_data_w
1367 
`ifdef CFG_PL_MULTIPLY_ENABLED
1368 
                : w_result_sel_mul_w ? multiplier_result_w
1369 
`endif
1370 
                : operand_w;
1371 
end
1372 
 
1373 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1374 
// Indicate when a branch should be taken in X stage
1375 
assign branch_taken_x =      (stall_x == `FALSE)
1376 
                          && (   (branch_x == `TRUE)
1377 
                              && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
1378 
                              && (valid_x == `TRUE)
1379 
                             );
1380 
`endif
1381 
 
1382 
// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1383 
assign branch_taken_m =      (stall_m == `FALSE)
1384 
                          && (   (   (branch_m == `TRUE)
1385 
                                  && (condition_met_m == `TRUE)
1386 
                                  && (valid_m == `TRUE)
1387 
                                 )
1388 
                              || (exception_m == `TRUE)
1389 
                             );
1390 
 
1391 
// Generate signal that will kill instructions in each pipeline stage when necessary
1392 
assign kill_f =    (branch_taken_m == `TRUE)
1393 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1394 
                || (branch_taken_x == `TRUE)
1395 
`endif
1396 
`ifdef CFG_ICACHE_ENABLED
1397 
                || (icache_refill_request == `TRUE)
1398 
`endif
1399 
`ifdef CFG_DCACHE_ENABLED
1400 
                || (dcache_refill_request == `TRUE)
1401 
`endif
1402 
                ;
1403 
assign kill_d =    (branch_taken_m == `TRUE)
1404 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1405 
                || (branch_taken_x == `TRUE)
1406 
`endif
1407 
`ifdef CFG_ICACHE_ENABLED
1408 
                || (icache_refill_request == `TRUE)
1409 
`endif
1410 
`ifdef CFG_DCACHE_ENABLED
1411 
                || (dcache_refill_request == `TRUE)
1412 
`endif
1413 
                ;
1414 
assign kill_x =    (branch_taken_m == `TRUE)
1415 
`ifdef CFG_DCACHE_ENABLED
1416 
                || (dcache_refill_request == `TRUE)
1417 
`endif
1418 
                ;
1419 
assign kill_m =    `FALSE
1420 
`ifdef CFG_DCACHE_ENABLED
1421 
                || (dcache_refill_request == `TRUE)
1422 
`endif
1423 
                ;
1424 
assign kill_w =    `FALSE
1425 
`ifdef CFG_DCACHE_ENABLED
1426 
                || (dcache_refill_request == `TRUE)
1427 
`endif
1428 
                ;
1429 
 
1430 
// Exceptions
1431 
 
1432 
`ifdef CFG_DEBUG_ENABLED
1433 
assign breakpoint_exception =    (break_x == `TRUE)
1434 
                              || (bp_match == `TRUE)
1435 
`ifdef CFG_JTAG_ENABLED
1436 
                              || (jtag_break == `TRUE)
1437 
`endif
1438 
                              ;
1439 
assign watchpoint_exception = wp_match == `TRUE;
1440 
`endif
1441 
`ifdef CFG_BUS_ERRORS_ENABLED
1442 
assign instruction_bus_error_exception = bus_error_x == `TRUE;
1443 
assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1444 
`endif
1445 
`ifdef CFG_MC_DIVIDE_ENABLED
1446 
assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1447 
`endif
1448 
assign system_call_exception = scall_x == `TRUE;
1449 
 
1450 
`ifdef CFG_DEBUG_ENABLED
1451 
assign debug_exception_x =  (breakpoint_exception == `TRUE)
1452 
                         || (watchpoint_exception == `TRUE)
1453 
                         ;
1454 
 
1455 
assign non_debug_exception_x = (system_call_exception == `TRUE)
1456 
`ifdef CFG_JTAG_ENABLED
1457 
                            || (reset_exception == `TRUE)
1458 
`endif
1459 
`ifdef CFG_BUS_ERRORS_ENABLED
1460 
                            || (instruction_bus_error_exception == `TRUE)
1461 
                            || (data_bus_error_exception == `TRUE)
1462 
`endif
1463 
`ifdef CFG_MC_DIVIDE_ENABLED
1464 
                            || (divide_by_zero_exception == `TRUE)
1465 
`endif
1466 
`ifdef CFG_INTERRUPTS_ENABLED
1467 
                            || (   (interrupt_exception == `TRUE)
1468 
`ifdef LM32_SINGLE_STEP_ENABLED
1469 
                                && (dc_ss == `FALSE)
1470 
`endif
1471 
                               )
1472 
`endif
1473 
                            ;
1474 
 
1475 
assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
1476 
`else
1477 
assign exception_x =           (system_call_exception == `TRUE)
1478 
`ifdef CFG_BUS_ERRORS_ENABLED
1479 
                            || (instruction_bus_error_exception == `TRUE)
1480 
                            || (data_bus_error_exception == `TRUE)
1481 
`endif
1482 
`ifdef CFG_MC_DIVIDE_ENABLED
1483 
                            || (divide_by_zero_exception == `TRUE)
1484 
`endif
1485 
`ifdef CFG_INTERRUPTS_ENABLED
1486 
                            || (   (interrupt_exception == `TRUE)
1487 
`ifdef LM32_SINGLE_STEP_ENABLED
1488 
                                && (dc_ss == `FALSE)
1489 
`endif
1490 
                               )
1491 
`endif
1492 
                            ;
1493 
`endif
1494 
 
1495 
// Exception ID
1496 
always @*
1497 
begin
1498 
`ifdef CFG_DEBUG_ENABLED
1499 
`ifdef CFG_JTAG_ENABLED
1500 
    if (reset_exception == `TRUE)
1501 
        eid_x = `LM32_EID_RESET;
1502 
    else
1503 
`endif
1504 
         if (breakpoint_exception == `TRUE)
1505 
        eid_x = `LM32_EID_BREAKPOINT;
1506 
    else
1507 
`endif
1508 
`ifdef CFG_BUS_ERRORS_ENABLED
1509 
         if (instruction_bus_error_exception == `TRUE)
1510 
        eid_x = `LM32_EID_INST_BUS_ERROR;
1511 
    else
1512 
`endif
1513 
`ifdef CFG_DEBUG_ENABLED
1514 
         if (watchpoint_exception == `TRUE)
1515 
        eid_x = `LM32_EID_WATCHPOINT;
1516 
    else
1517 
`endif
1518 
`ifdef CFG_BUS_ERRORS_ENABLED
1519 
         if (data_bus_error_exception == `TRUE)
1520 
        eid_x = `LM32_EID_DATA_BUS_ERROR;
1521 
    else
1522 
`endif
1523 
`ifdef CFG_MC_DIVIDE_ENABLED
1524 
         if (divide_by_zero_exception == `TRUE)
1525 
        eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1526 
    else
1527 
`endif
1528 
`ifdef CFG_INTERRUPTS_ENABLED
1529 
         if (   (interrupt_exception == `TRUE)
1530 
`ifdef LM32_SINGLE_STEP_ENABLED
1531 
             && (dc_ss == `FALSE)
1532 
`endif
1533 
            )
1534 
        eid_x = `LM32_EID_INTERRUPT;
1535 
    else
1536 
`endif
1537 
        eid_x = `LM32_EID_SCALL;
1538 
end
1539 
 
1540 
// Stall generation
1541 
 
1542 
assign stall_a = (stall_f == `TRUE);
1543 
 
1544 
assign stall_f = (stall_d == `TRUE);
1545 
 
1546 
assign stall_d =   (stall_x == `TRUE)
1547 
                || (   (interlock == `TRUE)
1548 
                    && (kill_d == `FALSE)
1549 
                   )
1550 
                || (   (eret_d == `TRUE)
1551 
                    && (load_q_x == `TRUE)
1552 
                   )
1553 
`ifdef CFG_DEBUG_ENABLED
1554 
                || (   (bret_d == `TRUE)
1555 
                    && (load_q_x == `TRUE)
1556 
                   )
1557 
`endif
1558 
                || (   (csr_write_enable_d == `TRUE)
1559 
                    && (load_q_x == `TRUE)
1560 
                   )
1561 
                ;
1562 
 
1563 
assign stall_x =    (stall_m == `TRUE)
1564 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1565 
                 || (   (mc_stall_request_x == `TRUE)
1566 
                     && (kill_x == `FALSE)
1567 
                    )
1568 
`endif
1569 
                 ;
1570 
 
1571 
assign stall_m =    (stall_wb_load == `TRUE)
1572 
`ifdef CFG_SIZE_OVER_SPEED
1573 
                 || (D_CYC_O == `TRUE)
1574 
`else
1575 
                 || (   (D_CYC_O == `TRUE)
1576 
                     && (   (store_m == `TRUE)
1577 
                         || (load_m == `TRUE)
1578 
                         || (load_x == `TRUE)
1579 
                        )
1580 
                    )
1581 
`endif
1582 
`ifdef CFG_DCACHE_ENABLED
1583 
                 || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1584 
`endif
1585 
`ifdef CFG_ICACHE_ENABLED
1586 
                 || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
1587 
                 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
1588 
`else
1589 
`ifdef CFG_IWB_ENABLED
1590 
                 || (I_CYC_O == `TRUE)
1591 
`endif
1592 
`endif
1593 
`ifdef CFG_USER_ENABLED
1594 
                 || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1595 
                     && (user_complete == `FALSE)
1596 
                    )
1597 
`endif
1598 
                 ;
1599 
 
1600 
// Qualify state changing control signals
1601 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1602 
wire   q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1603 
`endif
1604 
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
1605 
assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1606 
assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1607 
`endif
1608 
`ifdef CFG_MC_MULTIPLY_ENABLED
1609 
assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1610 
`endif
1611 
`ifdef CFG_MC_DIVIDE_ENABLED
1612 
assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1613 
assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1614 
`endif
1615 
wire   q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1616 
assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1617 
assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1618 
`ifdef CFG_DEBUG_ENABLED
1619 
assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1620 
`endif
1621 
assign load_q_x = (load_x == `TRUE)
1622 
               && (q_x == `TRUE)
1623 
`ifdef CFG_DEBUG_ENABLED
1624 
               && (bp_match == `FALSE)
1625 
`endif
1626 
                  ;
1627 
`ifdef CFG_USER_ENABLED
1628 
assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1629 
`endif
1630 
wire   q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1631 
assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1632 
assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1633 
`ifdef CFG_DEBUG_ENABLED
1634 
assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1635 
assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1636 
`else
1637 
assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1638 
`endif
1639 
// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1640 
assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE);
1641 
assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1642 
assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1643 
// The enable that actually does write the registers needs to be qualified with kill
1644 
assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
1645 
 
1646 
// Configuration (CFG) CSR
1647 
assign cfg = {
1648 
              `LM32_REVISION,
1649 
              watchpoints[3:0],
1650 
              breakpoints[3:0],
1651 
              interrupts[5:0],
1652 
`ifdef CFG_JTAG_UART_ENABLED
1653 
              `TRUE,
1654 
`else
1655 
              `FALSE,
1656 
`endif
1657 
`ifdef CFG_ROM_DEBUG_ENABLED
1658 
              `TRUE,
1659 
`else
1660 
              `FALSE,
1661 
`endif
1662 
`ifdef CFG_HW_DEBUG_ENABLED
1663 
              `TRUE,
1664 
`else
1665 
              `FALSE,
1666 
`endif
1667 
`ifdef CFG_DEBUG_ENABLED
1668 
              `TRUE,
1669 
`else
1670 
              `FALSE,
1671 
`endif
1672 
`ifdef CFG_ICACHE_ENABLED
1673 
              `TRUE,
1674 
`else
1675 
              `FALSE,
1676 
`endif
1677 
`ifdef CFG_DCACHE_ENABLED
1678 
              `TRUE,
1679 
`else
1680 
              `FALSE,
1681 
`endif
1682 
`ifdef CFG_CYCLE_COUNTER_ENABLED
1683 
              `TRUE,
1684 
`else
1685 
              `FALSE,
1686 
`endif
1687 
`ifdef CFG_USER_ENABLED
1688 
              `TRUE,
1689 
`else
1690 
              `FALSE,
1691 
`endif
1692 
`ifdef CFG_SIGN_EXTEND_ENABLED
1693 
              `TRUE,
1694 
`else
1695 
              `FALSE,
1696 
`endif
1697 
`ifdef LM32_BARREL_SHIFT_ENABLED
1698 
              `TRUE,
1699 
`else
1700 
              `FALSE,
1701 
`endif
1702 
`ifdef CFG_MC_DIVIDE_ENABLED
1703 
              `TRUE,
1704 
`else
1705 
              `FALSE,
1706 
`endif
1707 
`ifdef LM32_MULTIPLY_ENABLED
1708 
              `TRUE
1709 
`else
1710 
              `FALSE
1711 
`endif
1712 
              };
1713 
 
1714 
// Cache flush
1715 
`ifdef CFG_ICACHE_ENABLED
1716 
assign iflush =    (csr_write_enable_d == `TRUE)
1717 
                && (csr_d == `LM32_CSR_ICC)
1718 
                && (stall_d == `FALSE)
1719 
                && (kill_d == `FALSE)
1720 
                && (valid_d == `TRUE);
1721 
`endif
1722 
`ifdef CFG_DCACHE_ENABLED
1723 
assign dflush_x =  (csr_write_enable_q_x == `TRUE)
1724 
                && (csr_x == `LM32_CSR_DCC);
1725 
`endif
1726 
 
1727 
// Extract CSR index
1728 
assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
1729 
 
1730 
// CSR reads
1731 
always @*
1732 
begin
1733 
    case (csr_x)
1734 
`ifdef CFG_INTERRUPTS_ENABLED
1735 
    `LM32_CSR_IE,
1736 
    `LM32_CSR_IM,
1737 
    `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;
1738 
`endif
1739 
`ifdef CFG_CYCLE_COUNTER_ENABLED
1740 
    `LM32_CSR_CC:   csr_read_data_x = cc;
1741 
`endif
1742 
    `LM32_CSR_CFG:  csr_read_data_x = cfg;
1743 
    `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
1744 
`ifdef CFG_DEBUG_ENABLED
1745 
    `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
1746 
`endif
1747 
`ifdef CFG_JTAG_UART_ENABLED
1748 
    `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;
1749 
    `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
1750 
`endif
1751 
    default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
1752 
    endcase
1753 
end
1754 
 
1755 
/////////////////////////////////////////////////////
1756 
// Sequential Logic
1757 
/////////////////////////////////////////////////////
1758 
 
1759 
// Exception Base Address (EBA) CSR
1760 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1761 
begin
1762 
    if (rst_i == `TRUE)
1763 
        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
1764 
    else
1765 
    begin
1766 
        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
1767 
            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
1768 
`ifdef CFG_HW_DEBUG_ENABLED
1769 
        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
1770 
            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
1771 
`endif
1772 
    end
1773 
end
1774 
 
1775 
`ifdef CFG_DEBUG_ENABLED
1776 
// Debug Exception Base Address (DEBA) CSR
1777 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1778 
begin
1779 
    if (rst_i == `TRUE)
1780 
        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
1781 
    else
1782 
    begin
1783 
        if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
1784 
            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
1785 
`ifdef CFG_HW_DEBUG_ENABLED
1786 
        if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
1787 
            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
1788 
`endif
1789 
    end
1790 
end
1791 
`endif
1792 
 
1793 
// Cycle Counter (CC) CSR
1794 
`ifdef CFG_CYCLE_COUNTER_ENABLED
1795 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1796 
begin
1797 
    if (rst_i == `TRUE)
1798 
        cc <= {`LM32_WORD_WIDTH{1'b0}};
1799 
    else
1800 
        cc <= cc + 1'b1;
1801 
end
1802 
`endif
1803 
 
1804 
`ifdef CFG_BUS_ERRORS_ENABLED
1805 
// Watch for data bus errors
1806 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1807 
begin
1808 
    if (rst_i == `TRUE)
1809 
        data_bus_error_seen <= `FALSE;
1810 
    else
1811 
    begin
1812 
        // Set flag when bus error is detected
1813 
        if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
1814 
            data_bus_error_seen <= `TRUE;
1815 
        // Clear flag when exception is taken
1816 
        if ((exception_m == `TRUE) && (kill_m == `FALSE))
1817 
            data_bus_error_seen <= `FALSE;
1818 
    end
1819 
end
1820 
`endif
1821 
 
1822 
// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
1823 
 
1824 
`ifdef CFG_ICACHE_ENABLED
1825 
`ifdef CFG_DCACHE_ENABLED
1826 
always @*
1827 
begin
1828 
    if (   (icache_refill_request == `TRUE)
1829 
        || (dcache_refill_request == `TRUE)
1830 
       )
1831 
        valid_a = `FALSE;
1832 
    else if (   (icache_restart_request == `TRUE)
1833 
             || (dcache_restart_request == `TRUE)
1834 
            )
1835 
        valid_a = `TRUE;
1836 
    else
1837 
        valid_a = !icache_refilling && !dcache_refilling;
1838 
end
1839 
`else
1840 
always @*
1841 
begin
1842 
    if (icache_refill_request == `TRUE)
1843 
        valid_a = `FALSE;
1844 
    else if (icache_restart_request == `TRUE)
1845 
        valid_a = `TRUE;
1846 
    else
1847 
        valid_a = !icache_refilling;
1848 
end
1849 
`endif
1850 
`else
1851 
`ifdef CFG_DCACHE_ENABLED
1852 
always @*
1853 
begin
1854 
    if (dcache_refill_request == `TRUE)
1855 
        valid_a = `FALSE;
1856 
    else if (dcache_restart_request == `TRUE)
1857 
        valid_a = `TRUE;
1858 
    else
1859 
        valid_a = !dcache_refilling;
1860 
end
1861 
`endif
1862 
`endif
1863 
 
1864 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1865 
begin
1866 
    if (rst_i == `TRUE)
1867 
    begin
1868 
        valid_f <= `FALSE;
1869 
        valid_d <= `FALSE;
1870 
        valid_x <= `FALSE;
1871 
        valid_m <= `FALSE;
1872 
        valid_w <= `FALSE;
1873 
    end
1874 
    else
1875 
    begin
1876 
        if ((kill_f == `TRUE) || (stall_a == `FALSE))
1877 
`ifdef LM32_CACHE_ENABLED
1878 
            valid_f <= valid_a;
1879 
`else
1880 
            valid_f <= `TRUE;
1881 
`endif
1882 
        else if (stall_f == `FALSE)
1883 
            valid_f <= `FALSE;
1884 
        if (kill_d == `TRUE)
1885 
            valid_d <= `FALSE;
1886 
        else if (stall_f == `FALSE)
1887 
            valid_d <= valid_f & !kill_f;
1888 
        else if (stall_d == `FALSE)
1889 
            valid_d <= `FALSE;
1890 
        if (kill_x == `TRUE)
1891 
            valid_x <= `FALSE;
1892 
        else if (stall_d == `FALSE)
1893 
            valid_x <= valid_d & !kill_d;
1894 
        else if (stall_x == `FALSE)
1895 
            valid_x <= `FALSE;
1896 
        if (kill_m == `TRUE)
1897 
            valid_m <= `FALSE;
1898 
        else if (stall_x == `FALSE)
1899 
            valid_m <= valid_x & !kill_x;
1900 
        else if (stall_m == `FALSE)
1901 
            valid_m <= `FALSE;
1902 
        if (stall_m == `FALSE)
1903 
            valid_w <= valid_m & !kill_m;
1904 
        else
1905 
            valid_w <= `FALSE;
1906 
    end
1907 
end
1908 
 
1909 
// Microcode pipeline registers
1910 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1911 
begin
1912 
    if (rst_i == `TRUE)
1913 
    begin
1914 
`ifdef CFG_USER_ENABLED
1915 
        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
1916 
`endif
1917 
        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
1918 
        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
1919 
        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
1920 
        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
1921 
        x_result_sel_csr_x <= `FALSE;
1922 
`ifdef LM32_MC_ARITHMETIC_ENABLED
1923 
        x_result_sel_mc_arith_x <= `FALSE;
1924 
`endif
1925 
`ifdef LM32_NO_BARREL_SHIFT
1926 
        x_result_sel_shift_x <= `FALSE;
1927 
`endif
1928 
`ifdef CFG_SIGN_EXTEND_ENABLED
1929 
        x_result_sel_sext_x <= `FALSE;
1930 
`endif
1931 
        x_result_sel_logic_x <= `FALSE;
1932 
`ifdef CFG_USER_ENABLED
1933 
        x_result_sel_user_x <= `FALSE;
1934 
`endif
1935 
        x_result_sel_add_x <= `FALSE;
1936 
        m_result_sel_compare_x <= `FALSE;
1937 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1938 
        m_result_sel_shift_x <= `FALSE;
1939 
`endif
1940 
        w_result_sel_load_x <= `FALSE;
1941 
`ifdef CFG_PL_MULTIPLY_ENABLED
1942 
        w_result_sel_mul_x <= `FALSE;
1943 
`endif
1944 
        x_bypass_enable_x <= `FALSE;
1945 
        m_bypass_enable_x <= `FALSE;
1946 
        write_enable_x <= `FALSE;
1947 
        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
1948 
        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
1949 
        load_x <= `FALSE;
1950 
        store_x <= `FALSE;
1951 
        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
1952 
        sign_extend_x <= `FALSE;
1953 
        adder_op_x <= `FALSE;
1954 
        adder_op_x_n <= `FALSE;
1955 
        logic_op_x <= 4'h0;
1956 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1957 
        direction_x <= `FALSE;
1958 
`endif
1959 
`ifdef CFG_ROTATE_ENABLED
1960 
        rotate_x <= `FALSE;
1961 
 
1962 
`endif
1963 
        branch_x <= `FALSE;
1964 
        condition_x <= `LM32_CONDITION_U1;
1965 
`ifdef CFG_DEBUG_ENABLED
1966 
        break_x <= `FALSE;
1967 
`endif
1968 
        scall_x <= `FALSE;
1969 
        eret_x <= `FALSE;
1970 
`ifdef CFG_DEBUG_ENABLED
1971 
        bret_x <= `FALSE;
1972 
`endif
1973 
`ifdef CFG_BUS_ERRORS_ENABLED
1974 
        bus_error_x <= `FALSE;
1975 
`endif
1976 
        csr_write_enable_x <= `FALSE;
1977 
        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
1978 
        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
1979 
        m_result_sel_compare_m <= `FALSE;
1980 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1981 
        m_result_sel_shift_m <= `FALSE;
1982 
`endif
1983 
        w_result_sel_load_m <= `FALSE;
1984 
`ifdef CFG_PL_MULTIPLY_ENABLED
1985 
        w_result_sel_mul_m <= `FALSE;
1986 
`endif
1987 
        m_bypass_enable_m <= `FALSE;
1988 
        branch_m <= `FALSE;
1989 
        exception_m <= `FALSE;
1990 
        load_m <= `FALSE;
1991 
        store_m <= `FALSE;
1992 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1993 
        direction_m <= `FALSE;
1994 
`endif
1995 
        write_enable_m <= `FALSE;
1996 
        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
1997 
        condition_met_m <= `FALSE;
1998 
`ifdef CFG_DCACHE_ENABLED
1999 
        dflush_m <= `FALSE;
2000 
`endif
2001 
`ifdef CFG_DEBUG_ENABLED
2002 
        debug_exception_m <= `FALSE;
2003 
        non_debug_exception_m <= `FALSE;
2004 
`endif
2005 
        operand_w <= {`LM32_WORD_WIDTH{1'b0}};
2006 
        w_result_sel_load_w <= `FALSE;
2007 
`ifdef CFG_PL_MULTIPLY_ENABLED
2008 
        w_result_sel_mul_w <= `FALSE;
2009 
`endif
2010 
        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
2011 
        write_enable_w <= `FALSE;
2012 
`ifdef CFG_DEBUG_ENABLED
2013 
        debug_exception_w <= `FALSE;
2014 
        non_debug_exception_w <= `FALSE;
2015 
`else
2016 
        exception_w <= `FALSE;
2017 
`endif
2018 
    end
2019 
    else
2020 
    begin
2021 
        // D/X stage registers
2022 
 
2023 
        if (stall_x == `FALSE)
2024 
        begin
2025 
`ifdef CFG_USER_ENABLED
2026 
            user_opcode <= user_opcode_d;
2027 
`endif
2028 
            operand_0_x <= d_result_0;
2029 
            operand_1_x <= d_result_1;
2030 
            store_operand_x <= bypass_data_1;
2031 
            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : pc_d + branch_offset_d;
2032 
            x_result_sel_csr_x <= x_result_sel_csr_d;
2033 
`ifdef LM32_MC_ARITHMETIC_ENABLED
2034 
            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2035 
`endif
2036 
`ifdef LM32_NO_BARREL_SHIFT
2037 
            x_result_sel_shift_x <= x_result_sel_shift_d;
2038 
`endif
2039 
`ifdef CFG_SIGN_EXTEND_ENABLED
2040 
            x_result_sel_sext_x <= x_result_sel_sext_d;
2041 
`endif
2042 
            x_result_sel_logic_x <= x_result_sel_logic_d;
2043 
`ifdef CFG_USER_ENABLED
2044 
            x_result_sel_user_x <= x_result_sel_user_d;
2045 
`endif
2046 
            x_result_sel_add_x <= x_result_sel_add_d;
2047 
            m_result_sel_compare_x <= m_result_sel_compare_d;
2048 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2049 
            m_result_sel_shift_x <= m_result_sel_shift_d;
2050 
`endif
2051 
            w_result_sel_load_x <= w_result_sel_load_d;
2052 
`ifdef CFG_PL_MULTIPLY_ENABLED
2053 
            w_result_sel_mul_x <= w_result_sel_mul_d;
2054 
`endif
2055 
            x_bypass_enable_x <= x_bypass_enable_d;
2056 
            m_bypass_enable_x <= m_bypass_enable_d;
2057 
            load_x <= load_d;
2058 
            store_x <= store_d;
2059 
            branch_x <= branch_d;
2060 
            write_idx_x <= write_idx_d;
2061 
            csr_x <= csr_d;
2062 
            size_x <= size_d;
2063 
            sign_extend_x <= sign_extend_d;
2064 
            adder_op_x <= adder_op_d;
2065 
            adder_op_x_n <= ~adder_op_d;
2066 
            logic_op_x <= logic_op_d;
2067 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2068 
            direction_x <= direction_d;
2069 
`endif
2070 
`ifdef CFG_ROTATE_ENABLED
2071 
            rotate_x <= rotate_d;
2072 
`endif
2073 
            condition_x <= condition_d;
2074 
            csr_write_enable_x <= csr_write_enable_d;
2075 
`ifdef CFG_DEBUG_ENABLED
2076 
            break_x <= break_d;
2077 
`endif
2078 
            scall_x <= scall_d;
2079 
`ifdef CFG_BUS_ERRORS_ENABLED
2080 
            bus_error_x <= bus_error_d;
2081 
`endif
2082 
            eret_x <= eret_d;
2083 
`ifdef CFG_DEBUG_ENABLED
2084 
            bret_x <= bret_d;
2085 
`endif
2086 
            write_enable_x <= write_enable_d;
2087 
        end
2088 
 
2089 
        // X/M stage registers
2090 
 
2091 
        if (stall_m == `FALSE)
2092 
        begin
2093 
            operand_m <= x_result;
2094 
            m_result_sel_compare_m <= m_result_sel_compare_x;
2095 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2096 
            m_result_sel_shift_m <= m_result_sel_shift_x;
2097 
`endif
2098 
            if (exception_x == `TRUE)
2099 
            begin
2100 
                w_result_sel_load_m <= `FALSE;
2101 
`ifdef CFG_PL_MULTIPLY_ENABLED
2102 
                w_result_sel_mul_m <= `FALSE;
2103 
`endif
2104 
            end
2105 
            else
2106 
            begin
2107 
                w_result_sel_load_m <= w_result_sel_load_x;
2108 
`ifdef CFG_PL_MULTIPLY_ENABLED
2109 
                w_result_sel_mul_m <= w_result_sel_mul_x;
2110 
`endif
2111 
            end
2112 
            m_bypass_enable_m <= m_bypass_enable_x;
2113 
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2114 
            direction_m <= direction_x;
2115 
`endif
2116 
            load_m <= load_x;
2117 
            store_m <= store_x;
2118 
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2119 
            branch_m <= branch_x && !branch_taken_x;
2120 
`else
2121 
            branch_m <= branch_x;
2122 
`endif
2123 
`ifdef CFG_DEBUG_ENABLED
2124 
            if (debug_exception_x == `TRUE)
2125 
                write_idx_m <= `LM32_BA_REG;
2126 
            else if (non_debug_exception_x == `TRUE)
2127 
                write_idx_m <= `LM32_EA_REG;
2128 
            else
2129 
                write_idx_m <= write_idx_x;
2130 
`else
2131 
            if (exception_x == `TRUE)
2132 
                write_idx_m <= `LM32_EA_REG;
2133 
            else
2134 
                write_idx_m <= write_idx_x;
2135 
`endif
2136 
            condition_met_m <= condition_met_x;
2137 
`ifdef CFG_DEBUG_ENABLED
2138 
            branch_target_m <= exception_x == `TRUE ? {(debug_exception_x == `TRUE) || (dc_re == `TRUE) ? deba : eba, eid_x, {3{1'b0}}} : branch_target_x;
2139 
`else
2140 
            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2141 
`endif
2142 
`ifdef CFG_TRACE_ENABLED
2143 
            eid_m <= eid_x;
2144 
`endif
2145 
`ifdef CFG_DCACHE_ENABLED
2146 
            dflush_m <= dflush_x;
2147 
`endif
2148 
            eret_m <= eret_q_x;
2149 
`ifdef CFG_DEBUG_ENABLED
2150 
            bret_m <= bret_q_x;
2151 
`endif
2152 
            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2153 
`ifdef CFG_DEBUG_ENABLED
2154 
            debug_exception_m <= debug_exception_x;
2155 
            non_debug_exception_m <= non_debug_exception_x;
2156 
`endif
2157 
        end
2158 
 
2159 
        // State changing regs
2160 
        if (stall_m == `FALSE)
2161 
        begin
2162 
            if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2163 
                exception_m <= `TRUE;
2164 
            else
2165 
                exception_m <= `FALSE;
2166 
        end
2167 
 
2168 
        // M/W stage registers
2169 
 
2170 
        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2171 
        w_result_sel_load_w <= w_result_sel_load_m;
2172 
`ifdef CFG_PL_MULTIPLY_ENABLED
2173 
        w_result_sel_mul_w <= w_result_sel_mul_m;
2174 
`endif
2175 
        write_idx_w <= write_idx_m;
2176 
`ifdef CFG_TRACE_ENABLED
2177 
        eid_w <= eid_m;
2178 
        eret_w <= eret_m;
2179 
`ifdef CFG_DEBUG_ENABLED
2180 
        bret_w <= bret_m;
2181 
`endif
2182 
`endif
2183 
        write_enable_w <= write_enable_m;
2184 
`ifdef CFG_DEBUG_ENABLED
2185 
        debug_exception_w <= debug_exception_m;
2186 
        non_debug_exception_w <= non_debug_exception_m;
2187 
`else
2188 
        exception_w <= exception_m;
2189 
`endif
2190 
    end
2191 
end
2192 
 
2193 
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2194 
// Buffer data read from register file, in case a stall occurs, and watch for
2195 
// any writes to the modified registers
2196 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2197 
begin
2198 
    if (rst_i == `TRUE)
2199 
    begin
2200 
        use_buf <= `FALSE;
2201 
        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2202 
        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2203 
    end
2204 
    else
2205 
    begin
2206 
        if (stall_d == `FALSE)
2207 
            use_buf <= `FALSE;
2208 
        else if (use_buf == `FALSE)
2209 
        begin
2210 
            reg_data_buf_0 <= reg_data_live_0;
2211 
            reg_data_buf_1 <= reg_data_live_1;
2212 
            use_buf <= `TRUE;
2213 
        end
2214 
        if (reg_write_enable_q_w == `TRUE)
2215 
        begin
2216 
            if (write_idx_w == read_idx_0_d)
2217 
                reg_data_buf_0 <= w_result;
2218 
            if (write_idx_w == read_idx_1_d)
2219 
                reg_data_buf_1 <= w_result;
2220 
        end
2221 
    end
2222 
end
2223 
`endif
2224 
 
2225 
`ifdef LM32_EBR_REGISTER_FILE
2226 
`else
2227 
// Register file write port
2228 
// Adding a reset causes a huge slowdown and requires lots of extra LUTs
2229 
always @(posedge clk_i)
2230 
begin
2231 
    if (reg_write_enable_q_w == `TRUE)
2232 
        registers[write_idx_w] <= w_result;
2233 
end
2234 
`endif
2235 
 
2236 
`ifdef CFG_TRACE_ENABLED
2237 
// PC tracing logic
2238 
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2239 
begin
2240 
    if (rst_i == `TRUE)
2241 
    begin
2242 
        trace_pc_valid <= `FALSE;
2243 
        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2244 
        trace_exception <= `FALSE;
2245 
        trace_eid <= `LM32_EID_RESET;
2246 
        trace_eret <= `FALSE;
2247 
`ifdef CFG_DEBUG_ENABLED
2248 
        trace_bret <= `FALSE;
2249 
`endif
2250 
        pc_c <= `CFG_EBA_RESET/4;
2251 
    end
2252 
    else
2253 
    begin
2254 
        trace_pc_valid <= `FALSE;
2255 
 
2256 
        // Has an exception occured
2257 
`ifdef CFG_DEBUG_ENABLED
2258 
        if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
2259 
`else
2260 
        if (exception_q_w == `TRUE)
2261 
`endif
2262 
        begin
2263 
            trace_exception <= `TRUE;
2264 
            trace_pc_valid <= `TRUE;
2265 
            trace_pc <= pc_w;
2266 
            trace_eid <= eid_w;
2267 
        end
2268 
        else
2269 
            trace_exception <= `FALSE;
2270 
 
2271 
        if ((valid_w == `TRUE) && (!kill_w))
2272 
        begin
2273 
            // An instruction is commiting. Determine if it is non-sequential
2274 
            if (pc_c + 1'b1 != pc_w)
2275 
            begin
2276 
                // Non-sequential instruction
2277 
                trace_pc_valid <= `TRUE;
2278 
                trace_pc <= pc_w;
2279 
            end
2280 
            // Record PC so we can determine if next instruction is sequential or not
2281 
            pc_c <= pc_w;
2282 
            // Indicate if it was an eret/bret instruction
2283 
            trace_eret <= eret_w;
2284 
`ifdef CFG_DEBUG_ENABLED
2285 
            trace_bret <= bret_w;
2286 
`endif
2287 
        end
2288 
        else
2289 
        begin
2290 
            trace_eret <= `FALSE;
2291 
`ifdef CFG_DEBUG_ENABLED
2292 
            trace_bret <= `FALSE;
2293 
`endif
2294 
        end
2295 
    end
2296 
end
2297 
`endif
2298 
 
2299 
/////////////////////////////////////////////////////
2300 
// Behavioural Logic
2301 
/////////////////////////////////////////////////////
2302 
 
2303 
// synthesis translate_off
2304 
 
2305 
// Reset register 0. Only needed for simulation.
2306 
initial
2307 
begin
2308 
`ifdef LM32_EBR_REGISTER_FILE
2309 
    reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2310 
    reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2311 
`else
2312 
    registers[0] = {`LM32_WORD_WIDTH{1'b0}};
2313 
`endif
2314 
end
2315 
 
2316 
// synthesis translate_on
2317 
 
2318 
endmodule

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