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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_debug.v] - Blame information for rev 17

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// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_debug.v
// Title            : Hardware debug registers and associated logic.
// Dependencies     : lm32_include.v
// Version          : 6.1.17
// =============================================================================
 
`include "lm32_include.v"
 
`ifdef CFG_DEBUG_ENABLED
 
// States for single-step FSM
`define LM32_DEBUG_SS_STATE_RNG                 2:0
`define LM32_DEBUG_SS_STATE_IDLE                3'b000
`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET        3'b001
`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN    3'b010
`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT    3'b011
`define LM32_DEBUG_SS_STATE_RESTART             3'b100
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_debug (
    // ----- Inputs -------
    clk_i,
    rst_i,
    pc_x,
    load_x,
    store_x,
    load_store_address_x,
    csr_write_enable_x,
    csr_write_data,
    csr_x,
`ifdef CFG_HW_DEBUG_ENABLED
    jtag_csr_write_enable,
    jtag_csr_write_data,
    jtag_csr,
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
    eret_q_x,
    bret_q_x,
    stall_x,
    exception_x,
    q_x,
`ifdef CFG_DCACHE_ENABLED
    dcache_refill_request,
`endif
`endif
    // ----- Outputs -------
`ifdef LM32_SINGLE_STEP_ENABLED
    dc_ss,
`endif
    dc_re,
    bp_match,
    wp_match
    );
 
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
 
parameter breakpoints = 0;                      // Number of breakpoint CSRs
parameter watchpoints = 0;                      // Number of watchpoint CSRs
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                    // Clock
input rst_i;                                    // Reset
 
input [`LM32_PC_RNG] pc_x;                      // X stage PC
input load_x;                                   // Load instruction in X stage
input store_x;                                  // Store instruction in X stage
input [`LM32_WORD_RNG] load_store_address_x;    // Load or store effective address
input csr_write_enable_x;                       // wcsr instruction in X stage
input [`LM32_WORD_RNG] csr_write_data;          // Data to write to CSR
input [`LM32_CSR_RNG] csr_x;                    // Which CSR to write
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_csr_write_enable;                    // JTAG interface CSR write enable
input [`LM32_WORD_RNG] jtag_csr_write_data;     // Data to write to CSR
input [`LM32_CSR_RNG] jtag_csr;                 // Which CSR to write
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
input eret_q_x;                                 // eret instruction in X stage
input bret_q_x;                                 // bret instruction in X stage
input stall_x;                                  // Instruction in X stage is stalled
input exception_x;                              // An exception has occured in X stage 
input q_x;                                      // Indicates the instruction in the X stage is qualified
`ifdef CFG_DCACHE_ENABLED
input dcache_refill_request;                    // Indicates data cache wants to be refilled 
`endif
`endif
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
`ifdef LM32_SINGLE_STEP_ENABLED
output dc_ss;                                   // Single-step enable
reg    dc_ss;
`endif
output dc_re;                                   // Remap exceptions
reg    dc_re;
output bp_match;                                // Indicates a breakpoint has matched
wire   bp_match;
output wp_match;                                // Indicates a watchpoint has matched
wire   wp_match;
 
/////////////////////////////////////////////////////
// Internal nets and registers 
/////////////////////////////////////////////////////
 
genvar i;                                       // Loop index for generate statements
 
// Debug CSRs
 
reg [`LM32_PC_RNG] bp_a[0:breakpoints-1];       // Instruction breakpoint address
reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
 
reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1];   // Watchpoint enable
reg [`LM32_WORD_RNG] wp[0:watchpoints-1];       // Watchpoint address
wire [0:watchpoints-1]wp_match_n;               // Indicates if a h/w data watchpoint matched
 
wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
wire [`LM32_WORD_RNG] debug_csr_write_data;     // Data to write to debug CSR
wire [`LM32_CSR_RNG] debug_csr;                 // Debug CSR to write to
 
`ifdef LM32_SINGLE_STEP_ENABLED
// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
//reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
integer state;                                  // State of single-step FSM
`endif
 
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`define  INCLUDE_FUNCTION
`include "lm32_functions.v"
 
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
 
// Check for breakpoints
generate
    for (i = 0; i < breakpoints; i = i + 1)
    begin : bp_comb
assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
    end
endgenerate
generate
`ifdef LM32_SINGLE_STEP_ENABLED
    if (breakpoints > 0)
assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
    else
assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
`else
    if (breakpoints > 0)
assign bp_match = |bp_match_n;
    else
assign bp_match = `FALSE;
`endif
endgenerate
 
// Check for watchpoints
generate
    for (i = 0; i < watchpoints; i = i + 1)
    begin : wp_comb
assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
    end
endgenerate
generate
    if (watchpoints > 0)
assign wp_match = |wp_match_n;
    else
assign wp_match = `FALSE;
endgenerate
 
`ifdef CFG_HW_DEBUG_ENABLED
// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
`else
assign debug_csr_write_enable = csr_write_enable_x;
assign debug_csr_write_data = csr_write_data;
assign debug_csr = csr_x;
`endif
 
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
 
// Breakpoint address and enable CSRs
generate
    for (i = 0; i < breakpoints; i = i + 1)
    begin : bp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
        bp_e[i] <= `FALSE;
    end
    else
    begin
        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
        begin
            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
            bp_e[i] <= debug_csr_write_data[0];
        end
    end
end
    end
endgenerate
 
// Watchpoint address and control flags CSRs
generate
    for (i = 0; i < watchpoints; i = i + 1)
    begin : wp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
        wpc_c[i] <= `LM32_WPC_C_DISABLED;
    end
    else
    begin
        if (debug_csr_write_enable == `TRUE)
        begin
            if (debug_csr == `LM32_CSR_DC)
                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
            if (debug_csr == `LM32_CSR_WP0 + i)
                wp[i] <= debug_csr_write_data;
        end
    end
end
    end
endgenerate
 
// Remap exceptions control bit
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
        dc_re <= `FALSE;
    else
    begin
        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
            dc_re <= debug_csr_write_data[1];
    end
end
 
`ifdef LM32_SINGLE_STEP_ENABLED
// Single-step control flag
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        state <= `LM32_DEBUG_SS_STATE_IDLE;
        dc_ss <= `FALSE;
    end
    else
    begin
        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
        begin
            dc_ss <= debug_csr_write_data[0];
            if (debug_csr_write_data[0] == `FALSE)
                state <= `LM32_DEBUG_SS_STATE_IDLE;
            else
                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
        end
        case (state)
        `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
        begin
            // Wait for eret or bret instruction to be executed
            if (   (   (eret_q_x == `TRUE)
                    || (bret_q_x == `TRUE)
                    )
                && (stall_x == `FALSE)
               )
                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
        end
        `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
        begin
            // Wait for an instruction to be executed
            if ((q_x == `TRUE) && (stall_x == `FALSE))
                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
        end
        `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
        begin
            // Wait for exception to be raised
`ifdef CFG_DCACHE_ENABLED
            if (dcache_refill_request == `TRUE)
                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
            else
`endif
                 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
            begin
                dc_ss <= `FALSE;
                state <= `LM32_DEBUG_SS_STATE_RESTART;
            end
        end
        `LM32_DEBUG_SS_STATE_RESTART:
        begin
            // Watch to see if stepped instruction is restarted due to a cache miss
`ifdef CFG_DCACHE_ENABLED
            if (dcache_refill_request == `TRUE)
                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
            else
`endif
                state <= `LM32_DEBUG_SS_STATE_IDLE;
        end
        endcase
    end
end
`endif
 
endmodule
 
`endif

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_debug.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	alirezamon	`// =============================================================================`
2			`// COPYRIGHT NOTICE`
3			`// Copyright 2006 (c) Lattice Semiconductor Corporation`
4			`// ALL RIGHTS RESERVED`
5			`// This confidential and proprietary software may be used only as authorised by`
6			`// a licensing agreement from Lattice Semiconductor Corporation.`
7			`// The entire notice above must be reproduced on all authorized copies and`
8			`// copies may only be made to the extent permitted by a licensing agreement from`
9			`// Lattice Semiconductor Corporation.`
10			`//`
11			`// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)`
12			`// 5555 NE Moore Court 408-826-6000 (other locations)`
13			`// Hillsboro, OR 97124 web : http://www.latticesemi.com/`
14			`// U.S.A email: techsupport@latticesemi.com`
15			`// =============================================================================/`
16			`// FILE DETAILS`
17			`// Project : LatticeMico32`
18			`// File : lm32_debug.v`
19			`// Title : Hardware debug registers and associated logic.`
20			`// Dependencies : lm32_include.v`
21			`// Version : 6.1.17`
22			`// =============================================================================`
23
24			`include "lm32_include.v"
25
26			`ifdef CFG_DEBUG_ENABLED
27
28			`// States for single-step FSM`
29			`define LM32_DEBUG_SS_STATE_RNG 2:0
30			`define LM32_DEBUG_SS_STATE_IDLE 3'b000
31			`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
32			`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
33			`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
34			`define LM32_DEBUG_SS_STATE_RESTART 3'b100
35
36			`/////////////////////////////////////////////////////`
37			`// Module interface`
38			`/////////////////////////////////////////////////////`
39
40			`module lm32_debug (`
41			`// ----- Inputs -------`
42			`clk_i,`
43			`rst_i,`
44			`pc_x,`
45			`load_x,`
46			`store_x,`
47			`load_store_address_x,`
48			`csr_write_enable_x,`
49			`csr_write_data,`
50			`csr_x,`
51			`ifdef CFG_HW_DEBUG_ENABLED
52			`jtag_csr_write_enable,`
53			`jtag_csr_write_data,`
54			`jtag_csr,`
55			`endif
56			`ifdef LM32_SINGLE_STEP_ENABLED
57			`eret_q_x,`
58			`bret_q_x,`
59			`stall_x,`
60			`exception_x,`
61			`q_x,`
62			`ifdef CFG_DCACHE_ENABLED
63			`dcache_refill_request,`
64			`endif
65			`endif
66			`// ----- Outputs -------`
67			`ifdef LM32_SINGLE_STEP_ENABLED
68			`dc_ss,`
69			`endif
70			`dc_re,`
71			`bp_match,`
72			`wp_match`
73			`);`
74
75			`/////////////////////////////////////////////////////`
76			`// Parameters`
77			`/////////////////////////////////////////////////////`
78
79			`parameter breakpoints = 0; // Number of breakpoint CSRs`
80			`parameter watchpoints = 0; // Number of watchpoint CSRs`
81
82			`/////////////////////////////////////////////////////`
83			`// Inputs`
84			`/////////////////////////////////////////////////////`
85
86			`input clk_i; // Clock`
87			`input rst_i; // Reset`
88
89			input [`LM32_PC_RNG] pc_x; // X stage PC
90			`input load_x; // Load instruction in X stage`
91			`input store_x; // Store instruction in X stage`
92			input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
93			`input csr_write_enable_x; // wcsr instruction in X stage`
94			input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
95			input [`LM32_CSR_RNG] csr_x; // Which CSR to write
96			`ifdef CFG_HW_DEBUG_ENABLED
97			`input jtag_csr_write_enable; // JTAG interface CSR write enable`
98			input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
99			input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
100			`endif
101			`ifdef LM32_SINGLE_STEP_ENABLED
102			`input eret_q_x; // eret instruction in X stage`
103			`input bret_q_x; // bret instruction in X stage`
104			`input stall_x; // Instruction in X stage is stalled`
105			`input exception_x; // An exception has occured in X stage`
106			`input q_x; // Indicates the instruction in the X stage is qualified`
107			`ifdef CFG_DCACHE_ENABLED
108			`input dcache_refill_request; // Indicates data cache wants to be refilled`
109			`endif
110			`endif
111
112			`/////////////////////////////////////////////////////`
113			`// Outputs`
114			`/////////////////////////////////////////////////////`
115
116			`ifdef LM32_SINGLE_STEP_ENABLED
117			`output dc_ss; // Single-step enable`
118			`reg dc_ss;`
119			`endif
120			`output dc_re; // Remap exceptions`
121			`reg dc_re;`
122			`output bp_match; // Indicates a breakpoint has matched`
123			`wire bp_match;`
124			`output wp_match; // Indicates a watchpoint has matched`
125			`wire wp_match;`
126
127			`/////////////////////////////////////////////////////`
128			`// Internal nets and registers`
129			`/////////////////////////////////////////////////////`
130
131			`genvar i; // Loop index for generate statements`
132
133			`// Debug CSRs`
134
135			reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
136			`reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable`
137			`wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched`
138
139			reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
140			reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
141			`wire [0:watchpoints-1]wp_match_n; // Indicates if a h/w data watchpoint matched`
142
143			`wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)`
144			wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
145			wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
146
147			`ifdef LM32_SINGLE_STEP_ENABLED
148			`// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now`
149			//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
150			`integer state; // State of single-step FSM`
151			`endif
152
153			`/////////////////////////////////////////////////////`
154			`// Functions`
155			`/////////////////////////////////////////////////////`
156			`define INCLUDE_FUNCTION
157			`include "lm32_functions.v"
158
159			`/////////////////////////////////////////////////////`
160			`// Combinational Logic`
161			`/////////////////////////////////////////////////////`
162
163			`// Check for breakpoints`
164			`generate`
165			`for (i = 0; i < breakpoints; i = i + 1)`
166			`begin : bp_comb`
167			assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
168			`end`
169			`endgenerate`
170			`generate`
171			`ifdef LM32_SINGLE_STEP_ENABLED
172			`if (breakpoints > 0)`
173			assign bp_match = (\|bp_match_n) \|\| (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
174			`else`
175			assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
176			`else
177			`if (breakpoints > 0)`
178			`assign bp_match = \|bp_match_n;`
179			`else`
180			assign bp_match = `FALSE;
181			`endif
182			`endgenerate`
183
184			`// Check for watchpoints`
185			`generate`
186			`for (i = 0; i < watchpoints; i = i + 1)`
187			`begin : wp_comb`
188			`assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) \| (store_x & wpc_c[i][1]));`
189			`end`
190			`endgenerate`
191			`generate`
192			`if (watchpoints > 0)`
193			`assign wp_match = \|wp_match_n;`
194			`else`
195			assign wp_match = `FALSE;
196			`endgenerate`
197
198			`ifdef CFG_HW_DEBUG_ENABLED
199			`// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs`
200			assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) \|\| (jtag_csr_write_enable == `TRUE);
201			assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
202			assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
203			`else
204			`assign debug_csr_write_enable = csr_write_enable_x;`
205			`assign debug_csr_write_data = csr_write_data;`
206			`assign debug_csr = csr_x;`
207			`endif
208
209			`/////////////////////////////////////////////////////`
210			`// Sequential Logic`
211			`/////////////////////////////////////////////////////`
212
213			`// Breakpoint address and enable CSRs`
214			`generate`
215			`for (i = 0; i < breakpoints; i = i + 1)`
216			`begin : bp_seq`
217			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
218			`begin`
219			if (rst_i == `TRUE)
220			`begin`
221			bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
222			bp_e[i] <= `FALSE;
223			`end`
224			`else`
225			`begin`
226			if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
227			`begin`
228			bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
229			`bp_e[i] <= debug_csr_write_data[0];`
230			`end`
231			`end`
232			`end`
233			`end`
234			`endgenerate`
235
236			`// Watchpoint address and control flags CSRs`
237			`generate`
238			`for (i = 0; i < watchpoints; i = i + 1)`
239			`begin : wp_seq`
240			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
241			`begin`
242			if (rst_i == `TRUE)
243			`begin`
244			wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
245			wpc_c[i] <= `LM32_WPC_C_DISABLED;
246			`end`
247			`else`
248			`begin`
249			if (debug_csr_write_enable == `TRUE)
250			`begin`
251			if (debug_csr == `LM32_CSR_DC)
252			`wpc_c[i] <= debug_csr_write_data[3+i2:2+i2];`
253			if (debug_csr == `LM32_CSR_WP0 + i)
254			`wp[i] <= debug_csr_write_data;`
255			`end`
256			`end`
257			`end`
258			`end`
259			`endgenerate`
260
261			`// Remap exceptions control bit`
262			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
263			`begin`
264			if (rst_i == `TRUE)
265			dc_re <= `FALSE;
266			`else`
267			`begin`
268			if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
269			`dc_re <= debug_csr_write_data[1];`
270			`end`
271			`end`
272
273			`ifdef LM32_SINGLE_STEP_ENABLED
274			`// Single-step control flag`
275			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
276			`begin`
277			if (rst_i == `TRUE)
278			`begin`
279			state <= `LM32_DEBUG_SS_STATE_IDLE;
280			dc_ss <= `FALSE;
281			`end`
282			`else`
283			`begin`
284			if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
285			`begin`
286			`dc_ss <= debug_csr_write_data[0];`
287			if (debug_csr_write_data[0] == `FALSE)
288			state <= `LM32_DEBUG_SS_STATE_IDLE;
289			`else`
290			state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
291			`end`
292			`case (state)`
293			`LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
294			`begin`
295			`// Wait for eret or bret instruction to be executed`
296			if ( ( (eret_q_x == `TRUE)
297			\|\| (bret_q_x == `TRUE)
298			`)`
299			&& (stall_x == `FALSE)
300			`)`
301			state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
302			`end`
303			`LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
304			`begin`
305			`// Wait for an instruction to be executed`
306			if ((q_x == `TRUE) && (stall_x == `FALSE))
307			state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
308			`end`
309			`LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
310			`begin`
311			`// Wait for exception to be raised`
312			`ifdef CFG_DCACHE_ENABLED
313			if (dcache_refill_request == `TRUE)
314			state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
315			`else`
316			`endif
317			if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
318			`begin`
319			dc_ss <= `FALSE;
320			state <= `LM32_DEBUG_SS_STATE_RESTART;
321			`end`
322			`end`
323			`LM32_DEBUG_SS_STATE_RESTART:
324			`begin`
325			`// Watch to see if stepped instruction is restarted due to a cache miss`
326			`ifdef CFG_DCACHE_ENABLED
327			if (dcache_refill_request == `TRUE)
328			state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
329			`else`
330			`endif
331			state <= `LM32_DEBUG_SS_STATE_IDLE;
332			`end`
333			`endcase`
334			`end`
335			`end`
336			`endif
337
338			`endmodule`
339
340			`endif