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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_icache.v] - Blame information for rev 17

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// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_icache.v
// Title            : Instruction cache
// Dependencies     : lm32_include.v
// Version          : 6.1.17
// =============================================================================
 
`include "lm32_include.v"
 
`define LM32_IC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
`define LM32_IC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
`define LM32_IC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
`define LM32_IC_ADDR_IDX_RNG             addr_set_msb:addr_offset_lsb
 
`define LM32_IC_TMEM_ADDR_WIDTH          addr_set_width
`define LM32_IC_TMEM_ADDR_RNG            (`LM32_IC_TMEM_ADDR_WIDTH-1):0
`define LM32_IC_DMEM_ADDR_WIDTH          (addr_offset_width+addr_set_width)
`define LM32_IC_DMEM_ADDR_RNG            (`LM32_IC_DMEM_ADDR_WIDTH-1):0
 
`define LM32_IC_TAGS_WIDTH               (addr_tag_width+1)
`define LM32_IC_TAGS_RNG                 (`LM32_IC_TAGS_WIDTH-1):0
`define LM32_IC_TAGS_TAG_RNG             (`LM32_IC_TAGS_WIDTH-1):1
`define LM32_IC_TAGS_VALID_RNG           0
 
`define LM32_IC_STATE_RNG                3:0
`define LM32_IC_STATE_FLUSH_INIT         4'b0001
`define LM32_IC_STATE_FLUSH              4'b0010
`define LM32_IC_STATE_CHECK              4'b0100
`define LM32_IC_STATE_REFILL             4'b1000
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_icache (
    // ----- Inputs -----
    clk_i,
    rst_i,
    stall_a,
    stall_f,
    address_a,
    address_f,
    read_enable_f,
    refill_ready,
    refill_data,
    iflush,
    // ----- Outputs -----
    stall_request,
    restart_request,
    refill_request,
    refill_address,
    refilling,
    inst
    );
 
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
 
parameter associativity = 1;                            // Associativity of the cache (Number of ways)
parameter sets = 512;                                   // Number of sets
parameter bytes_per_line = 16;                          // Number of bytes per cache line
parameter base_address = 0;                             // Base address of cachable memory
parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
localparam addr_offset_width = 2;
localparam addr_set_width = 9;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
localparam addr_tag_msb = 31;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                        // Clock 
input rst_i;                                        // Reset
 
input stall_a;                                      // Stall instruction in A stage
input stall_f;                                      // Stall instruction in F stage
 
input [`LM32_PC_RNG] address_a;                     // Address of instruction in A stage
input [`LM32_PC_RNG] address_f;                     // Address of instruction in F stage
input read_enable_f;                                // Indicates if cache access is valid
 
input refill_ready;                                 // Next word of refill data is ready
input [`LM32_INSTRUCTION_RNG] refill_data;          // Data to refill the cache with
 
input iflush;                                       // Flush the cache
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
output stall_request;                               // Request to stall the pipeline
wire   stall_request;
output restart_request;                             // Request to restart instruction that caused the cache miss
reg    restart_request;
output refill_request;                              // Request to refill a cache line
wire   refill_request;
output [`LM32_PC_RNG] refill_address;               // Base address of cache refill
reg    [`LM32_PC_RNG] refill_address;
output refilling;                                   // Indicates the instruction cache is currently refilling
reg    refilling;
output [`LM32_INSTRUCTION_RNG] inst;                // Instruction read from cache
wire   [`LM32_INSTRUCTION_RNG] inst;
 
/////////////////////////////////////////////////////
// Internal nets and registers 
/////////////////////////////////////////////////////
 
wire enable;
wire [0:associativity-1] way_mem_we;
wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
 
wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
wire [`LM32_IC_TAGS_RNG] tmem_write_data;
 
reg [`LM32_IC_STATE_RNG] state;
wire flushing;
wire check;
wire refill;
 
reg [associativity-1:0] refill_way_select;
reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
wire last_refill;
reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
 
genvar i;
 
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`define  INCLUDE_FUNCTION
`include "lm32_functions.v"
 
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
 
generate
    for (i = 0; i < associativity; i = i + 1)
    begin : memories
 
// Way 0 data
lm32_ram #(
    // ----- Parameters -------
    .data_width                 (32),
    .address_width              (`LM32_IC_DMEM_ADDR_WIDTH)
  ) way_0_data_ram (
    // ----- Inputs -------
    .read_clk                   (clk_i),
    .write_clk                  (clk_i),
    .reset                      (rst_i),
    .read_address               (dmem_read_address),
    .enable_read                (enable),
    .write_address              (dmem_write_address),
    .enable_write               (`TRUE),
    .write_enable               (way_mem_we[i]),
    .write_data                 (refill_data),
    // ----- Outputs -------
    .read_data                  (way_data[i])
    );
 
// Way 0 tags
lm32_ram #(
    // ----- Parameters -------
    .data_width                 (`LM32_IC_TAGS_WIDTH),
    .address_width              (`LM32_IC_TMEM_ADDR_WIDTH)
  ) way_0_tag_ram (
    // ----- Inputs -------
    .read_clk                   (clk_i),
    .write_clk                  (clk_i),
    .reset                      (rst_i),
    .read_address               (tmem_read_address),
    .enable_read                (enable),
    .write_address              (tmem_write_address),
    .enable_write               (`TRUE),
    .write_enable               (way_mem_we[i] | flushing),
    .write_data                 (tmem_write_data),
    // ----- Outputs -------
    .read_data                  ({way_tag[i], way_valid[i]})
    );
 
    end
endgenerate
 
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
 
// Compute which ways in the cache match the address address being read
generate
    for (i = 0; i < associativity; i = i + 1)
    begin : match
assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
    end
endgenerate
 
// Select data from way that matched the address being read     
generate
    if (associativity == 1)
    begin : inst_1
assign inst = way_data[0];
    end
    else if (associativity == 2)
         begin : inst_2
assign inst = way_match[0] ? way_data[0] : way_data[1];
    end
endgenerate
 
// Compute address to use to index into the data memories
generate
    if (bytes_per_line > 4)
        begin : wadr1
assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
        end
    else
        begin : wadr2
assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
        end
endgenerate
 
assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
 
// Compute address to use to index into the tag memories                        
assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
assign tmem_write_address = flushing
                                ? flush_set
                                : refill_address[`LM32_IC_ADDR_SET_RNG];
 
// Compute signal to indicate when we are on the last refill accesses
generate
    if (bytes_per_line > 4)
        begin : lrefil1
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
        end
    else
        begin : lrefil2
assign last_refill = `TRUE;
        end
endgenerate
 
// Compute data and tag memory access enable
assign enable = (stall_a == `FALSE);
 
// Compute data and tag memory write enables
generate
    if (associativity == 1)
    begin : we_1
assign way_mem_we[0] = (refill_ready == `TRUE);
    end
    else
    begin : we_2
assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
    end
endgenerate
 
// On the last refill cycle set the valid bit, for all other writes it should be cleared
assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
 
// Signals that indicate which state we are in
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
 
assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE);
assign stall_request = (check == `FALSE);
assign refill_request = (refill == `TRUE);
 
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
 
// Record way selected for replacement on a cache miss
generate
    if (associativity >= 2)
    begin : way_select
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
    else
    begin
        if (miss == `TRUE)
            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
    end
end
    end
endgenerate
 
// Record whether we are refilling
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
        refilling <= `FALSE;
    else
        refilling <= refill;
end
 
// Instruction cache control FSM
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        state <= `LM32_IC_STATE_FLUSH_INIT;
        flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
        refill_address <= {`LM32_PC_WIDTH{1'bx}};
        restart_request <= `FALSE;
    end
    else
    begin
        case (state)
 
        // Flush the cache for the first time after reset
        `LM32_IC_STATE_FLUSH_INIT:
        begin
            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
                state <= `LM32_IC_STATE_CHECK;
            flush_set <= flush_set - 1'b1;
        end
 
        // Flush the cache in response to an write to the ICC CSR
        `LM32_IC_STATE_FLUSH:
        begin
            if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
                state <= `LM32_IC_STATE_REFILL;
            flush_set <= flush_set - 1'b1;
        end
 
        // Check for cache misses
        `LM32_IC_STATE_CHECK:
        begin
            if (stall_a == `FALSE)
                restart_request <= `FALSE;
            if (iflush == `TRUE)
            begin
                refill_address <= address_f;
                state <= `LM32_IC_STATE_FLUSH;
            end
            else if (miss == `TRUE)
            begin
                refill_address <= address_f;
                state <= `LM32_IC_STATE_REFILL;
            end
        end
 
        // Refill a cache line
        `LM32_IC_STATE_REFILL:
        begin
            if (refill_ready == `TRUE)
            begin
                if (last_refill == `TRUE)
                begin
                    restart_request <= `TRUE;
                    state <= `LM32_IC_STATE_CHECK;
                end
            end
        end
 
        endcase
    end
end
 
generate
    if (bytes_per_line > 4)
    begin : refilof1
// Refill offset
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
        refill_offset <= {addr_offset_width{1'b0}};
    else
    begin
        case (state)
 
        // Check for cache misses
        `LM32_IC_STATE_CHECK:
        begin
            if (iflush == `TRUE)
                refill_offset <= {addr_offset_width{1'b0}};
            else if (miss == `TRUE)
                refill_offset <= {addr_offset_width{1'b0}};
        end
 
        // Refill a cache line
        `LM32_IC_STATE_REFILL:
        begin
            if (refill_ready == `TRUE)
                refill_offset <= refill_offset + 1'b1;
        end
 
        endcase
    end
end
    end
endgenerate
 
endmodule

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_icache.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	alirezamon	`// =============================================================================`
2			`// COPYRIGHT NOTICE`
3			`// Copyright 2006 (c) Lattice Semiconductor Corporation`
4			`// ALL RIGHTS RESERVED`
5			`// This confidential and proprietary software may be used only as authorised by`
6			`// a licensing agreement from Lattice Semiconductor Corporation.`
7			`// The entire notice above must be reproduced on all authorized copies and`
8			`// copies may only be made to the extent permitted by a licensing agreement from`
9			`// Lattice Semiconductor Corporation.`
10			`//`
11			`// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)`
12			`// 5555 NE Moore Court 408-826-6000 (other locations)`
13			`// Hillsboro, OR 97124 web : http://www.latticesemi.com/`
14			`// U.S.A email: techsupport@latticesemi.com`
15			`// =============================================================================/`
16			`// FILE DETAILS`
17			`// Project : LatticeMico32`
18			`// File : lm32_icache.v`
19			`// Title : Instruction cache`
20			`// Dependencies : lm32_include.v`
21			`// Version : 6.1.17`
22			`// =============================================================================`
23
24			`include "lm32_include.v"
25
26			`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
27			`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
28			`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
29			`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
30
31			`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
32			`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
33			`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
34			`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
35
36			`define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
37			`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
38			`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
39			`define LM32_IC_TAGS_VALID_RNG 0
40
41			`define LM32_IC_STATE_RNG 3:0
42			`define LM32_IC_STATE_FLUSH_INIT 4'b0001
43			`define LM32_IC_STATE_FLUSH 4'b0010
44			`define LM32_IC_STATE_CHECK 4'b0100
45			`define LM32_IC_STATE_REFILL 4'b1000
46
47			`/////////////////////////////////////////////////////`
48			`// Module interface`
49			`/////////////////////////////////////////////////////`
50
51			`module lm32_icache (`
52			`// ----- Inputs -----`
53			`clk_i,`
54			`rst_i,`
55			`stall_a,`
56			`stall_f,`
57			`address_a,`
58			`address_f,`
59			`read_enable_f,`
60			`refill_ready,`
61			`refill_data,`
62			`iflush,`
63			`// ----- Outputs -----`
64			`stall_request,`
65			`restart_request,`
66			`refill_request,`
67			`refill_address,`
68			`refilling,`
69			`inst`
70			`);`
71
72			`/////////////////////////////////////////////////////`
73			`// Parameters`
74			`/////////////////////////////////////////////////////`
75
76			`parameter associativity = 1; // Associativity of the cache (Number of ways)`
77			`parameter sets = 512; // Number of sets`
78			`parameter bytes_per_line = 16; // Number of bytes per cache line`
79			`parameter base_address = 0; // Base address of cachable memory`
80			`parameter limit = 0; // Limit (highest address) of cachable memory`
81
82			`localparam addr_offset_width = 2;`
83			`localparam addr_set_width = 9;`
84			`localparam addr_offset_lsb = 2;`
85			`localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);`
86			`localparam addr_set_lsb = (addr_offset_msb+1);`
87			`localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);`
88			`localparam addr_tag_lsb = (addr_set_msb+1);`
89			`localparam addr_tag_msb = 31;`
90			`localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);`
91
92			`/////////////////////////////////////////////////////`
93			`// Inputs`
94			`/////////////////////////////////////////////////////`
95
96			`input clk_i; // Clock`
97			`input rst_i; // Reset`
98
99			`input stall_a; // Stall instruction in A stage`
100			`input stall_f; // Stall instruction in F stage`
101
102			input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
103			input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
104			`input read_enable_f; // Indicates if cache access is valid`
105
106			`input refill_ready; // Next word of refill data is ready`
107			input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
108
109			`input iflush; // Flush the cache`
110
111			`/////////////////////////////////////////////////////`
112			`// Outputs`
113			`/////////////////////////////////////////////////////`
114
115			`output stall_request; // Request to stall the pipeline`
116			`wire stall_request;`
117			`output restart_request; // Request to restart instruction that caused the cache miss`
118			`reg restart_request;`
119			`output refill_request; // Request to refill a cache line`
120			`wire refill_request;`
121			output [`LM32_PC_RNG] refill_address; // Base address of cache refill
122			reg [`LM32_PC_RNG] refill_address;
123			`output refilling; // Indicates the instruction cache is currently refilling`
124			`reg refilling;`
125			output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
126			wire [`LM32_INSTRUCTION_RNG] inst;
127
128			`/////////////////////////////////////////////////////`
129			`// Internal nets and registers`
130			`/////////////////////////////////////////////////////`
131
132			`wire enable;`
133			`wire [0:associativity-1] way_mem_we;`
134			wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
135			wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
136			`wire [0:associativity-1] way_valid;`
137			`wire [0:associativity-1] way_match;`
138			`wire miss;`
139
140			wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
141			wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
142			wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
143			wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
144			wire [`LM32_IC_TAGS_RNG] tmem_write_data;
145
146			reg [`LM32_IC_STATE_RNG] state;
147			`wire flushing;`
148			`wire check;`
149			`wire refill;`
150
151			`reg [associativity-1:0] refill_way_select;`
152			reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
153			`wire last_refill;`
154			reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
155
156			`genvar i;`
157
158			`/////////////////////////////////////////////////////`
159			`// Functions`
160			`/////////////////////////////////////////////////////`
161			`define INCLUDE_FUNCTION
162			`include "lm32_functions.v"
163
164			`/////////////////////////////////////////////////////`
165			`// Instantiations`
166			`/////////////////////////////////////////////////////`
167
168			`generate`
169			`for (i = 0; i < associativity; i = i + 1)`
170			`begin : memories`
171
172			`// Way 0 data`
173			`lm32_ram #(`
174			`// ----- Parameters -------`
175			`.data_width (32),`
176			.address_width (`LM32_IC_DMEM_ADDR_WIDTH)
177			`) way_0_data_ram (`
178			`// ----- Inputs -------`
179			`.read_clk (clk_i),`
180			`.write_clk (clk_i),`
181			`.reset (rst_i),`
182			`.read_address (dmem_read_address),`
183			`.enable_read (enable),`
184			`.write_address (dmem_write_address),`
185			.enable_write (`TRUE),
186			`.write_enable (way_mem_we[i]),`
187			`.write_data (refill_data),`
188			`// ----- Outputs -------`
189			`.read_data (way_data[i])`
190			`);`
191
192			`// Way 0 tags`
193			`lm32_ram #(`
194			`// ----- Parameters -------`
195			.data_width (`LM32_IC_TAGS_WIDTH),
196			.address_width (`LM32_IC_TMEM_ADDR_WIDTH)
197			`) way_0_tag_ram (`
198			`// ----- Inputs -------`
199			`.read_clk (clk_i),`
200			`.write_clk (clk_i),`
201			`.reset (rst_i),`
202			`.read_address (tmem_read_address),`
203			`.enable_read (enable),`
204			`.write_address (tmem_write_address),`
205			.enable_write (`TRUE),
206			`.write_enable (way_mem_we[i] \| flushing),`
207			`.write_data (tmem_write_data),`
208			`// ----- Outputs -------`
209			`.read_data ({way_tag[i], way_valid[i]})`
210			`);`
211
212			`end`
213			`endgenerate`
214
215			`/////////////////////////////////////////////////////`
216			`// Combinational logic`
217			`/////////////////////////////////////////////////////`
218
219			`// Compute which ways in the cache match the address address being read`
220			`generate`
221			`for (i = 0; i < associativity; i = i + 1)`
222			`begin : match`
223			assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
224			`end`
225			`endgenerate`
226
227			`// Select data from way that matched the address being read`
228			`generate`
229			`if (associativity == 1)`
230			`begin : inst_1`
231			`assign inst = way_data[0];`
232			`end`
233			`else if (associativity == 2)`
234			`begin : inst_2`
235			`assign inst = way_match[0] ? way_data[0] : way_data[1];`
236			`end`
237			`endgenerate`
238
239			`// Compute address to use to index into the data memories`
240			`generate`
241			`if (bytes_per_line > 4)`
242			`begin : wadr1`
243			assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
244			`end`
245			`else`
246			`begin : wadr2`
247			assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
248			`end`
249			`endgenerate`
250
251			assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
252
253			`// Compute address to use to index into the tag memories`
254			assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
255			`assign tmem_write_address = flushing`
256			`? flush_set`
257			: refill_address[`LM32_IC_ADDR_SET_RNG];
258
259			`// Compute signal to indicate when we are on the last refill accesses`
260			`generate`
261			`if (bytes_per_line > 4)`
262			`begin : lrefil1`
263			`assign last_refill = refill_offset == {addr_offset_width{1'b1}};`
264			`end`
265			`else`
266			`begin : lrefil2`
267			assign last_refill = `TRUE;
268			`end`
269			`endgenerate`
270
271			`// Compute data and tag memory access enable`
272			assign enable = (stall_a == `FALSE);
273
274			`// Compute data and tag memory write enables`
275			`generate`
276			`if (associativity == 1)`
277			`begin : we_1`
278			assign way_mem_we[0] = (refill_ready == `TRUE);
279			`end`
280			`else`
281			`begin : we_2`
282			assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
283			assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
284			`end`
285			`endgenerate`
286
287			`// On the last refill cycle set the valid bit, for all other writes it should be cleared`
288			assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
289			assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
290
291			`// Signals that indicate which state we are in`
292			`assign flushing = \|state[1:0];`
293			`assign check = state[2];`
294			`assign refill = state[3];`
295
296			assign miss = (~(\|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE);
297			assign stall_request = (check == `FALSE);
298			assign refill_request = (refill == `TRUE);
299
300			`/////////////////////////////////////////////////////`
301			`// Sequential logic`
302			`/////////////////////////////////////////////////////`
303
304			`// Record way selected for replacement on a cache miss`
305			`generate`
306			`if (associativity >= 2)`
307			`begin : way_select`
308			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
309			`begin`
310			if (rst_i == `TRUE)
311			`refill_way_select <= {{associativity-1{1'b0}}, 1'b1};`
312			`else`
313			`begin`
314			if (miss == `TRUE)
315			`refill_way_select <= {refill_way_select[0], refill_way_select[1]};`
316			`end`
317			`end`
318			`end`
319			`endgenerate`
320
321			`// Record whether we are refilling`
322			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
323			`begin`
324			if (rst_i == `TRUE)
325			refilling <= `FALSE;
326			`else`
327			`refilling <= refill;`
328			`end`
329
330			`// Instruction cache control FSM`
331			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
332			`begin`
333			if (rst_i == `TRUE)
334			`begin`
335			state <= `LM32_IC_STATE_FLUSH_INIT;
336			flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
337			refill_address <= {`LM32_PC_WIDTH{1'bx}};
338			restart_request <= `FALSE;
339			`end`
340			`else`
341			`begin`
342			`case (state)`
343
344			`// Flush the cache for the first time after reset`
345			`LM32_IC_STATE_FLUSH_INIT:
346			`begin`
347			if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
348			state <= `LM32_IC_STATE_CHECK;
349			`flush_set <= flush_set - 1'b1;`
350			`end`
351
352			`// Flush the cache in response to an write to the ICC CSR`
353			`LM32_IC_STATE_FLUSH:
354			`begin`
355			if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
356			state <= `LM32_IC_STATE_REFILL;
357			`flush_set <= flush_set - 1'b1;`
358			`end`
359
360			`// Check for cache misses`
361			`LM32_IC_STATE_CHECK:
362			`begin`
363			if (stall_a == `FALSE)
364			restart_request <= `FALSE;
365			if (iflush == `TRUE)
366			`begin`
367			`refill_address <= address_f;`
368			state <= `LM32_IC_STATE_FLUSH;
369			`end`
370			else if (miss == `TRUE)
371			`begin`
372			`refill_address <= address_f;`
373			state <= `LM32_IC_STATE_REFILL;
374			`end`
375			`end`
376
377			`// Refill a cache line`
378			`LM32_IC_STATE_REFILL:
379			`begin`
380			if (refill_ready == `TRUE)
381			`begin`
382			if (last_refill == `TRUE)
383			`begin`
384			restart_request <= `TRUE;
385			state <= `LM32_IC_STATE_CHECK;
386			`end`
387			`end`
388			`end`
389
390			`endcase`
391			`end`
392			`end`
393
394			`generate`
395			`if (bytes_per_line > 4)`
396			`begin : refilof1`
397			`// Refill offset`
398			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
399			`begin`
400			if (rst_i == `TRUE)
401			`refill_offset <= {addr_offset_width{1'b0}};`
402			`else`
403			`begin`
404			`case (state)`
405
406			`// Check for cache misses`
407			`LM32_IC_STATE_CHECK:
408			`begin`
409			if (iflush == `TRUE)
410			`refill_offset <= {addr_offset_width{1'b0}};`
411			else if (miss == `TRUE)
412			`refill_offset <= {addr_offset_width{1'b0}};`
413			`end`
414
415			`// Refill a cache line`
416			`LM32_IC_STATE_REFILL:
417			`begin`
418			if (refill_ready == `TRUE)
419			`refill_offset <= refill_offset + 1'b1;`
420			`end`
421
422			`endcase`
423			`end`
424			`end`
425			`end`
426			`endgenerate`
427
428			`endmodule`