1 |
17 |
alirezamon |
// =============================================================================
|
2 |
|
|
// COPYRIGHT NOTICE
|
3 |
|
|
// Copyright 2006 (c) Lattice Semiconductor Corporation
|
4 |
|
|
// ALL RIGHTS RESERVED
|
5 |
|
|
// This confidential and proprietary software may be used only as authorised by
|
6 |
|
|
// a licensing agreement from Lattice Semiconductor Corporation.
|
7 |
|
|
// The entire notice above must be reproduced on all authorized copies and
|
8 |
|
|
// copies may only be made to the extent permitted by a licensing agreement from
|
9 |
|
|
// Lattice Semiconductor Corporation.
|
10 |
|
|
//
|
11 |
|
|
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
|
12 |
|
|
// 5555 NE Moore Court 408-826-6000 (other locations)
|
13 |
|
|
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
|
14 |
|
|
// U.S.A email: techsupport@latticesemi.com
|
15 |
|
|
// =============================================================================/
|
16 |
|
|
// FILE DETAILS
|
17 |
|
|
// Project : LatticeMico32
|
18 |
|
|
// File : lm32_instruction_unit.v
|
19 |
|
|
// Title : Instruction unit
|
20 |
|
|
// Dependencies : lm32_include.v
|
21 |
|
|
// Version : 6.1.17
|
22 |
|
|
// =============================================================================
|
23 |
|
|
|
24 |
|
|
`include "lm32_include.v"
|
25 |
|
|
|
26 |
|
|
/////////////////////////////////////////////////////
|
27 |
|
|
// Module interface
|
28 |
|
|
/////////////////////////////////////////////////////
|
29 |
|
|
|
30 |
|
|
module lm32_instruction_unit (
|
31 |
|
|
// ----- Inputs -------
|
32 |
|
|
clk_i,
|
33 |
|
|
rst_i,
|
34 |
|
|
// From pipeline
|
35 |
|
|
stall_a,
|
36 |
|
|
stall_f,
|
37 |
|
|
stall_d,
|
38 |
|
|
stall_x,
|
39 |
|
|
stall_m,
|
40 |
|
|
valid_f,
|
41 |
|
|
kill_f,
|
42 |
|
|
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|
43 |
|
|
branch_taken_x,
|
44 |
|
|
branch_target_x,
|
45 |
|
|
`endif
|
46 |
|
|
branch_taken_m,
|
47 |
|
|
branch_target_m,
|
48 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
49 |
|
|
iflush,
|
50 |
|
|
`endif
|
51 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
52 |
|
|
dcache_restart_request,
|
53 |
|
|
dcache_refill_request,
|
54 |
|
|
dcache_refilling,
|
55 |
|
|
`endif
|
56 |
|
|
`ifdef CFG_IWB_ENABLED
|
57 |
|
|
// From Wishbone
|
58 |
|
|
i_dat_i,
|
59 |
|
|
i_ack_i,
|
60 |
|
|
i_err_i,
|
61 |
|
|
i_rty_i,
|
62 |
|
|
`endif
|
63 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
64 |
|
|
jtag_read_enable,
|
65 |
|
|
jtag_write_enable,
|
66 |
|
|
jtag_write_data,
|
67 |
|
|
jtag_address,
|
68 |
|
|
`endif
|
69 |
|
|
// ----- Outputs -------
|
70 |
|
|
// To pipeline
|
71 |
|
|
pc_f,
|
72 |
|
|
pc_d,
|
73 |
|
|
pc_x,
|
74 |
|
|
pc_m,
|
75 |
|
|
pc_w,
|
76 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
77 |
|
|
icache_stall_request,
|
78 |
|
|
icache_restart_request,
|
79 |
|
|
icache_refill_request,
|
80 |
|
|
icache_refilling,
|
81 |
|
|
`endif
|
82 |
|
|
`ifdef CFG_IWB_ENABLED
|
83 |
|
|
// To Wishbone
|
84 |
|
|
i_dat_o,
|
85 |
|
|
i_adr_o,
|
86 |
|
|
i_cyc_o,
|
87 |
|
|
i_sel_o,
|
88 |
|
|
i_stb_o,
|
89 |
|
|
i_we_o,
|
90 |
|
|
i_cti_o,
|
91 |
|
|
i_lock_o,
|
92 |
|
|
i_bte_o,
|
93 |
|
|
`endif
|
94 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
95 |
|
|
jtag_read_data,
|
96 |
|
|
jtag_access_complete,
|
97 |
|
|
`endif
|
98 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
99 |
|
|
bus_error_d,
|
100 |
|
|
`endif
|
101 |
|
|
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
|
102 |
|
|
instruction_f,
|
103 |
|
|
`endif
|
104 |
|
|
instruction_d
|
105 |
|
|
);
|
106 |
|
|
|
107 |
|
|
/////////////////////////////////////////////////////
|
108 |
|
|
// Parameters
|
109 |
|
|
/////////////////////////////////////////////////////
|
110 |
|
|
|
111 |
|
|
parameter associativity = 1; // Associativity of the cache (Number of ways)
|
112 |
|
|
parameter sets = 512; // Number of sets
|
113 |
|
|
parameter bytes_per_line = 16; // Number of bytes per cache line
|
114 |
|
|
parameter base_address = 0; // Base address of cachable memory
|
115 |
|
|
parameter limit = 0; // Limit (highest address) of cachable memory
|
116 |
|
|
|
117 |
|
|
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
|
118 |
|
|
//localparam addr_offset_width = (bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2);
|
119 |
|
|
localparam addr_offset_width = 2;
|
120 |
|
|
localparam addr_offset_lsb = 2;
|
121 |
|
|
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
|
122 |
|
|
|
123 |
|
|
/////////////////////////////////////////////////////
|
124 |
|
|
// Inputs
|
125 |
|
|
/////////////////////////////////////////////////////
|
126 |
|
|
|
127 |
|
|
input clk_i; // Clock
|
128 |
|
|
input rst_i; // Reset
|
129 |
|
|
|
130 |
|
|
input stall_a; // Stall A stage instruction
|
131 |
|
|
input stall_f; // Stall F stage instruction
|
132 |
|
|
input stall_d; // Stall D stage instruction
|
133 |
|
|
input stall_x; // Stall X stage instruction
|
134 |
|
|
input stall_m; // Stall M stage instruction
|
135 |
|
|
input valid_f; // Instruction in F stage is valid
|
136 |
|
|
input kill_f; // Kill instruction in F stage
|
137 |
|
|
|
138 |
|
|
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|
139 |
|
|
input branch_taken_x; // Branch instruction in X stage is taken
|
140 |
|
|
input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
|
141 |
|
|
`endif
|
142 |
|
|
input branch_taken_m; // Branch instruction in M stage is taken
|
143 |
|
|
input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
|
144 |
|
|
|
145 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
146 |
|
|
input iflush; // Flush instruction cache
|
147 |
|
|
`endif
|
148 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
149 |
|
|
input dcache_restart_request; // Restart instruction that caused a data cache miss
|
150 |
|
|
input dcache_refill_request; // Request to refill data cache
|
151 |
|
|
input dcache_refilling;
|
152 |
|
|
`endif
|
153 |
|
|
|
154 |
|
|
`ifdef CFG_IWB_ENABLED
|
155 |
|
|
input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
|
156 |
|
|
input i_ack_i; // Instruction Wishbone interface acknowledgement
|
157 |
|
|
input i_err_i; // Instruction Wishbone interface error
|
158 |
|
|
input i_rty_i; // Instruction Wishbone interface retry
|
159 |
|
|
`endif
|
160 |
|
|
|
161 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
162 |
|
|
input jtag_read_enable; // JTAG read memory request
|
163 |
|
|
input jtag_write_enable; // JTAG write memory request
|
164 |
|
|
input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
|
165 |
|
|
input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
|
166 |
|
|
`endif
|
167 |
|
|
|
168 |
|
|
/////////////////////////////////////////////////////
|
169 |
|
|
// Outputs
|
170 |
|
|
/////////////////////////////////////////////////////
|
171 |
|
|
|
172 |
|
|
output [`LM32_PC_RNG] pc_f; // F stage PC
|
173 |
|
|
reg [`LM32_PC_RNG] pc_f;
|
174 |
|
|
output [`LM32_PC_RNG] pc_d; // D stage PC
|
175 |
|
|
reg [`LM32_PC_RNG] pc_d;
|
176 |
|
|
output [`LM32_PC_RNG] pc_x; // X stage PC
|
177 |
|
|
reg [`LM32_PC_RNG] pc_x;
|
178 |
|
|
output [`LM32_PC_RNG] pc_m; // M stage PC
|
179 |
|
|
reg [`LM32_PC_RNG] pc_m;
|
180 |
|
|
output [`LM32_PC_RNG] pc_w; // W stage PC
|
181 |
|
|
reg [`LM32_PC_RNG] pc_w;
|
182 |
|
|
|
183 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
184 |
|
|
output icache_stall_request; // Instruction cache stall request
|
185 |
|
|
wire icache_stall_request;
|
186 |
|
|
output icache_restart_request; // Request to restart instruction that cached instruction cache miss
|
187 |
|
|
wire icache_restart_request;
|
188 |
|
|
output icache_refill_request; // Instruction cache refill request
|
189 |
|
|
wire icache_refill_request;
|
190 |
|
|
output icache_refilling; // Indicates the icache is refilling
|
191 |
|
|
wire icache_refilling;
|
192 |
|
|
`endif
|
193 |
|
|
|
194 |
|
|
`ifdef CFG_IWB_ENABLED
|
195 |
|
|
output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
|
196 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
197 |
|
|
reg [`LM32_WORD_RNG] i_dat_o;
|
198 |
|
|
`else
|
199 |
|
|
wire [`LM32_WORD_RNG] i_dat_o;
|
200 |
|
|
`endif
|
201 |
|
|
output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
|
202 |
|
|
reg [`LM32_WORD_RNG] i_adr_o;
|
203 |
|
|
output i_cyc_o; // Instruction Wishbone interface cycle
|
204 |
|
|
reg i_cyc_o;
|
205 |
|
|
output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
|
206 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
207 |
|
|
reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
|
208 |
|
|
`else
|
209 |
|
|
wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
|
210 |
|
|
`endif
|
211 |
|
|
output i_stb_o; // Instruction Wishbone interface strobe
|
212 |
|
|
reg i_stb_o;
|
213 |
|
|
output i_we_o; // Instruction Wishbone interface write enable
|
214 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
215 |
|
|
reg i_we_o;
|
216 |
|
|
`else
|
217 |
|
|
wire i_we_o;
|
218 |
|
|
`endif
|
219 |
|
|
output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
|
220 |
|
|
reg [`LM32_CTYPE_RNG] i_cti_o;
|
221 |
|
|
output i_lock_o; // Instruction Wishbone interface lock bus
|
222 |
|
|
reg i_lock_o;
|
223 |
|
|
output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
|
224 |
|
|
wire [`LM32_BTYPE_RNG] i_bte_o;
|
225 |
|
|
`endif
|
226 |
|
|
|
227 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
228 |
|
|
output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
|
229 |
|
|
reg [`LM32_BYTE_RNG] jtag_read_data;
|
230 |
|
|
output jtag_access_complete; // Requested memory access by JTAG interface is complete
|
231 |
|
|
wire jtag_access_complete;
|
232 |
|
|
`endif
|
233 |
|
|
|
234 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
235 |
|
|
output bus_error_d; // Indicates a bus error occured while fetching the instruction
|
236 |
|
|
reg bus_error_d;
|
237 |
|
|
`endif
|
238 |
|
|
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
|
239 |
|
|
output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
|
240 |
|
|
wire [`LM32_INSTRUCTION_RNG] instruction_f;
|
241 |
|
|
`endif
|
242 |
|
|
output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
|
243 |
|
|
reg [`LM32_INSTRUCTION_RNG] instruction_d;
|
244 |
|
|
|
245 |
|
|
/////////////////////////////////////////////////////
|
246 |
|
|
// Internal nets and registers
|
247 |
|
|
/////////////////////////////////////////////////////
|
248 |
|
|
|
249 |
|
|
reg [`LM32_PC_RNG] pc_a; // A stage PC
|
250 |
|
|
|
251 |
|
|
`ifdef LM32_CACHE_ENABLED
|
252 |
|
|
reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
|
253 |
|
|
`endif
|
254 |
|
|
|
255 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
256 |
|
|
wire icache_read_enable_f; // Indicates if instruction cache miss is valid
|
257 |
|
|
wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
|
258 |
|
|
reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
|
259 |
|
|
reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
|
260 |
|
|
wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
|
261 |
|
|
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
|
262 |
|
|
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
|
263 |
|
|
wire last_word; // Indicates if this is the last word in the cache line
|
264 |
|
|
wire [`LM32_PC_RNG] first_address; // First cache refill address
|
265 |
|
|
`else
|
266 |
|
|
`ifdef CFG_IWB_ENABLED
|
267 |
|
|
reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
|
268 |
|
|
`endif
|
269 |
|
|
`endif
|
270 |
|
|
`ifdef CFG_IROM_ENABLED
|
271 |
|
|
wire irom_select_a; // Indicates if A stage PC maps to a ROM address
|
272 |
|
|
reg irom_select_f; // Indicates if F stage PC maps to a ROM address
|
273 |
|
|
wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
|
274 |
|
|
`endif
|
275 |
|
|
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
|
276 |
|
|
`else
|
277 |
|
|
wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
|
278 |
|
|
`endif
|
279 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
280 |
|
|
reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
|
281 |
|
|
`endif
|
282 |
|
|
|
283 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
284 |
|
|
reg jtag_access; // Indicates if a JTAG WB access is in progress
|
285 |
|
|
`endif
|
286 |
|
|
|
287 |
|
|
/////////////////////////////////////////////////////
|
288 |
|
|
// Functions
|
289 |
|
|
/////////////////////////////////////////////////////
|
290 |
|
|
`define INCLUDE_FUNCTION
|
291 |
|
|
`include "lm32_functions.v"
|
292 |
|
|
|
293 |
|
|
/////////////////////////////////////////////////////
|
294 |
|
|
// Instantiations
|
295 |
|
|
/////////////////////////////////////////////////////
|
296 |
|
|
|
297 |
|
|
// Instruction ROM
|
298 |
|
|
`ifdef CFG_IROM_ENABLED
|
299 |
|
|
pmi_ram_dp #(
|
300 |
|
|
// ----- Parameters -------
|
301 |
|
|
.pmi_wr_addr_depth (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
|
302 |
|
|
.pmi_wr_addr_width ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
|
303 |
|
|
.pmi_wr_data_width (`LM32_INSTRUCTION_WIDTH),
|
304 |
|
|
.pmi_rd_addr_depth (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
|
305 |
|
|
.pmi_rd_addr_width ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
|
306 |
|
|
.pmi_rd_data_width (`LM32_INSTRUCTION_WIDTH),
|
307 |
|
|
.pmi_regmode ("noreg"),
|
308 |
|
|
.pmi_gsr ("enable"),
|
309 |
|
|
.pmi_resetmode ("async"),
|
310 |
|
|
.pmi_init_file (`CFG_IROM_INIT_FILE),
|
311 |
|
|
.pmi_init_file_format ("hex"),
|
312 |
|
|
.module_type ("pmi_ram_dp")
|
313 |
|
|
) ram (
|
314 |
|
|
// ----- Inputs -------
|
315 |
|
|
.RdClock (clk_i),
|
316 |
|
|
.WrClock (`FALSE),
|
317 |
|
|
.Reset (rst_i),
|
318 |
|
|
.Data ({32{1'b0}}),
|
319 |
|
|
.RdAddress (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
|
320 |
|
|
.WrAddress ({(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1){1'b0}}),
|
321 |
|
|
.RdClockEn (~stall_a),
|
322 |
|
|
.WrClockEn (`FALSE),
|
323 |
|
|
.WE (`FALSE),
|
324 |
|
|
// ----- Outputs -------
|
325 |
|
|
.Q (irom_data_f)
|
326 |
|
|
);
|
327 |
|
|
`endif
|
328 |
|
|
|
329 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
330 |
|
|
// Instruction cache
|
331 |
|
|
lm32_icache #(
|
332 |
|
|
.associativity (associativity),
|
333 |
|
|
.sets (sets),
|
334 |
|
|
.bytes_per_line (bytes_per_line),
|
335 |
|
|
.base_address (base_address),
|
336 |
|
|
.limit (limit)
|
337 |
|
|
) icache (
|
338 |
|
|
// ----- Inputs -----
|
339 |
|
|
.clk_i (clk_i),
|
340 |
|
|
.rst_i (rst_i),
|
341 |
|
|
.stall_a (stall_a),
|
342 |
|
|
.stall_f (stall_f),
|
343 |
|
|
.address_a (pc_a),
|
344 |
|
|
.address_f (pc_f),
|
345 |
|
|
.read_enable_f (icache_read_enable_f),
|
346 |
|
|
.refill_ready (icache_refill_ready),
|
347 |
|
|
.refill_data (icache_refill_data),
|
348 |
|
|
.iflush (iflush),
|
349 |
|
|
// ----- Outputs -----
|
350 |
|
|
.stall_request (icache_stall_request),
|
351 |
|
|
.restart_request (icache_restart_request),
|
352 |
|
|
.refill_request (icache_refill_request),
|
353 |
|
|
.refill_address (icache_refill_address),
|
354 |
|
|
.refilling (icache_refilling),
|
355 |
|
|
.inst (icache_data_f)
|
356 |
|
|
);
|
357 |
|
|
`endif
|
358 |
|
|
|
359 |
|
|
/////////////////////////////////////////////////////
|
360 |
|
|
// Combinational Logic
|
361 |
|
|
/////////////////////////////////////////////////////
|
362 |
|
|
|
363 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
364 |
|
|
// Generate signal that indicates when instruction cache misses are valid
|
365 |
|
|
assign icache_read_enable_f = (valid_f == `TRUE)
|
366 |
|
|
&& (kill_f == `FALSE)
|
367 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
368 |
|
|
&& (dcache_restart_request == `FALSE)
|
369 |
|
|
`endif
|
370 |
|
|
`ifdef CFG_IROM_ENABLED
|
371 |
|
|
&& (irom_select_f == `FALSE)
|
372 |
|
|
`endif
|
373 |
|
|
;
|
374 |
|
|
`endif
|
375 |
|
|
|
376 |
|
|
// Compute address of next instruction to fetch
|
377 |
|
|
always @(*)
|
378 |
|
|
begin
|
379 |
|
|
// The request from the latest pipeline stage must take priority
|
380 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
381 |
|
|
if (dcache_restart_request == `TRUE)
|
382 |
|
|
pc_a = restart_address;
|
383 |
|
|
else
|
384 |
|
|
`endif
|
385 |
|
|
if (branch_taken_m == `TRUE)
|
386 |
|
|
pc_a = branch_target_m;
|
387 |
|
|
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|
388 |
|
|
else if (branch_taken_x == `TRUE)
|
389 |
|
|
pc_a = branch_target_x;
|
390 |
|
|
`endif
|
391 |
|
|
else
|
392 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
393 |
|
|
if (icache_restart_request == `TRUE)
|
394 |
|
|
pc_a = restart_address;
|
395 |
|
|
else
|
396 |
|
|
`endif
|
397 |
|
|
pc_a = pc_f + 1'b1;
|
398 |
|
|
end
|
399 |
|
|
|
400 |
|
|
// Select where instruction should be fetched from
|
401 |
|
|
`ifdef CFG_IROM_ENABLED
|
402 |
|
|
assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
|
403 |
|
|
`endif
|
404 |
|
|
|
405 |
|
|
// Select instruction from selected source
|
406 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
407 |
|
|
`ifdef CFG_IROM_ENABLED
|
408 |
|
|
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
|
409 |
|
|
`else
|
410 |
|
|
assign instruction_f = icache_data_f;
|
411 |
|
|
`endif
|
412 |
|
|
`else
|
413 |
|
|
`ifdef CFG_IROM_ENABLED
|
414 |
|
|
`ifdef CFG_IWB_ENABLED
|
415 |
|
|
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
|
416 |
|
|
`else
|
417 |
|
|
assign instruction_f = irom_data_f;
|
418 |
|
|
`endif
|
419 |
|
|
`else
|
420 |
|
|
assign instruction_f = wb_data_f;
|
421 |
|
|
`endif
|
422 |
|
|
`endif
|
423 |
|
|
|
424 |
|
|
// Unused/constant Wishbone signals
|
425 |
|
|
`ifdef CFG_IWB_ENABLED
|
426 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
427 |
|
|
`else
|
428 |
|
|
assign i_dat_o = 32'd0;
|
429 |
|
|
assign i_we_o = `FALSE;
|
430 |
|
|
assign i_sel_o = 4'b1111;
|
431 |
|
|
`endif
|
432 |
|
|
assign i_bte_o = `LM32_BTYPE_LINEAR;
|
433 |
|
|
`endif
|
434 |
|
|
|
435 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
436 |
|
|
// Determine parameters for next cache refill Wishbone access
|
437 |
|
|
// generate
|
438 |
|
|
// case (bytes_per_line)
|
439 |
|
|
// 4:
|
440 |
|
|
// begin
|
441 |
|
|
// assign first_cycle_type = `LM32_CTYPE_END;
|
442 |
|
|
// assign next_cycle_type = `LM32_CTYPE_END;
|
443 |
|
|
// assign last_word = `TRUE;
|
444 |
|
|
// assign first_address = icache_refill_address;
|
445 |
|
|
// end
|
446 |
|
|
// 8:
|
447 |
|
|
// begin
|
448 |
|
|
// assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
449 |
|
|
// assign next_cycle_type = `LM32_CTYPE_END;
|
450 |
|
|
// assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
|
451 |
|
|
// assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
|
452 |
|
|
// end
|
453 |
|
|
// 16:
|
454 |
|
|
// begin
|
455 |
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
456 |
|
|
assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
|
457 |
|
|
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
|
458 |
|
|
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
|
459 |
|
|
// end
|
460 |
|
|
// endcase
|
461 |
|
|
// endgenerate
|
462 |
|
|
`endif
|
463 |
|
|
|
464 |
|
|
/////////////////////////////////////////////////////
|
465 |
|
|
// Sequential Logic
|
466 |
|
|
/////////////////////////////////////////////////////
|
467 |
|
|
|
468 |
|
|
// PC
|
469 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
470 |
|
|
begin
|
471 |
|
|
if (rst_i == `TRUE)
|
472 |
|
|
begin
|
473 |
|
|
pc_f <= (`CFG_EBA_RESET-4)/4;
|
474 |
|
|
pc_d <= {`LM32_PC_WIDTH{1'b0}};
|
475 |
|
|
pc_x <= {`LM32_PC_WIDTH{1'b0}};
|
476 |
|
|
pc_m <= {`LM32_PC_WIDTH{1'b0}};
|
477 |
|
|
pc_w <= {`LM32_PC_WIDTH{1'b0}};
|
478 |
|
|
end
|
479 |
|
|
else
|
480 |
|
|
begin
|
481 |
|
|
if (stall_f == `FALSE)
|
482 |
|
|
pc_f <= pc_a;
|
483 |
|
|
if (stall_d == `FALSE)
|
484 |
|
|
pc_d <= pc_f;
|
485 |
|
|
if (stall_x == `FALSE)
|
486 |
|
|
pc_x <= pc_d;
|
487 |
|
|
if (stall_m == `FALSE)
|
488 |
|
|
pc_m <= pc_x;
|
489 |
|
|
pc_w <= pc_m;
|
490 |
|
|
end
|
491 |
|
|
end
|
492 |
|
|
|
493 |
|
|
`ifdef LM32_CACHE_ENABLED
|
494 |
|
|
// Address to restart from after a cache miss has been handled
|
495 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
496 |
|
|
begin
|
497 |
|
|
if (rst_i == `TRUE)
|
498 |
|
|
restart_address <= {`LM32_PC_WIDTH{1'b0}};
|
499 |
|
|
else
|
500 |
|
|
begin
|
501 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
502 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
503 |
|
|
// D-cache restart address must take priority, otherwise instructions will be lost
|
504 |
|
|
if (dcache_refill_request == `TRUE)
|
505 |
|
|
restart_address <= pc_w;
|
506 |
|
|
else if ((icache_refill_request == `TRUE) && (!dcache_refilling))
|
507 |
|
|
restart_address <= icache_refill_address;
|
508 |
|
|
`else
|
509 |
|
|
if (dcache_refill_request == `TRUE)
|
510 |
|
|
restart_address <= pc_w;
|
511 |
|
|
`endif
|
512 |
|
|
`else
|
513 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
514 |
|
|
if (icache_refill_request == `TRUE)
|
515 |
|
|
restart_address <= icache_refill_address;
|
516 |
|
|
`endif
|
517 |
|
|
`endif
|
518 |
|
|
end
|
519 |
|
|
end
|
520 |
|
|
`endif
|
521 |
|
|
|
522 |
|
|
// Record where instruction was fetched from
|
523 |
|
|
`ifdef CFG_IROM_ENABLED
|
524 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
525 |
|
|
begin
|
526 |
|
|
if (rst_i == `TRUE)
|
527 |
|
|
irom_select_f <= `FALSE;
|
528 |
|
|
else
|
529 |
|
|
begin
|
530 |
|
|
if (stall_f == `FALSE)
|
531 |
|
|
irom_select_f <= irom_select_a;
|
532 |
|
|
end
|
533 |
|
|
end
|
534 |
|
|
`endif
|
535 |
|
|
|
536 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
537 |
|
|
assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
|
538 |
|
|
always @*
|
539 |
|
|
begin
|
540 |
|
|
case (jtag_address[1:0])
|
541 |
|
|
2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
|
542 |
|
|
2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
|
543 |
|
|
2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
|
544 |
|
|
2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
|
545 |
|
|
endcase
|
546 |
|
|
end
|
547 |
|
|
`endif
|
548 |
|
|
|
549 |
|
|
`ifdef CFG_IWB_ENABLED
|
550 |
|
|
// Instruction Wishbone interface
|
551 |
|
|
`ifdef CFG_ICACHE_ENABLED
|
552 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
553 |
|
|
begin
|
554 |
|
|
if (rst_i == `TRUE)
|
555 |
|
|
begin
|
556 |
|
|
i_cyc_o <= `FALSE;
|
557 |
|
|
i_stb_o <= `FALSE;
|
558 |
|
|
i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
|
559 |
|
|
i_cti_o <= `LM32_CTYPE_END;
|
560 |
|
|
i_lock_o <= `FALSE;
|
561 |
|
|
icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
|
562 |
|
|
icache_refill_ready <= `FALSE;
|
563 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
564 |
|
|
bus_error_f <= `FALSE;
|
565 |
|
|
`endif
|
566 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
567 |
|
|
i_we_o <= `FALSE;
|
568 |
|
|
i_sel_o <= 4'b1111;
|
569 |
|
|
jtag_access <= `FALSE;
|
570 |
|
|
`endif
|
571 |
|
|
end
|
572 |
|
|
else
|
573 |
|
|
begin
|
574 |
|
|
icache_refill_ready <= `FALSE;
|
575 |
|
|
// Is a cycle in progress?
|
576 |
|
|
if (i_cyc_o == `TRUE)
|
577 |
|
|
begin
|
578 |
|
|
// Has cycle completed?
|
579 |
|
|
if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
|
580 |
|
|
begin
|
581 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
582 |
|
|
if (jtag_access == `TRUE)
|
583 |
|
|
begin
|
584 |
|
|
i_cyc_o <= `FALSE;
|
585 |
|
|
i_stb_o <= `FALSE;
|
586 |
|
|
i_we_o <= `FALSE;
|
587 |
|
|
jtag_access <= `FALSE;
|
588 |
|
|
end
|
589 |
|
|
else
|
590 |
|
|
`endif
|
591 |
|
|
begin
|
592 |
|
|
if (last_word == `TRUE)
|
593 |
|
|
begin
|
594 |
|
|
// Cache line fill complete
|
595 |
|
|
i_cyc_o <= `FALSE;
|
596 |
|
|
i_stb_o <= `FALSE;
|
597 |
|
|
i_lock_o <= `FALSE;
|
598 |
|
|
end
|
599 |
|
|
// Fetch next word in cache line
|
600 |
|
|
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
|
601 |
|
|
i_cti_o <= next_cycle_type;
|
602 |
|
|
// Write fetched data into instruction cache
|
603 |
|
|
icache_refill_ready <= `TRUE;
|
604 |
|
|
icache_refill_data <= i_dat_i;
|
605 |
|
|
end
|
606 |
|
|
end
|
607 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
608 |
|
|
if (i_err_i == `TRUE)
|
609 |
|
|
begin
|
610 |
|
|
bus_error_f <= `TRUE;
|
611 |
|
|
$display ("Instruction bus error. Address: %x", i_adr_o);
|
612 |
|
|
end
|
613 |
|
|
`endif
|
614 |
|
|
end
|
615 |
|
|
else
|
616 |
|
|
begin
|
617 |
|
|
if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
|
618 |
|
|
begin
|
619 |
|
|
// Read first word of cache line
|
620 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
621 |
|
|
i_sel_o <= 4'b1111;
|
622 |
|
|
`endif
|
623 |
|
|
i_adr_o <= {first_address, 2'b00};
|
624 |
|
|
i_cyc_o <= `TRUE;
|
625 |
|
|
i_stb_o <= `TRUE;
|
626 |
|
|
i_cti_o <= first_cycle_type;
|
627 |
|
|
//i_lock_o <= `TRUE;
|
628 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
629 |
|
|
bus_error_f <= `FALSE;
|
630 |
|
|
`endif
|
631 |
|
|
end
|
632 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
633 |
|
|
else
|
634 |
|
|
begin
|
635 |
|
|
if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
|
636 |
|
|
begin
|
637 |
|
|
case (jtag_address[1:0])
|
638 |
|
|
2'b00: i_sel_o <= 4'b1000;
|
639 |
|
|
2'b01: i_sel_o <= 4'b0100;
|
640 |
|
|
2'b10: i_sel_o <= 4'b0010;
|
641 |
|
|
2'b11: i_sel_o <= 4'b0001;
|
642 |
|
|
endcase
|
643 |
|
|
i_adr_o <= jtag_address;
|
644 |
|
|
i_dat_o <= {4{jtag_write_data}};
|
645 |
|
|
i_cyc_o <= `TRUE;
|
646 |
|
|
i_stb_o <= `TRUE;
|
647 |
|
|
i_we_o <= jtag_write_enable;
|
648 |
|
|
i_cti_o <= `LM32_CTYPE_END;
|
649 |
|
|
jtag_access <= `TRUE;
|
650 |
|
|
end
|
651 |
|
|
end
|
652 |
|
|
`endif
|
653 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
654 |
|
|
// Clear bus error when exception taken, otherwise they would be
|
655 |
|
|
// continually generated if exception handler is cached
|
656 |
|
|
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
|
657 |
|
|
if (branch_taken_x == `TRUE)
|
658 |
|
|
bus_error_f <= `FALSE;
|
659 |
|
|
`endif
|
660 |
|
|
if (branch_taken_m == `TRUE)
|
661 |
|
|
bus_error_f <= `FALSE;
|
662 |
|
|
`endif
|
663 |
|
|
end
|
664 |
|
|
end
|
665 |
|
|
end
|
666 |
|
|
`else
|
667 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
668 |
|
|
begin
|
669 |
|
|
if (rst_i == `TRUE)
|
670 |
|
|
begin
|
671 |
|
|
i_cyc_o <= `FALSE;
|
672 |
|
|
i_stb_o <= `FALSE;
|
673 |
|
|
i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
|
674 |
|
|
i_cti_o <= `LM32_CTYPE_CLASSIC;
|
675 |
|
|
i_lock_o <= `FALSE;
|
676 |
|
|
wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
|
677 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
678 |
|
|
bus_error_f <= `FALSE;
|
679 |
|
|
`endif
|
680 |
|
|
end
|
681 |
|
|
else
|
682 |
|
|
begin
|
683 |
|
|
// Is a cycle in progress?
|
684 |
|
|
if (i_cyc_o == `TRUE)
|
685 |
|
|
begin
|
686 |
|
|
// Has cycle completed?
|
687 |
|
|
if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
|
688 |
|
|
begin
|
689 |
|
|
// Cycle complete
|
690 |
|
|
i_cyc_o <= `FALSE;
|
691 |
|
|
i_stb_o <= `FALSE;
|
692 |
|
|
// Register fetched instruction
|
693 |
|
|
wb_data_f <= i_dat_i;
|
694 |
|
|
end
|
695 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
696 |
|
|
if (i_err_i == `TRUE)
|
697 |
|
|
begin
|
698 |
|
|
bus_error_f <= `TRUE;
|
699 |
|
|
$display ("Instruction bus error. Address: %x", i_adr_o);
|
700 |
|
|
end
|
701 |
|
|
`endif
|
702 |
|
|
end
|
703 |
|
|
else
|
704 |
|
|
begin
|
705 |
|
|
// Wait for an instruction fetch from an external address
|
706 |
|
|
if ( (stall_a == `FALSE)
|
707 |
|
|
`ifdef CFG_IROM_ENABLED
|
708 |
|
|
&& (irom_select_a == `FALSE)
|
709 |
|
|
`endif
|
710 |
|
|
)
|
711 |
|
|
begin
|
712 |
|
|
// Fetch instruction
|
713 |
|
|
`ifdef CFG_HW_DEBUG_ENABLED
|
714 |
|
|
i_sel_o <= 4'b1111;
|
715 |
|
|
`endif
|
716 |
|
|
i_adr_o <= {pc_a, 2'b00};
|
717 |
|
|
i_cyc_o <= `TRUE;
|
718 |
|
|
i_stb_o <= `TRUE;
|
719 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
720 |
|
|
bus_error_f <= `FALSE;
|
721 |
|
|
`endif
|
722 |
|
|
end
|
723 |
|
|
end
|
724 |
|
|
end
|
725 |
|
|
end
|
726 |
|
|
`endif
|
727 |
|
|
`endif
|
728 |
|
|
|
729 |
|
|
// Instruction register
|
730 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
731 |
|
|
begin
|
732 |
|
|
if (rst_i == `TRUE)
|
733 |
|
|
begin
|
734 |
|
|
instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
|
735 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
736 |
|
|
bus_error_d <= `FALSE;
|
737 |
|
|
`endif
|
738 |
|
|
end
|
739 |
|
|
else
|
740 |
|
|
begin
|
741 |
|
|
if (stall_d == `FALSE)
|
742 |
|
|
begin
|
743 |
|
|
instruction_d <= instruction_f;
|
744 |
|
|
`ifdef CFG_BUS_ERRORS_ENABLED
|
745 |
|
|
bus_error_d <= bus_error_f;
|
746 |
|
|
`endif
|
747 |
|
|
end
|
748 |
|
|
end
|
749 |
|
|
end
|
750 |
|
|
|
751 |
|
|
endmodule
|