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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_jtag.v] - Blame information for rev 17

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// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_jtag.v
// Title            : JTAG interface
// Dependencies     : lm32_include.v
// Version          : 6.1.17
// =============================================================================
 
`include "lm32_include.v"
 
`ifdef CFG_JTAG_ENABLED
 
`define LM32_DP                             3'b000
`define LM32_TX                             3'b001
`define LM32_RX                             3'b010
 
// LM32 Debug Protocol commands IDs
`define LM32_DP_RNG                         3:0
`define LM32_DP_READ_MEMORY                 4'b0001
`define LM32_DP_WRITE_MEMORY                4'b0010
`define LM32_DP_READ_SEQUENTIAL             4'b0011
`define LM32_DP_WRITE_SEQUENTIAL            4'b0100
`define LM32_DP_WRITE_CSR                   4'b0101
`define LM32_DP_BREAK                       4'b0110
`define LM32_DP_RESET                       4'b0111
 
// States for FSM
`define LM32_JTAG_STATE_RNG                 3:0
`define LM32_JTAG_STATE_READ_COMMAND        4'h0
`define LM32_JTAG_STATE_READ_BYTE_0         4'h1
`define LM32_JTAG_STATE_READ_BYTE_1         4'h2
`define LM32_JTAG_STATE_READ_BYTE_2         4'h3
`define LM32_JTAG_STATE_READ_BYTE_3         4'h4
`define LM32_JTAG_STATE_READ_BYTE_4         4'h5
`define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
`define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
`define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_jtag (
    // ----- Inputs -------
    clk_i,
    rst_i,
    jtag_clk,
    jtag_update,
    jtag_reg_q,
    jtag_reg_addr_q,
`ifdef CFG_JTAG_UART_ENABLED
    csr,
    csr_write_enable,
    csr_write_data,
    stall_x,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
    jtag_read_data,
    jtag_access_complete,
`endif
`ifdef CFG_DEBUG_ENABLED
    exception_q_w,
`endif
    // ----- Outputs -------
`ifdef CFG_JTAG_UART_ENABLED
    jtx_csr_read_data,
    jrx_csr_read_data,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
    jtag_csr_write_enable,
    jtag_csr_write_data,
    jtag_csr,
    jtag_read_enable,
    jtag_write_enable,
    jtag_write_data,
    jtag_address,
`endif
`ifdef CFG_DEBUG_ENABLED
    jtag_break,
    jtag_reset,
`endif
    jtag_reg_d,
    jtag_reg_addr_d
    );
 
   parameter lat_family = `LATTICE_FAMILY;
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                            // Clock
input rst_i;                                            // Reset
 
input jtag_clk;                                         // JTAG clock
input jtag_update;                                      // JTAG data register has been updated
input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
input [2:0] jtag_reg_addr_q;                            // JTAG data register
 
`ifdef CFG_JTAG_UART_ENABLED
input [`LM32_CSR_RNG] csr;                              // CSR to write
input csr_write_enable;                                 // CSR write enable
input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
input stall_x;                                          // Stall instruction in X stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
input jtag_access_complete;                             // Memory access if complete
`endif
`ifdef CFG_DEBUG_ENABLED
input exception_q_w;                                    // Indicates an exception has occured in W stage
`endif
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
`ifdef CFG_JTAG_UART_ENABLED
output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
wire   [`LM32_WORD_RNG] jtx_csr_read_data;
output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
wire   [`LM32_WORD_RNG] jrx_csr_read_data;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output jtag_csr_write_enable;                           // CSR write enable
reg    jtag_csr_write_enable;
output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
wire   [`LM32_WORD_RNG] jtag_csr_write_data;
output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
wire   [`LM32_CSR_RNG] jtag_csr;
output jtag_read_enable;                                // Memory read enable
reg    jtag_read_enable;
output jtag_write_enable;                               // Memory write enable
reg    jtag_write_enable;
output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
wire   [`LM32_BYTE_RNG] jtag_write_data;
output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
wire   [`LM32_WORD_RNG] jtag_address;
`endif
`ifdef CFG_DEBUG_ENABLED
output jtag_break;                                      // Request to raise a breakpoint exception
reg    jtag_break;
output jtag_reset;                                      // Request to raise a reset exception
reg    jtag_reset;
`endif
output [`LM32_BYTE_RNG] jtag_reg_d;
reg    [`LM32_BYTE_RNG] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire   [2:0] jtag_reg_addr_d;
 
/////////////////////////////////////////////////////
// Internal nets and registers 
/////////////////////////////////////////////////////
 
reg rx_toggle;                          // Clock-domain crossing registers
reg rx_toggle_r;                        // Registered version of rx_toggle
reg rx_toggle_r_r;                      // Registered version of rx_toggle_r
reg rx_toggle_r_r_r;                    // Registered version of rx_toggle_r_r
 
reg [`LM32_BYTE_RNG] rx_byte;
reg [2:0] rx_addr;
 
`ifdef CFG_JTAG_UART_ENABLED
reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
reg uart_tx_valid;                      // TX data is valid
reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
reg uart_rx_valid;                      // RX data is valid
`endif
 
reg [`LM32_DP_RNG] command;             // The last received command
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
reg [`LM32_BYTE_RNG] jtag_byte_1;
reg [`LM32_BYTE_RNG] jtag_byte_2;
reg [`LM32_BYTE_RNG] jtag_byte_3;
reg [`LM32_BYTE_RNG] jtag_byte_4;
reg processing;                         // Indicates if we're still processing a memory read/write
`endif
 
reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
 
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
 
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
`endif
 
// Generate status flags for reading via the JTAG interface                 
`ifdef CFG_JTAG_UART_ENABLED
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
`else
assign jtag_reg_addr_d[1:0] = 2'b00;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_reg_addr_d[2] = processing;
`else
assign jtag_reg_addr_d[2] = 1'b0;
`endif
 
`ifdef CFG_JTAG_UART_ENABLED
assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
`endif
 
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
 
// Toggle a flag when a JTAG write occurs
generate
      if (lat_family == "EC" || lat_family == "ECP"  ||
          lat_family == "XP" || lat_family == "ECP2" || lat_family == "ECP2M") begin
 
         always @(posedge jtag_clk `CFG_RESET_SENSITIVITY)
           begin
              if (rst_i == `TRUE)
                rx_toggle <= 1'b0;
              else
                if (jtag_update == `TRUE)
                  rx_toggle <= ~rx_toggle;
           end
 
      end else begin // for SC & SCM
 
         always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
           begin
              if (rst_i == `TRUE)
                rx_toggle <= 1'b0;
              else
                rx_toggle <= ~rx_toggle;
           end
 
      end
endgenerate
 
always @(*)
begin
    rx_byte = jtag_reg_q;
    rx_addr = jtag_reg_addr_q;
end
 
// Clock domain crossing from JTAG clock domain to CPU clock domain
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        rx_toggle_r <= 1'b0;
        rx_toggle_r_r <= 1'b0;
        rx_toggle_r_r_r <= 1'b0;
    end
    else
    begin
        rx_toggle_r <= rx_toggle;
        rx_toggle_r_r <= rx_toggle_r;
        rx_toggle_r_r_r <= rx_toggle_r_r;
    end
end
 
// LM32 debug protocol state machine
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        state <= `LM32_JTAG_STATE_READ_COMMAND;
        command <= 4'b0000;
        jtag_reg_d <= 8'h00;
`ifdef CFG_HW_DEBUG_ENABLED
        processing <= `FALSE;
        jtag_csr_write_enable <= `FALSE;
        jtag_read_enable <= `FALSE;
        jtag_write_enable <= `FALSE;
`endif
`ifdef CFG_DEBUG_ENABLED
        jtag_break <= `FALSE;
        jtag_reset <= `FALSE;
`endif
`ifdef CFG_JTAG_UART_ENABLED
        uart_tx_byte <= 8'h00;
        uart_tx_valid <= `FALSE;
        uart_rx_byte <= 8'h00;
        uart_rx_valid <= `FALSE;
`endif
    end
    else
    begin
`ifdef CFG_JTAG_UART_ENABLED
        if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
        begin
            case (csr)
            `LM32_CSR_JTX:
            begin
                // Set flag indicating data is available
                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
                uart_tx_valid <= `TRUE;
            end
            `LM32_CSR_JRX:
            begin
                // Clear flag indidicating data has been received
                uart_rx_valid <= `FALSE;
            end
            endcase
        end
`endif
`ifdef CFG_DEBUG_ENABLED
        // When an exception has occured, clear the requests
        if (exception_q_w == `TRUE)
        begin
            jtag_break <= `FALSE;
            jtag_reset <= `FALSE;
        end
`endif
        case (state)
        `LM32_JTAG_STATE_READ_COMMAND:
        begin
            // Wait for rx register to toggle which indicates new data is available
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                command <= rx_byte[7:4];
                case (rx_addr)
`ifdef CFG_DEBUG_ENABLED
                `LM32_DP:
                begin
                    case (rx_byte[7:4])
`ifdef CFG_HW_DEBUG_ENABLED
                    `LM32_DP_READ_MEMORY:
                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
                    `LM32_DP_READ_SEQUENTIAL:
                    begin
                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
                    end
                    `LM32_DP_WRITE_MEMORY:
                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
                    `LM32_DP_WRITE_SEQUENTIAL:
                    begin
                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
                        state <= 5;
                    end
                    `LM32_DP_WRITE_CSR:
                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
`endif
                    `LM32_DP_BREAK:
                    begin
`ifdef CFG_JTAG_UART_ENABLED
                        uart_rx_valid <= `FALSE;
                        uart_tx_valid <= `FALSE;
`endif
                        jtag_break <= `TRUE;
                    end
                    `LM32_DP_RESET:
                    begin
`ifdef CFG_JTAG_UART_ENABLED
                        uart_rx_valid <= `FALSE;
                        uart_tx_valid <= `FALSE;
`endif
                        jtag_reset <= `TRUE;
                    end
                    endcase
                end
`endif
`ifdef CFG_JTAG_UART_ENABLED
                `LM32_TX:
                begin
                    uart_rx_byte <= rx_byte;
                    uart_rx_valid <= `TRUE;
                end
                `LM32_RX:
                begin
                    jtag_reg_d <= uart_tx_byte;
                    uart_tx_valid <= `FALSE;
                end
`endif
                default:
                    ;
                endcase
            end
        end
`ifdef CFG_HW_DEBUG_ENABLED
        `LM32_JTAG_STATE_READ_BYTE_0:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_0 <= rx_byte;
                state <= `LM32_JTAG_STATE_READ_BYTE_1;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_1:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_1 <= rx_byte;
                state <= `LM32_JTAG_STATE_READ_BYTE_2;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_2:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_2 <= rx_byte;
                state <= `LM32_JTAG_STATE_READ_BYTE_3;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_3:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_3 <= rx_byte;
                if (command == `LM32_DP_READ_MEMORY)
                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
                else
                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_4:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_4 <= rx_byte;
                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
            end
        end
        `LM32_JTAG_STATE_PROCESS_COMMAND:
        begin
            case (command)
            `LM32_DP_READ_MEMORY,
            `LM32_DP_READ_SEQUENTIAL:
            begin
                jtag_read_enable <= `TRUE;
                processing <= `TRUE;
                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
            end
            `LM32_DP_WRITE_MEMORY,
            `LM32_DP_WRITE_SEQUENTIAL:
            begin
                jtag_write_enable <= `TRUE;
                processing <= `TRUE;
                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
            end
            `LM32_DP_WRITE_CSR:
            begin
                jtag_csr_write_enable <= `TRUE;
                processing <= `TRUE;
                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
            end
            endcase
        end
        `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
        begin
            if (jtag_access_complete == `TRUE)
            begin
                jtag_read_enable <= `FALSE;
                jtag_reg_d <= jtag_read_data;
                jtag_write_enable <= `FALSE;
                processing <= `FALSE;
                state <= `LM32_JTAG_STATE_READ_COMMAND;
            end
        end
        `LM32_JTAG_STATE_WAIT_FOR_CSR:
        begin
            jtag_csr_write_enable <= `FALSE;
            processing <= `FALSE;
            state <= `LM32_JTAG_STATE_READ_COMMAND;
        end
`endif
        endcase
    end
end
 
endmodule
 
`endif

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_jtag.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	alirezamon	`// =============================================================================`
2			`// COPYRIGHT NOTICE`
3			`// Copyright 2006 (c) Lattice Semiconductor Corporation`
4			`// ALL RIGHTS RESERVED`
5			`// This confidential and proprietary software may be used only as authorised by`
6			`// a licensing agreement from Lattice Semiconductor Corporation.`
7			`// The entire notice above must be reproduced on all authorized copies and`
8			`// copies may only be made to the extent permitted by a licensing agreement from`
9			`// Lattice Semiconductor Corporation.`
10			`//`
11			`// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)`
12			`// 5555 NE Moore Court 408-826-6000 (other locations)`
13			`// Hillsboro, OR 97124 web : http://www.latticesemi.com/`
14			`// U.S.A email: techsupport@latticesemi.com`
15			`// =============================================================================/`
16			`// FILE DETAILS`
17			`// Project : LatticeMico32`
18			`// File : lm32_jtag.v`
19			`// Title : JTAG interface`
20			`// Dependencies : lm32_include.v`
21			`// Version : 6.1.17`
22			`// =============================================================================`
23
24			`include "lm32_include.v"
25
26			`ifdef CFG_JTAG_ENABLED
27
28			`define LM32_DP 3'b000
29			`define LM32_TX 3'b001
30			`define LM32_RX 3'b010
31
32			`// LM32 Debug Protocol commands IDs`
33			`define LM32_DP_RNG 3:0
34			`define LM32_DP_READ_MEMORY 4'b0001
35			`define LM32_DP_WRITE_MEMORY 4'b0010
36			`define LM32_DP_READ_SEQUENTIAL 4'b0011
37			`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
38			`define LM32_DP_WRITE_CSR 4'b0101
39			`define LM32_DP_BREAK 4'b0110
40			`define LM32_DP_RESET 4'b0111
41
42			`// States for FSM`
43			`define LM32_JTAG_STATE_RNG 3:0
44			`define LM32_JTAG_STATE_READ_COMMAND 4'h0
45			`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
46			`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
47			`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
48			`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
49			`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
50			`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
51			`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
52			`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
53
54			`/////////////////////////////////////////////////////`
55			`// Module interface`
56			`/////////////////////////////////////////////////////`
57
58			`module lm32_jtag (`
59			`// ----- Inputs -------`
60			`clk_i,`
61			`rst_i,`
62			`jtag_clk,`
63			`jtag_update,`
64			`jtag_reg_q,`
65			`jtag_reg_addr_q,`
66			`ifdef CFG_JTAG_UART_ENABLED
67			`csr,`
68			`csr_write_enable,`
69			`csr_write_data,`
70			`stall_x,`
71			`endif
72			`ifdef CFG_HW_DEBUG_ENABLED
73			`jtag_read_data,`
74			`jtag_access_complete,`
75			`endif
76			`ifdef CFG_DEBUG_ENABLED
77			`exception_q_w,`
78			`endif
79			`// ----- Outputs -------`
80			`ifdef CFG_JTAG_UART_ENABLED
81			`jtx_csr_read_data,`
82			`jrx_csr_read_data,`
83			`endif
84			`ifdef CFG_HW_DEBUG_ENABLED
85			`jtag_csr_write_enable,`
86			`jtag_csr_write_data,`
87			`jtag_csr,`
88			`jtag_read_enable,`
89			`jtag_write_enable,`
90			`jtag_write_data,`
91			`jtag_address,`
92			`endif
93			`ifdef CFG_DEBUG_ENABLED
94			`jtag_break,`
95			`jtag_reset,`
96			`endif
97			`jtag_reg_d,`
98			`jtag_reg_addr_d`
99			`);`
100
101			parameter lat_family = `LATTICE_FAMILY;
102
103			`/////////////////////////////////////////////////////`
104			`// Inputs`
105			`/////////////////////////////////////////////////////`
106
107			`input clk_i; // Clock`
108			`input rst_i; // Reset`
109
110			`input jtag_clk; // JTAG clock`
111			`input jtag_update; // JTAG data register has been updated`
112			input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
113			`input [2:0] jtag_reg_addr_q; // JTAG data register`
114
115			`ifdef CFG_JTAG_UART_ENABLED
116			input [`LM32_CSR_RNG] csr; // CSR to write
117			`input csr_write_enable; // CSR write enable`
118			input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
119			`input stall_x; // Stall instruction in X stage`
120			`endif
121			`ifdef CFG_HW_DEBUG_ENABLED
122			input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
123			`input jtag_access_complete; // Memory access if complete`
124			`endif
125			`ifdef CFG_DEBUG_ENABLED
126			`input exception_q_w; // Indicates an exception has occured in W stage`
127			`endif
128
129			`/////////////////////////////////////////////////////`
130			`// Outputs`
131			`/////////////////////////////////////////////////////`
132
133			`ifdef CFG_JTAG_UART_ENABLED
134			output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
135			wire [`LM32_WORD_RNG] jtx_csr_read_data;
136			output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
137			wire [`LM32_WORD_RNG] jrx_csr_read_data;
138			`endif
139			`ifdef CFG_HW_DEBUG_ENABLED
140			`output jtag_csr_write_enable; // CSR write enable`
141			`reg jtag_csr_write_enable;`
142			output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
143			wire [`LM32_WORD_RNG] jtag_csr_write_data;
144			output [`LM32_CSR_RNG] jtag_csr; // CSR to write
145			wire [`LM32_CSR_RNG] jtag_csr;
146			`output jtag_read_enable; // Memory read enable`
147			`reg jtag_read_enable;`
148			`output jtag_write_enable; // Memory write enable`
149			`reg jtag_write_enable;`
150			output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
151			wire [`LM32_BYTE_RNG] jtag_write_data;
152			output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
153			wire [`LM32_WORD_RNG] jtag_address;
154			`endif
155			`ifdef CFG_DEBUG_ENABLED
156			`output jtag_break; // Request to raise a breakpoint exception`
157			`reg jtag_break;`
158			`output jtag_reset; // Request to raise a reset exception`
159			`reg jtag_reset;`
160			`endif
161			output [`LM32_BYTE_RNG] jtag_reg_d;
162			reg [`LM32_BYTE_RNG] jtag_reg_d;
163			`output [2:0] jtag_reg_addr_d;`
164			`wire [2:0] jtag_reg_addr_d;`
165
166			`/////////////////////////////////////////////////////`
167			`// Internal nets and registers`
168			`/////////////////////////////////////////////////////`
169
170			`reg rx_toggle; // Clock-domain crossing registers`
171			`reg rx_toggle_r; // Registered version of rx_toggle`
172			`reg rx_toggle_r_r; // Registered version of rx_toggle_r`
173			`reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r`
174
175			reg [`LM32_BYTE_RNG] rx_byte;
176			`reg [2:0] rx_addr;`
177
178			`ifdef CFG_JTAG_UART_ENABLED
179			reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
180			`reg uart_tx_valid; // TX data is valid`
181			reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
182			`reg uart_rx_valid; // RX data is valid`
183			`endif
184
185			reg [`LM32_DP_RNG] command; // The last received command
186			`ifdef CFG_HW_DEBUG_ENABLED
187			reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
188			reg [`LM32_BYTE_RNG] jtag_byte_1;
189			reg [`LM32_BYTE_RNG] jtag_byte_2;
190			reg [`LM32_BYTE_RNG] jtag_byte_3;
191			reg [`LM32_BYTE_RNG] jtag_byte_4;
192			`reg processing; // Indicates if we're still processing a memory read/write`
193			`endif
194
195			reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
196
197			`/////////////////////////////////////////////////////`
198			`// Combinational Logic`
199			`/////////////////////////////////////////////////////`
200
201			`ifdef CFG_HW_DEBUG_ENABLED
202			`assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};`
203			assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
204			`assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};`
205			`assign jtag_write_data = jtag_byte_4;`
206			`endif
207
208			`// Generate status flags for reading via the JTAG interface`
209			`ifdef CFG_JTAG_UART_ENABLED
210			`assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};`
211			`else
212			`assign jtag_reg_addr_d[1:0] = 2'b00;`
213			`endif
214			`ifdef CFG_HW_DEBUG_ENABLED
215			`assign jtag_reg_addr_d[2] = processing;`
216			`else
217			`assign jtag_reg_addr_d[2] = 1'b0;`
218			`endif
219
220			`ifdef CFG_JTAG_UART_ENABLED
221			assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
222			assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
223			`endif
224
225			`/////////////////////////////////////////////////////`
226			`// Sequential Logic`
227			`/////////////////////////////////////////////////////`
228
229			`// Toggle a flag when a JTAG write occurs`
230			`generate`
231			`if (lat_family == "EC" \|\| lat_family == "ECP" \|\|`
232			`lat_family == "XP" \|\| lat_family == "ECP2" \|\| lat_family == "ECP2M") begin`
233
234			always @(posedge jtag_clk `CFG_RESET_SENSITIVITY)
235			`begin`
236			if (rst_i == `TRUE)
237			`rx_toggle <= 1'b0;`
238			`else`
239			if (jtag_update == `TRUE)
240			`rx_toggle <= ~rx_toggle;`
241			`end`
242
243			`end else begin // for SC & SCM`
244
245			always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
246			`begin`
247			if (rst_i == `TRUE)
248			`rx_toggle <= 1'b0;`
249			`else`
250			`rx_toggle <= ~rx_toggle;`
251			`end`
252
253			`end`
254			`endgenerate`
255
256			`always @(*)`
257			`begin`
258			`rx_byte = jtag_reg_q;`
259			`rx_addr = jtag_reg_addr_q;`
260			`end`
261
262			`// Clock domain crossing from JTAG clock domain to CPU clock domain`
263			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
264			`begin`
265			if (rst_i == `TRUE)
266			`begin`
267			`rx_toggle_r <= 1'b0;`
268			`rx_toggle_r_r <= 1'b0;`
269			`rx_toggle_r_r_r <= 1'b0;`
270			`end`
271			`else`
272			`begin`
273			`rx_toggle_r <= rx_toggle;`
274			`rx_toggle_r_r <= rx_toggle_r;`
275			`rx_toggle_r_r_r <= rx_toggle_r_r;`
276			`end`
277			`end`
278
279			`// LM32 debug protocol state machine`
280			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
281			`begin`
282			if (rst_i == `TRUE)
283			`begin`
284			state <= `LM32_JTAG_STATE_READ_COMMAND;
285			`command <= 4'b0000;`
286			`jtag_reg_d <= 8'h00;`
287			`ifdef CFG_HW_DEBUG_ENABLED
288			processing <= `FALSE;
289			jtag_csr_write_enable <= `FALSE;
290			jtag_read_enable <= `FALSE;
291			jtag_write_enable <= `FALSE;
292			`endif
293			`ifdef CFG_DEBUG_ENABLED
294			jtag_break <= `FALSE;
295			jtag_reset <= `FALSE;
296			`endif
297			`ifdef CFG_JTAG_UART_ENABLED
298			`uart_tx_byte <= 8'h00;`
299			uart_tx_valid <= `FALSE;
300			`uart_rx_byte <= 8'h00;`
301			uart_rx_valid <= `FALSE;
302			`endif
303			`end`
304			`else`
305			`begin`
306			`ifdef CFG_JTAG_UART_ENABLED
307			if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
308			`begin`
309			`case (csr)`
310			`LM32_CSR_JTX:
311			`begin`
312			`// Set flag indicating data is available`
313			uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
314			uart_tx_valid <= `TRUE;
315			`end`
316			`LM32_CSR_JRX:
317			`begin`
318			`// Clear flag indidicating data has been received`
319			uart_rx_valid <= `FALSE;
320			`end`
321			`endcase`
322			`end`
323			`endif
324			`ifdef CFG_DEBUG_ENABLED
325			`// When an exception has occured, clear the requests`
326			if (exception_q_w == `TRUE)
327			`begin`
328			jtag_break <= `FALSE;
329			jtag_reset <= `FALSE;
330			`end`
331			`endif
332			`case (state)`
333			`LM32_JTAG_STATE_READ_COMMAND:
334			`begin`
335			`// Wait for rx register to toggle which indicates new data is available`
336			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
337			`begin`
338			`command <= rx_byte[7:4];`
339			`case (rx_addr)`
340			`ifdef CFG_DEBUG_ENABLED
341			`LM32_DP:
342			`begin`
343			`case (rx_byte[7:4])`
344			`ifdef CFG_HW_DEBUG_ENABLED
345			`LM32_DP_READ_MEMORY:
346			state <= `LM32_JTAG_STATE_READ_BYTE_0;
347			`LM32_DP_READ_SEQUENTIAL:
348			`begin`
349			`{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;`
350			state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
351			`end`
352			`LM32_DP_WRITE_MEMORY:
353			state <= `LM32_JTAG_STATE_READ_BYTE_0;
354			`LM32_DP_WRITE_SEQUENTIAL:
355			`begin`
356			`{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;`
357			`state <= 5;`
358			`end`
359			`LM32_DP_WRITE_CSR:
360			state <= `LM32_JTAG_STATE_READ_BYTE_0;
361			`endif
362			`LM32_DP_BREAK:
363			`begin`
364			`ifdef CFG_JTAG_UART_ENABLED
365			uart_rx_valid <= `FALSE;
366			uart_tx_valid <= `FALSE;
367			`endif
368			jtag_break <= `TRUE;
369			`end`
370			`LM32_DP_RESET:
371			`begin`
372			`ifdef CFG_JTAG_UART_ENABLED
373			uart_rx_valid <= `FALSE;
374			uart_tx_valid <= `FALSE;
375			`endif
376			jtag_reset <= `TRUE;
377			`end`
378			`endcase`
379			`end`
380			`endif
381			`ifdef CFG_JTAG_UART_ENABLED
382			`LM32_TX:
383			`begin`
384			`uart_rx_byte <= rx_byte;`
385			uart_rx_valid <= `TRUE;
386			`end`
387			`LM32_RX:
388			`begin`
389			`jtag_reg_d <= uart_tx_byte;`
390			uart_tx_valid <= `FALSE;
391			`end`
392			`endif
393			`default:`
394			`;`
395			`endcase`
396			`end`
397			`end`
398			`ifdef CFG_HW_DEBUG_ENABLED
399			`LM32_JTAG_STATE_READ_BYTE_0:
400			`begin`
401			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
402			`begin`
403			`jtag_byte_0 <= rx_byte;`
404			state <= `LM32_JTAG_STATE_READ_BYTE_1;
405			`end`
406			`end`
407			`LM32_JTAG_STATE_READ_BYTE_1:
408			`begin`
409			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
410			`begin`
411			`jtag_byte_1 <= rx_byte;`
412			state <= `LM32_JTAG_STATE_READ_BYTE_2;
413			`end`
414			`end`
415			`LM32_JTAG_STATE_READ_BYTE_2:
416			`begin`
417			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
418			`begin`
419			`jtag_byte_2 <= rx_byte;`
420			state <= `LM32_JTAG_STATE_READ_BYTE_3;
421			`end`
422			`end`
423			`LM32_JTAG_STATE_READ_BYTE_3:
424			`begin`
425			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
426			`begin`
427			`jtag_byte_3 <= rx_byte;`
428			if (command == `LM32_DP_READ_MEMORY)
429			state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
430			`else`
431			state <= `LM32_JTAG_STATE_READ_BYTE_4;
432			`end`
433			`end`
434			`LM32_JTAG_STATE_READ_BYTE_4:
435			`begin`
436			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
437			`begin`
438			`jtag_byte_4 <= rx_byte;`
439			state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
440			`end`
441			`end`
442			`LM32_JTAG_STATE_PROCESS_COMMAND:
443			`begin`
444			`case (command)`
445			`LM32_DP_READ_MEMORY,
446			`LM32_DP_READ_SEQUENTIAL:
447			`begin`
448			jtag_read_enable <= `TRUE;
449			processing <= `TRUE;
450			state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
451			`end`
452			`LM32_DP_WRITE_MEMORY,
453			`LM32_DP_WRITE_SEQUENTIAL:
454			`begin`
455			jtag_write_enable <= `TRUE;
456			processing <= `TRUE;
457			state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
458			`end`
459			`LM32_DP_WRITE_CSR:
460			`begin`
461			jtag_csr_write_enable <= `TRUE;
462			processing <= `TRUE;
463			state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
464			`end`
465			`endcase`
466			`end`
467			`LM32_JTAG_STATE_WAIT_FOR_MEMORY:
468			`begin`
469			if (jtag_access_complete == `TRUE)
470			`begin`
471			jtag_read_enable <= `FALSE;
472			`jtag_reg_d <= jtag_read_data;`
473			jtag_write_enable <= `FALSE;
474			processing <= `FALSE;
475			state <= `LM32_JTAG_STATE_READ_COMMAND;
476			`end`
477			`end`
478			`LM32_JTAG_STATE_WAIT_FOR_CSR:
479			`begin`
480			jtag_csr_write_enable <= `FALSE;
481			processing <= `FALSE;
482			state <= `LM32_JTAG_STATE_READ_COMMAND;
483			`end`
484			`endif
485			`endcase`
486			`end`
487			`end`
488
489			`endmodule`
490
491			`endif