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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_simtrace.v] - Blame information for rev 38

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1 17 alirezamon 
// =============================================================================/
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//                         FILE DETAILS
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// Project          : LatticeMico32
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// File             : lm32_simtrace.v
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// Title            : Trace excecution in simulation
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// Dependencies     : lm32_include.v
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// Version          : soc-lm32 only
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// =============================================================================
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`include "lm32_include.v"
11 38 alirezamon 
`define  DISPLAY_INST  0
12 17 alirezamon 
 
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// Index of opcode field in an instruction
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`define LM32_OPCODE_RNG         31:26
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`define LM32_OP_RNG             30:26
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_simtrace (
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    // ----- Inputs -------
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    clk_i,
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    rst_i,
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    // From pipeline
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    stall_x,
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    stall_m,
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        valid_w,
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        kill_w,
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    instruction_d,
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        pc_w
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    );
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input                         clk_i;
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input                         rst_i;
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input                         stall_x;        //
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input                         stall_m;        //
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input                         valid_w;        //
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input                         kill_w;         //
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input [`LM32_INSTRUCTION_RNG] instruction_d;  // Instruction to decode
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input [`LM32_PC_RNG]          pc_w;           // PC of instruction in D stage
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg [`LM32_INSTRUCTION_RNG] instruction_x;  // Instruction to decode
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reg [`LM32_INSTRUCTION_RNG] instruction_m;  // Instruction to decode
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reg [`LM32_INSTRUCTION_RNG] instruction;    // Instruction to decode
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wire [`LM32_WORD_RNG] extended_immediate;       // Zero or sign extended immediate
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wire [`LM32_WORD_RNG] high_immediate;           // Immedate as high 16 bits
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wire [`LM32_WORD_RNG] immediate;                // Immedate as high 16 bits
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wire [`LM32_WORD_RNG] call_immediate;           // Call immediate
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wire [`LM32_WORD_RNG] branch_immediate;         // Conditional branch immediate
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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`define  INCLUDE_FUNCTION
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`include "lm32_functions.v"
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wire [4:0]  r3    = instruction[25:21];
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wire [4:0]  r2    = instruction[20:16];
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wire [4:0]  r1    = instruction[15:11];
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wire [ 4:0] imm5  = instruction[ 4:0];
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wire [15:0] imm16 = instruction[15:0];
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wire [26:0] imm27 = instruction[26:0];
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//assign high_imm     = {instruction[15:0], 16'h0000};
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wire [`LM32_PC_RNG] call_imm     = {{ 4{instruction[25]}}, instruction[25:0]};
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wire [`LM32_PC_RNG] branch_imm   = {{14{instruction[15]}}, instruction[15:0] };
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// synopsys translate_off
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always @(posedge clk_i)
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begin
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        if (stall_x == `FALSE)
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                instruction_x <= instruction_d;
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        if (stall_m == `FALSE)
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                instruction_m <= instruction_x;
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        instruction <= instruction_m;
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89 38 alirezamon 
        if ((valid_w == `TRUE) && (!kill_w) && `DISPLAY_INST) begin
90 17 alirezamon 
                // $write ( $stime/10 );
91 34 alirezamon 
                //$writeh( " [", pc_w << 2);
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                //$writeh( "]\t" );
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                $write ( " [0x%h]\t", pc_w << 2);
94 17 alirezamon 
                case ( instruction[`LM32_OPCODE_RNG] )
95 34 alirezamon 
                        6'h00: $display( "srui    r%0d, r%0d, 0x%0h",    r2, r3, imm5 );
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                        6'h01: $display( "nori    r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h02: $display( "muli    r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h03: $display( "sh      (r%0d + 0x%0h), r%0d", r3, r2, imm16 );
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                        6'h04: $display( "lb      r%0d, (r%0d + 0x%0h)", r2, r3, imm16 );
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                        6'h05: $display( "sri     r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h06: $display( "xori    r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h07: $display( "lh      r%0d, (r%0d + 0x%0h)", r2, r3, imm16 );
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                        6'h08: $display( "andi    r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h09: $display( "xnori   r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h0a: $display( "lw      r%0d, (r%0d + 0x%0h)", r2, r3, imm16 );
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                        6'h0b: $display( "lhu     r%0d, (r%0d + 0x%0h)", r2, r3, imm16 );
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                        6'h0c: $display( "sb      (r%0d + 0x%0h), r%0d", r3, r2, imm16 );
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                        6'h0d: $display( "addi    r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h0e: $display( "ori     r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h0f: $display( "sli     r%0d, r%0d, 0x%0h",    r2, r3, imm5  );
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                        6'h10: $display( "lbu     r%0d, (r%0d + 0x%0h)", r2, r3, imm16 );
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                        6'h11: $display( "be      r%0d, r%0d, 0x%h",     r2, r3, (pc_w + branch_imm ) << 2 );
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                        6'h12: $display( "bg      r%0d, r%0d, 0x%h",     r2, r3, (pc_w + branch_imm ) << 2 );
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                        6'h13: $display( "bge     r%0d, r%0d, 0x%h",     r2, r3, (pc_w + branch_imm ) << 2 );
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                        6'h14: $display( "bgeu    r%0d, r%0d, 0x%h",     r2, r3, (pc_w + branch_imm ) << 2 );
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                        6'h15: $display( "bgu     r%0d, r%0d, 0x%h",     r2, r3, (pc_w + branch_imm ) << 2 );
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                        6'h16: $display( "sw      (r%0d + 0x%0h), r%0d", r3, r2, imm16 );
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                        6'h17: $display( "bne     r%0d, r%0d, 0x%h",     r2, r3, (pc_w + branch_imm ) << 2 );
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                        6'h18: $display( "andhi   r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h19: $display( "cmpei   r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h1a: $display( "cmpgi   r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h1b: $display( "cmpgei r%0d, r%0d, 0x%0h",     r2, r3, imm16 );
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                        6'h1c: $display( "cmpgeui r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h1d: $display( "cmpgui r%0d, r%0d, 0x%0h",     r2, r3, imm16 );
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                        6'h1e: $display( "orhi    r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
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                        6'h1f: $display( "cmpnei  r%0d, r%0d, 0x%0h",    r2, r3, imm16 );
127 17 alirezamon 
                        6'h20: $display( "sru     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h21: $display( "nor     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h22: $display( "mul     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h23: $display( "divu    r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h24: $display( "rcsr    r%0d, csr%0d",      r1, r3 );
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                        6'h25: $display( "sr      r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h26: $display( "xor     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h27: $display( "div (XXX not documented XXX)" );
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                        6'h28: $display( "and     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h29: $display( "xnor    r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h2a: $display( "XXX" );
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                        6'h2b: $display( "raise (XXX: scall or break)" );
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                        6'h2c: $display( "sextb   r%0d, r%0d", r1, r3 );
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                        6'h2d: $display( "add     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h2e: $display( "or      r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h2f: $display( "sl      r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h30: $display( "b       r%0d", r3 );
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                        6'h31: $display( "modu    r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h32: $display( "sub     r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h33: $display( "XXX" );
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                        6'h34: $display( "wcsr    csr%0d, r%0d", r3, r2 );
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                        6'h35: $display( "modu    r%0d, r%0d, r%0d",  r1, r3, r2 );
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                        6'h36: $display( "call    r%0d", r3 );
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                        6'h37: $display( "sexth   r%0d, r%0d", r1, r3 );
151 34 alirezamon 
                        6'h38: $display( "bi      0x%h", (pc_w + call_imm) << 2 );
152 17 alirezamon 
                        6'h39: $display( "cmpe    r%0d, r%0d, r%0d", r1, r3, r2 );
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                        6'h3a: $display( "cmpg    r%0d, r%0d, r%0d", r1, r3, r2 );
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                        6'h3b: $display( "cmpge   r%0d, r%0d, r%0d", r1, r3, r2 );
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                        6'h3c: $display( "cmpgeu  r%0d, r%0d, r%0d", r1, r3, r2 );
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                        6'h3d: $display( "cmpgu   r%0d, r%0d, r%0d", r1, r3, r2 );
157 34 alirezamon 
                        6'h3e: $display( "calli   0x%h", (pc_w + call_imm) << 2 );
158 17 alirezamon 
                        6'h3f: $display( "cmpne   r%0d, r%0d, r%0d", r1, r3, r2 );
159 
                endcase
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        end
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end
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// synopsys translate_on
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165 
endmodule
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