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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx-defines.v] - Blame information for rev 38

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1 38 alirezamon 
/* ****************************************************************************
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  This Source Code Form is subject to the terms of the
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  Open Hardware Description License, v. 1.0. If a copy
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  of the OHDL was not distributed with this file, You
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  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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  Description: mor1kx defines
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  Copyright (C) 2012 Authors
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  Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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/* ORBIS32 opcodes - top 6 bits */
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`define OR1K_INSN_WIDTH 32
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`define OR1K_RD_SELECT 25:21
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`define OR1K_RA_SELECT 20:16
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`define OR1K_RB_SELECT 15:11
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`define OR1K_IMM_WIDTH 16
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`define OR1K_IMM_SELECT 15:0
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`define OR1K_ALU_OPC_WIDTH 4
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`define OR1K_ALU_OPC_SELECT 3:0
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`define OR1K_ALU_OPC_ADD   `OR1K_ALU_OPC_WIDTH'h0
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`define OR1K_ALU_OPC_ADDC  `OR1K_ALU_OPC_WIDTH'h1
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`define OR1K_ALU_OPC_SUB   `OR1K_ALU_OPC_WIDTH'h2
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`define OR1K_ALU_OPC_AND   `OR1K_ALU_OPC_WIDTH'h3
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`define OR1K_ALU_OPC_OR    `OR1K_ALU_OPC_WIDTH'h4
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`define OR1K_ALU_OPC_XOR   `OR1K_ALU_OPC_WIDTH'h5
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`define OR1K_ALU_OPC_MUL   `OR1K_ALU_OPC_WIDTH'h6
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`define OR1K_ALU_OPC_RESV  `OR1K_ALU_OPC_WIDTH'h7
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`define OR1K_ALU_OPC_SHRT  `OR1K_ALU_OPC_WIDTH'h8
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`define OR1K_ALU_OPC_DIV   `OR1K_ALU_OPC_WIDTH'h9
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`define OR1K_ALU_OPC_DIVU  `OR1K_ALU_OPC_WIDTH'ha
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`define OR1K_ALU_OPC_MULU  `OR1K_ALU_OPC_WIDTH'hb
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`define OR1K_ALU_OPC_EXTBH `OR1K_ALU_OPC_WIDTH'hc
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`define OR1K_ALU_OPC_EXTW  `OR1K_ALU_OPC_WIDTH'hd
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`define OR1K_ALU_OPC_CMOV  `OR1K_ALU_OPC_WIDTH'he
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`define OR1K_ALU_OPC_FFL1  `OR1K_ALU_OPC_WIDTH'hf
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`define OR1K_ALU_OPC_SECONDARY_WIDTH 3
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`define OR1K_ALU_OPC_SECONDARY_SELECT 8:6
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`define OR1K_ALU_OPC_SECONDARY_SHRT_SLL `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
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`define OR1K_ALU_OPC_SECONDARY_SHRT_SRL `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
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`define OR1K_ALU_OPC_SECONDARY_SHRT_SRA `OR1K_ALU_OPC_SECONDARY_WIDTH'h2
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`define OR1K_ALU_OPC_SECONDARY_SHRT_ROR `OR1K_ALU_OPC_SECONDARY_WIDTH'h3
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`define OR1K_COMP_OPC_WIDTH 4
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`define OR1K_COMP_OPC_SELECT 24:21
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`define OR1K_COMP_OPC_EQ  `OR1K_COMP_OPC_WIDTH'h0
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`define OR1K_COMP_OPC_NE  `OR1K_COMP_OPC_WIDTH'h1
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`define OR1K_COMP_OPC_GTU `OR1K_COMP_OPC_WIDTH'h2
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`define OR1K_COMP_OPC_GEU `OR1K_COMP_OPC_WIDTH'h3
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`define OR1K_COMP_OPC_LTU `OR1K_COMP_OPC_WIDTH'h4
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`define OR1K_COMP_OPC_LEU `OR1K_COMP_OPC_WIDTH'h5
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`define OR1K_COMP_OPC_GTS `OR1K_COMP_OPC_WIDTH'ha
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`define OR1K_COMP_OPC_GES `OR1K_COMP_OPC_WIDTH'hb
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`define OR1K_COMP_OPC_LTS `OR1K_COMP_OPC_WIDTH'hc
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`define OR1K_COMP_OPC_LES `OR1K_COMP_OPC_WIDTH'hd
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`define OR1K_JUMPBRANCH_IMMEDIATE_SELECT 25:0
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`define OR1K_SYSTRAPSYNC_OPC_WIDTH 3
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`define OR1K_SYSTRAPSYNC_OPC_SELECT 25:23
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`define OR1K_SYSTRAPSYNC_OPC_SYSCALL `OR1K_SYSTRAPSYNC_OPC_WIDTH'h0
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`define OR1K_SYSTRAPSYNC_OPC_TRAP `OR1K_SYSTRAPSYNC_OPC_WIDTH'h2
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`define OR1K_SYSTRAPSYNC_OPC_MSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h4
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`define OR1K_SYSTRAPSYNC_OPC_PSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h5
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`define OR1K_SYSTRAPSYNC_OPC_CSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h6
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77 
`define OR1K_OPCODE_WIDTH 6
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`define OR1K_OPCODE_SELECT 31:26
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`define OR1K_OPCODE_J       {2'b00, 4'h0}
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`define OR1K_OPCODE_JAL     {2'b00, 4'h1}
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`define OR1K_OPCODE_BNF     {2'b00, 4'h3}
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`define OR1K_OPCODE_BF      {2'b00, 4'h4}
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`define OR1K_OPCODE_NOP     {2'b00, 4'h5}
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`define OR1K_OPCODE_MOVHI   {2'b00, 4'h6}
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`define OR1K_OPCODE_MACRC   {2'b00, 4'h6}
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/*
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`define OR1K_OPCODE_SYS     {2'b00, 4'h8}
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`define OR1K_OPCODE_TRAP    {2'b00, 4'h8}
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`define OR1K_OPCODE_MSYNC   {2'b00, 4'h8}
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`define OR1K_OPCODE_PSYNC   {2'b00, 4'h8}
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`define OR1K_OPCODE_CSYNC   {2'b00, 4'h8}
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 */
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`define OR1K_OPCODE_SYSTRAPSYNC {2'b00, 4'h8}
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`define OR1K_OPCODE_RFE     {2'b00, 4'h9}
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`define OR1K_OPCODE_JR      {2'b01, 4'h1}
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`define OR1K_OPCODE_JALR    {2'b01, 4'h2}
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`define OR1K_OPCODE_MACI    {2'b01, 4'h3}
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`define OR1K_OPCODE_LWA     {2'b01, 4'hB}
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`define OR1K_OPCODE_CUST1   {2'b01, 4'hC}
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`define OR1K_OPCODE_CUST2   {2'b01, 4'hD}
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`define OR1K_OPCODE_CUST3   {2'b01, 4'hE}
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`define OR1K_OPCODE_CUST4   {2'b01, 4'hF}
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`define OR1K_OPCODE_LD      {2'b10, 4'h0}
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`define OR1K_OPCODE_LWZ     {2'b10, 4'h1}
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`define OR1K_OPCODE_LWS     {2'b10, 4'h2}
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`define OR1K_OPCODE_LBZ     {2'b10, 4'h3}
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`define OR1K_OPCODE_LBS     {2'b10, 4'h4}
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`define OR1K_OPCODE_LHZ     {2'b10, 4'h5}
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`define OR1K_OPCODE_LHS     {2'b10, 4'h6}
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`define OR1K_OPCODE_ADDI    {2'b10, 4'h7}
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`define OR1K_OPCODE_ADDIC   {2'b10, 4'h8}
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`define OR1K_OPCODE_ANDI    {2'b10, 4'h9}
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`define OR1K_OPCODE_ORI     {2'b10, 4'hA}
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`define OR1K_OPCODE_XORI    {2'b10, 4'hB}
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`define OR1K_OPCODE_MULI    {2'b10, 4'hC}
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`define OR1K_OPCODE_MFSPR   {2'b10, 4'hD}
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/*
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`define OR1K_OPCODE_SLLI    {2'b10, 4'hE}
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`define OR1K_OPCODE_SRLI    {2'b10, 4'hE}
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`define OR1K_OPCODE_SRAI    {2'b10, 4'hE}
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`define OR1K_OPCODE_RORI    {2'b10, 4'hE}
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*/
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`define OR1K_OPCODE_SHRTI    {2'b10, 4'hE}
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/*
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`define OR1K_OPCODE_SFEQI   {2'b10, 4'hF}
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`define OR1K_OPCODE_SFNEI   {2'b10, 4'hF}
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`define OR1K_OPCODE_SFGTUI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFGEUI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFLTUI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFLEUI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFGTSI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFGESI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFLTSI  {2'b10, 4'hF}
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`define OR1K_OPCODE_SFLESI  {2'b10, 4'hF}
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*/
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`define OR1K_OPCODE_SFIMM   {2'b10, 4'hF}
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`define OR1K_OPCODE_MTSPR   {2'b11, 4'h0}
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`define OR1K_OPCODE_MAC     {2'b11, 4'h1}
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`define OR1K_OPCODE_MSB     {2'b11, 4'h1}
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`define OR1K_OPCODE_SWA     {2'b11, 4'h3}
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`define OR1K_OPCODE_SD      {2'b11, 4'h4}
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`define OR1K_OPCODE_SW      {2'b11, 4'h5}
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`define OR1K_OPCODE_SB      {2'b11, 4'h6}
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`define OR1K_OPCODE_SH      {2'b11, 4'h7}
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/*
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`define OR1K_OPCODE_ADD     {2'b11, 4'h8}
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`define OR1K_OPCODE_ADDC    {2'b11, 4'h8}
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`define OR1K_OPCODE_SUB     {2'b11, 4'h8}
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`define OR1K_OPCODE_AND     {2'b11, 4'h8}
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`define OR1K_OPCODE_OR      {2'b11, 4'h8}
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`define OR1K_OPCODE_XOR     {2'b11, 4'h8}
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`define OR1K_OPCODE_MUL     {2'b11, 4'h8}
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`define OR1K_OPCODE_SLL     {2'b11, 4'h8}
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`define OR1K_OPCODE_SRL     {2'b11, 4'h8}
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`define OR1K_OPCODE_SRA     {2'b11, 4'h8}
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`define OR1K_OPCODE_ROR     {2'b11, 4'h8}
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`define OR1K_OPCODE_DIV     {2'b11, 4'h8}
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`define OR1K_OPCODE_DIVU    {2'b11, 4'h8}
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`define OR1K_OPCODE_MULU    {2'b11, 4'h8}
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`define OR1K_OPCODE_EXTBS   {2'b11, 4'h8}
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`define OR1K_OPCODE_EXTHS   {2'b11, 4'h8}
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`define OR1K_OPCODE_EXTWS   {2'b11, 4'h8}
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`define OR1K_OPCODE_EXTBZ   {2'b11, 4'h8}
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`define OR1K_OPCODE_EXTHZ   {2'b11, 4'h8}
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`define OR1K_OPCODE_EXTWZ   {2'b11, 4'h8}
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`define OR1K_OPCODE_CMOV    {2'b11, 4'h8}
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`define OR1K_OPCODE_FF1     {2'b11, 4'h8}
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`define OR1K_OPCODE_FL1     {2'b11, 4'h8}
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*/
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`define OR1K_OPCODE_ALU     {2'b11, 4'h8}
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/*
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`define OR1K_OPCODE_SFEQ    {2'b11, 4'h9}
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`define OR1K_OPCODE_SFNE    {2'b11, 4'h9}
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`define OR1K_OPCODE_SFGTU   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFGEU   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFLTU   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFLEU   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFGTS   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFGES   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFLTS   {2'b11, 4'h9}
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`define OR1K_OPCODE_SFLES   {2'b11, 4'h9}
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*/
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`define OR1K_OPCODE_SF      {2'b11, 4'h9}
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`define OR1K_OPCODE_CUST5   {2'b11, 4'hC}
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`define OR1K_OPCODE_CUST6   {2'b11, 4'hD}
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`define OR1K_OPCODE_CUST7   {2'b11, 4'hE}
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`define OR1K_OPCODE_CUST8   {2'b11, 4'hF}
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201 
//
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// OR1K SPR defines
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//
204 
`include "mor1kx-sprs.v"
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206 
/* Exception addresses */
207 
`define OR1K_RESET_VECTOR    5'h01
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`define OR1K_BERR_VECTOR     5'h02
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`define OR1K_DPF_VECTOR      5'h03
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`define OR1K_IPF_VECTOR      5'h04
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`define OR1K_TT_VECTOR       5'h05
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`define OR1K_ALIGN_VECTOR    5'h06
213 
`define OR1K_ILLEGAL_VECTOR  5'h07
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`define OR1K_INT_VECTOR      5'h08
215 
`define OR1K_DTLB_VECTOR     5'h09
216 
`define OR1K_ITLB_VECTOR     5'h0a
217 
`define OR1K_RANGE_VECTOR    5'h0b
218 
`define OR1K_SYSCALL_VECTOR  5'h0c
219 
`define OR1K_FP_VECTOR       5'h0d
220 
`define OR1K_TRAP_VECTOR     5'h0e
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222 
// Whether we'll allow things using AYNC reset to have it:
223 
//`define OR_ASYNC_RST or posedge rst
224 
`define OR_ASYNC_RST
225 
 
226 
// Implementation version defines
227 
`define MOR1KX_CPUID 8'h01
228 
// mor1kx breaks up the VR2 version register to be 3 8-bit fields
229 
// MSB is major version, middle byte is minor version number
230 
// and final byte is the pipeline identifier.
231 
`define MOR1KX_VERSION_MAJOR 8'd3
232 
`define MOR1KX_VERSION_MINOR 8'd1
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234 
// mor1kx implementation-specific register definitions
235 
`define MOR1KX_PIPEID_CAPPUCCINO 8'd1
236 
`define MOR1KX_PIPEID_ESPRESSO   8'd2
237 
`define MOR1KX_PIPEID_PRONTOESPRESSO 8'd3

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