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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx-sprs.v] - Blame information for rev 38

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1 38 alirezamon 
/* ****************************************************************************
2 
  This Source Code Form is subject to the terms of the
3 
  Open Hardware Description License, v. 1.0. If a copy
4 
  of the OHDL was not distributed with this file, You
5 
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
6 
 
7 
  Description: SPR definitions
8 
 
9 
  Copyright (C) 2012 Authors
10 
 
11 
  Author(s): Julius Baxter <juliusbaxter@gmail.com>
12 
 
13 
***************************************************************************** */
14 
`define SPR_BASE(x)   (x/(2**11))
15 
`define SPR_OFFSET(x) (x%(2**11))
16 
 
17 
//
18 
// Addresses
19 
//
20 
`define OR1K_SPR_SYS_BASE       {5'd0}
21 
`define OR1K_SPR_VR_ADDR        {5'd0,11'd0}
22 
`define OR1K_SPR_UPR_ADDR       {5'd0,11'd1}
23 
`define OR1K_SPR_CPUCFGR_ADDR   {5'd0,11'd2}
24 
`define OR1K_SPR_DMMUCFGR_ADDR  {5'd0,11'd3}
25 
`define OR1K_SPR_IMMUCFGR_ADDR  {5'd0,11'd4}
26 
`define OR1K_SPR_DCCFGR_ADDR    {5'd0,11'd5}
27 
`define OR1K_SPR_ICCFGR_ADDR    {5'd0,11'd6}
28 
`define OR1K_SPR_DCFGR_ADDR     {5'd0,11'd7}
29 
`define OR1K_SPR_PCCFGR_ADDR    {5'd0,11'd8}
30 
`define OR1K_SPR_VR2_ADDR       {5'd0,11'd9}
31 
`define OR1K_SPR_AVR_ADDR       {5'd0,11'd10}
32 
`define OR1K_SPR_EVBAR_ADDR     {5'd0,11'd11}
33 
`define OR1K_SPR_AECR_ADDR      {5'd0,11'd12}
34 
`define OR1K_SPR_AESR_ADDR      {5'd0,11'd13}
35 
`define OR1K_SPR_NPC_ADDR       {5'd0,11'd16}
36 
`define OR1K_SPR_SR_ADDR        {5'd0,11'd17}
37 
`define OR1K_SPR_PPC_ADDR       {5'd0,11'd18}
38 
`define OR1K_SPR_FPCSR_ADDR     {5'd0,11'd20}
39 
`define OR1K_SPR_ISR0_ADDR      {5'd0,11'd21}
40 
`define OR1K_SPR_EPCR0_ADDR     {5'd0,11'd32}
41 
`define OR1K_SPR_EEAR0_ADDR     {5'd0,11'd48}
42 
`define OR1K_SPR_ESR0_ADDR      {5'd0,11'd64}
43 
`define OR1K_SPR_COREID_ADDR    {5'd0,11'd128}
44 
`define OR1K_SPR_NUMCORES_ADDR  {5'd0,11'd129}
45 
`define OR1K_SPR_GPR0_ADDR      {5'd0,11'd1024}
46 
 
47 
`define OR1K_SPR_DMMU_BASE      {5'd1}
48 
`define OR1K_SPR_DMMUCR_ADDR    {5'd1,11'd0}
49 
`define OR1K_SPR_DMMUPR_ADDR    {5'd1,11'd1}
50 
`define OR1K_SPR_DTLBEIR_ADDR   {5'd1,11'd2}
51 
`define OR1K_SPR_DATBMR0_ADDR   {5'd1,11'd4}
52 
`define OR1K_SPR_DATBTR0_ADDR   {5'd1,11'd8}
53 
`define OR1K_SPR_DTLBW0MR0_ADDR {5'd1,11'd512}
54 
`define OR1K_SPR_DTLBW0TR0_ADDR {5'd1,11'd640}
55 
`define OR1K_SPR_DTLBW1MR0_ADDR {5'd1,11'd768}
56 
`define OR1K_SPR_DTLBW1TR0_ADDR {5'd1,11'd896}
57 
`define OR1K_SPR_DTLBW2MR0_ADDR {5'd1,11'd1024}
58 
`define OR1K_SPR_DTLBW2TR0_ADDR {5'd1,11'd1152}
59 
`define OR1K_SPR_DTLBW3MR0_ADDR {5'd1,11'd1280}
60 
`define OR1K_SPR_DTLBW3TR0_ADDR {5'd1,11'd1408}
61 
 
62 
`define OR1K_SPR_IMMU_BASE      {5'd2}
63 
`define OR1K_SPR_IMMUCR_ADDR    {5'd2,11'd0}
64 
`define OR1K_SPR_IMMUPR_ADDR    {5'd2,11'd1}
65 
`define OR1K_SPR_ITLBEIR_ADDR   {5'd2,11'd2}
66 
`define OR1K_SPR_IATBMR0_ADDR   {5'd2,11'd4}
67 
`define OR1K_SPR_IATBTR0_ADDR   {5'd2,11'd8}
68 
`define OR1K_SPR_ITLBW0MR0_ADDR {5'd2,11'd512}
69 
`define OR1K_SPR_ITLBW0TR0_ADDR {5'd2,11'd640}
70 
`define OR1K_SPR_ITLBW1MR0_ADDR {5'd2,11'd768}
71 
`define OR1K_SPR_ITLBW1TR0_ADDR {5'd2,11'd896}
72 
`define OR1K_SPR_ITLBW2MR0_ADDR {5'd2,11'd1024}
73 
`define OR1K_SPR_ITLBW2TR0_ADDR {5'd2,11'd1152}
74 
`define OR1K_SPR_ITLBW3MR0_ADDR {5'd2,11'd1280}
75 
`define OR1K_SPR_ITLBW3TR0_ADDR {5'd2,11'd1408}
76 
 
77 
`define OR1K_SPR_DC_BASE        {5'd3}
78 
`define OR1K_SPR_DCCR_ADDR      {5'd3,11'd0}
79 
`define OR1K_SPR_DCBPR_ADDR     {5'd3,11'd1}
80 
`define OR1K_SPR_DCBFR_ADDR     {5'd3,11'd2}
81 
`define OR1K_SPR_DCBIR_ADDR     {5'd3,11'd3}
82 
`define OR1K_SPR_DCBWR_ADDR     {5'd3,11'd4}
83 
`define OR1K_SPR_DCBLR_ADDR     {5'd3,11'd5}
84 
 
85 
`define OR1K_SPR_IC_BASE        {5'd4}
86 
`define OR1K_SPR_ICCR_ADDR      {5'd4,11'd0}
87 
`define OR1K_SPR_ICBPR_ADDR     {5'd4,11'd1}
88 
`define OR1K_SPR_ICBIR_ADDR     {5'd4,11'd2}
89 
`define OR1K_SPR_ICBLR_ADDR     {5'd4,11'd3}
90 
 
91 
`define OR1K_SPR_MAC_BASE       {5'd5}
92 
`define OR1K_SPR_MACLO_ADDR     {5'd5,11'd1}
93 
`define OR1K_SPR_MACHI_ADDR     {5'd5,11'd2}
94 
 
95 
`define OR1K_SPR_DU_BASE        {5'd6}
96 
`define OR1K_SPR_DVR0_ADDR      {5'd6,11'd0}
97 
`define OR1K_SPR_DCR0_ADDR      {5'd6,11'd8}
98 
`define OR1K_SPR_DMR1_ADDR      {5'd6,11'd16}
99 
`define OR1K_SPR_DMR2_ADDR      {5'd6,11'd17}
100 
`define OR1K_SPR_DCWR0_ADDR     {5'd6,11'd18}
101 
`define OR1K_SPR_DSR_ADDR       {5'd6,11'd20}
102 
`define OR1K_SPR_DRR_ADDR       {5'd6,11'd21}
103 
 
104 
`define OR1K_SPR_PC_BASE        {5'd7}
105 
`define OR1K_SPR_PCCR0_ADDR     {5'd7,11'd0}
106 
`define OR1K_SPR_PCMR0_ADDR     {5'd7,11'd8}
107 
 
108 
`define OR1K_SPR_PM_BASE        {5'd8}
109 
`define OR1K_SPR_PMR_ADDR       {5'd8,11'd0}
110 
 
111 
`define OR1K_SPR_PIC_BASE       {5'd9}
112 
`define OR1K_SPR_PICMR_ADDR     {5'd9,11'd0}
113 
`define OR1K_SPR_PICSR_ADDR     {5'd9,11'd2}
114 
 
115 
`define OR1K_SPR_TT_BASE        {5'd10}
116 
`define OR1K_SPR_TTMR_ADDR      {5'd10,11'd0}
117 
`define OR1K_SPR_TTCR_ADDR      {5'd10,11'd1}
118 
 
119 
`define OR1K_SPR_FPU_BASE       {5'd11}
120 
 
121 
//
122 
// Register bit defines
123 
//
124 
 
125 
// Supervision Register
126 
`define OR1K_SPR_SR_SM     0  /* Supervisor mode */
127 
`define OR1K_SPR_SR_TEE    1  /* Timer exception enable */
128 
`define OR1K_SPR_SR_IEE    2  /* Interrupt exception enable */
129 
`define OR1K_SPR_SR_DCE    3  /* Data cache enable */
130 
`define OR1K_SPR_SR_ICE    4  /* Instruction cache enable */
131 
`define OR1K_SPR_SR_DME    5  /* Data MMU enable */
132 
`define OR1K_SPR_SR_IME    6  /* Instruction MMU enable */
133 
`define OR1K_SPR_SR_LEE    7  /* Little-endian enable */
134 
`define OR1K_SPR_SR_CE     8  /* CID enable */
135 
`define OR1K_SPR_SR_F      9  /* Flag */
136 
`define OR1K_SPR_SR_CY    10  /* Carry flag */
137 
`define OR1K_SPR_SR_OV    11  /* Overflow flag */
138 
`define OR1K_SPR_SR_OVE   12  /* Overflow exception enable */
139 
`define OR1K_SPR_SR_DSX   13  /* Delay slot exception */
140 
`define OR1K_SPR_SR_EPH   14  /* Exception prefix high */
141 
`define OR1K_SPR_SR_FO    15  /* Fixed to one */
142 
`define OR1K_SPR_SR_SUMRA 16  /* SPR user read mode access */
143 
`define OR1K_SPR_SR_RESERVED 27:17 /* Reserved */
144 
`define OR1K_SPR_SR_CID      31:28 /* Context ID */
145 
 
146 
// Version register - DEPRECATED
147 
`define OR1K_SPR_VR_REV   5:0  /* Revision */
148 
`define OR1K_SPR_VR_UVRP  6  /* Updated Version Registers Present */
149 
`define OR1K_SPR_VR_RESERVED 15:7 /* Reserved */
150 
`define OR1K_SPR_VR_CFG   23:16  /* Configuration Template */
151 
`define OR1K_SPR_VR_VER   31:24  /* Version */
152 
 
153 
 
154 
// Unit Present register
155 
`define OR1K_SPR_UPR_UP    0
156 
`define OR1K_SPR_UPR_DCP   1
157 
`define OR1K_SPR_UPR_ICP   2
158 
`define OR1K_SPR_UPR_DMP   3
159 
`define OR1K_SPR_UPR_IMP   4
160 
`define OR1K_SPR_UPR_MP    5
161 
`define OR1K_SPR_UPR_DUP   6
162 
`define OR1K_SPR_UPR_PCUP  7
163 
`define OR1K_SPR_UPR_PICP  8
164 
`define OR1K_SPR_UPR_PMP   9
165 
`define OR1K_SPR_UPR_TTP  10
166 
`define OR1K_SPR_UPR_RESERVED 23:11
167 
`define OR1K_SPR_UPR_CUP   31:24
168 
 
169 
// CPU Configuration register
170 
`define OR1K_SPR_CPUCFGR_NSGF   3:0 /* Number of shadow GPRs */
171 
`define OR1K_SPR_CPUCFGR_CFG    4
172 
`define OR1K_SPR_CPUCFGR_OB32S  5
173 
`define OR1K_SPR_CPUCFGR_OB64S  6
174 
`define OR1K_SPR_CPUCFGR_OF32S  7
175 
`define OR1K_SPR_CPUCFGR_OF64S  8
176 
`define OR1K_SPR_CPUCFGR_OV64S  9
177 
`define OR1K_SPR_CPUCFGR_ND     10 /* No delay-slot implementation */
178 
`define OR1K_SPR_CPUCFGR_AVRP   11 /* Arch. version registers */
179 
`define OR1K_SPR_CPUCFGR_EVBARP 12 /* Exception vector base addr reg */
180 
`define OR1K_SPR_CPUCFGR_ISRP   13 /* Implementation specific regs */
181 
`define OR1K_SPR_CPUCFGR_AECSRP 14 /* Arith. exception regs */
182 
`define OR1K_SPR_CPUCFGR_RESERVED 31:15
183 
 
184 
// Version register 2 (new with OR1K 1.0)
185 
`define OR1K_SPR_VR2_VER 23:0
186 
`define OR1K_SPR_VR2_CPUID 31:24
187 
 
188 
// Architecture Version register
189 
`define OR1K_SPR_AVR_RESERVED 7:0
190 
`define OR1K_SPR_AVR_REV 15:8
191 
`define OR1K_SPR_AVR_MIN 23:16
192 
`define OR1K_SPR_AVR_MAJ 31:24
193 
 
194 
// Exception Vector Base Address register
195 
`define OR1K_SPR_EVBAR_RESERVED 12:0
196 
`define OR1K_SPR_EVBAR_EVBA 31:13
197 
 
198 
// Arithmetic Exception Control register
199 
`define OR1K_SPR_AECR_CYADDE    0
200 
`define OR1K_SPR_AECR_OVADDE    1
201 
`define OR1K_SPR_AECR_CYMULE    2
202 
`define OR1K_SPR_AECR_OVMULE    3
203 
`define OR1K_SPR_AECR_DBZE      4
204 
`define OR1K_SPR_AECR_CYMACADDE 5
205 
`define OR1K_SPR_AECR_OVMACADDE 6
206 
`define OR1K_SPR_AECR_RESERVED  31:7
207 
 
208 
// Arithmetic Exception Status register
209 
`define OR1K_SPR_AESR_CYADDE    0
210 
`define OR1K_SPR_AESR_OVADDE    1
211 
`define OR1K_SPR_AESR_CYMULE    2
212 
`define OR1K_SPR_AESR_OVMULE    3
213 
`define OR1K_SPR_AESR_DBZE      4
214 
`define OR1K_SPR_AESR_CYMACADDE 5
215 
`define OR1K_SPR_AESR_OVMACADDE 6
216 
`define OR1K_SPR_AESR_RESERVED  31:7
217 
 
218 
// Tick timer registers
219 
`define OR1K_SPR_TTMR_TP   27:0 /* Time period */
220 
`define OR1K_SPR_TTMR_IP   28   /* Interrupt pending */
221 
`define OR1K_SPR_TTMR_IE   29   /* Interrupt enable */
222 
`define OR1K_SPR_TTMR_M    31:30 /* Mode */
223 
// Tick timer mode values
224 
`define OR1K_SPR_TTMR_M_DIS 2'b00  /* Disabled */
225 
`define OR1K_SPR_TTMR_M_RST 2'b01  /* Restart-on-match mode */
226 
`define OR1K_SPR_TTMR_M_STP 2'b10  /* Stop-on-match mode */
227 
`define OR1K_SPR_TTMR_M_CNT 2'b11  /* Continue counting mode */
228 
 
229 
// Data Cache Configuration register
230 
`define OR1K_SPR_DCCFGR_NCW   2:0 /* Number of Cache Ways */
231 
`define OR1K_SPR_DCCFGR_NCS   6:3 /* Number of Cache Sets */
232 
`define OR1K_SPR_DCCFGR_CBS   7   /* Cache Block Size */
233 
`define OR1K_SPR_DCCFGR_CWS   8   /* Cache Write Strategy */
234 
`define OR1K_SPR_DCCFGR_CCRI  9   /* Cache Control Register Implemented */
235 
`define OR1K_SPR_DCCFGR_CBIRI 10  /* Cache Block Invalidate Register Implemented */
236 
`define OR1K_SPR_DCCFGR_CBPRI 11  /* Cache Block Prefetch Register Implemented */
237 
`define OR1K_SPR_DCCFGR_CBLRI 12  /* Cache Block Lock Register Implemented */
238 
`define OR1K_SPR_DCCFGR_CBFRI 13  /* Cache Block Flush Register Implemented */
239 
`define OR1K_SPR_DCCFGR_CBWBRI 14 /* Cache Block Write-Back Register Implemented */
240 
 
241 
// Instruction Cache Configuration register
242 
`define OR1K_SPR_ICCFGR_NCW   2:0 /* Number of Cache Ways */
243 
`define OR1K_SPR_ICCFGR_NCS   6:3 /* Number of Cache Sets */
244 
`define OR1K_SPR_ICCFGR_CBS   7   /* Cache Block Size */
245 
`define OR1K_SPR_ICCFGR_CCRI  9   /* Cache Control Register Implemented */
246 
`define OR1K_SPR_ICCFGR_CBIRI 10  /* Cache Block Invalidate Register Implemented */
247 
`define OR1K_SPR_ICCFGR_CBPRI 11  /* Cache Block Prefetch Register Implemented */
248 
`define OR1K_SPR_ICCFGR_CBLRI 12  /* Cache Block Lock Register Implemented */
249 
 
250 
// Data MMU Configuration register
251 
`define OR1K_SPR_DMMUFGR_NTW   1:0 /* Number of TLB ways */
252 
`define OR1K_SPR_DMMUFGR_NTS   4:2 /* Number of TLB sets */
253 
`define OR1K_SPR_DMMUFGR_NAE   7:5 /* Number of ATB entries */
254 
`define OR1K_SPR_DMMUFGR_CRI   8   /* Control Register Implemented */
255 
`define OR1K_SPR_DMMUFGR_PRI   9   /* Protection Register Implemented */
256 
`define OR1K_SPR_DMMUFGR_TEIRI 10  /* TLB Entry Invalidate Register Implemented */
257 
`define OR1K_SPR_DMMUFGR_HTR   11  /* Hardware TLB Reload */
258 
 
259 
// Instruction MMU Configuration register
260 
`define OR1K_SPR_IMMUFGR_NTW   1:0 /* Number of TLB ways */
261 
`define OR1K_SPR_IMMUFGR_NTS   4:2 /* Number of TLB sets */
262 
`define OR1K_SPR_IMMUFGR_NAE   7:5 /* Number of ATB entries */
263 
`define OR1K_SPR_IMMUFGR_CRI   8   /* Control Register Implemented */
264 
`define OR1K_SPR_IMMUFGR_PRI   9   /* Protection Register Implemented */
265 
`define OR1K_SPR_IMMUFGR_TEIRI 10  /* TLB Entry Invalidate Register Implemented */
266 
`define OR1K_SPR_IMMUFGR_HTR   11  /* Hardware TLB Reload */
267 
 
268 
// Debug Mode Register 1
269 
`define OR1K_SPR_DMR1_ST 22
270 
`define OR1K_SPR_DMR1_BT 23
271 
 
272 
// Debug Stop Register
273 
`define OR1K_SPR_DSR_RSTE  0
274 
`define OR1K_SPR_DSR_BUSEE 1
275 
`define OR1K_SPR_DSR_DPFE  2
276 
`define OR1K_SPR_DSR_IPFE  3
277 
`define OR1K_SPR_DSR_TTE   4
278 
`define OR1K_SPR_DSR_AE    5
279 
`define OR1K_SPR_DSR_IIE   6
280 
`define OR1K_SPR_DSR_INTE  7
281 
`define OR1K_SPR_DSR_DME   8
282 
`define OR1K_SPR_DSR_IME   9
283 
`define OR1K_SPR_DSR_RE   10
284 
`define OR1K_SPR_DSR_SCE  11
285 
`define OR1K_SPR_DSR_FPE  12
286 
`define OR1K_SPR_DSR_TE   13
287 
 
288 
`define OR1K_SPR_DRR_RSTE  0
289 
`define OR1K_SPR_DRR_BUSEE 1
290 
`define OR1K_SPR_DRR_DPFE  2
291 
`define OR1K_SPR_DRR_IPFE  3
292 
`define OR1K_SPR_DRR_TTE   4
293 
`define OR1K_SPR_DRR_AE    5
294 
`define OR1K_SPR_DRR_IIE   6
295 
`define OR1K_SPR_DRR_IE    7
296 
`define OR1K_SPR_DRR_DME   8
297 
`define OR1K_SPR_DRR_IME   9
298 
`define OR1K_SPR_DRR_RE   10
299 
`define OR1K_SPR_DRR_SCE  11
300 
`define OR1K_SPR_DRR_FPE  12
301 
`define OR1K_SPR_DRR_TE   13
302 
 
303 
// Implementation-specific SPR defines
304 
`define MOR1KX_SPR_SR_WIDTH 16
305 
`define MOR1KX_SPR_SR_RESET_VALUE `MOR1KX_SPR_SR_WIDTH'h8001

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