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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx processor top level
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx
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#(
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter OPTION_CPU0 = "CAPPUCCINO",
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parameter FEATURE_DATACACHE = "NONE",
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parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
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parameter OPTION_DCACHE_SET_WIDTH = 9,
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parameter OPTION_DCACHE_WAYS = 2,
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parameter OPTION_DCACHE_LIMIT_WIDTH = 32,
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parameter OPTION_DCACHE_SNOOP = "NONE",
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parameter FEATURE_DMMU = "NONE",
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parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE",
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parameter OPTION_DMMU_SET_WIDTH = 6,
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parameter OPTION_DMMU_WAYS = 1,
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parameter FEATURE_INSTRUCTIONCACHE = "NONE",
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parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
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parameter OPTION_ICACHE_SET_WIDTH = 9,
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parameter OPTION_ICACHE_WAYS = 2,
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parameter OPTION_ICACHE_LIMIT_WIDTH = 32,
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parameter FEATURE_IMMU = "NONE",
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parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE",
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parameter OPTION_IMMU_SET_WIDTH = 6,
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parameter OPTION_IMMU_WAYS = 1,
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parameter FEATURE_TIMER = "ENABLED",
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parameter FEATURE_DEBUGUNIT = "NONE",
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parameter FEATURE_PERFCOUNTERS = "NONE",
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parameter FEATURE_MAC = "NONE",
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parameter FEATURE_SYSCALL = "ENABLED",
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parameter FEATURE_TRAP = "ENABLED",
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parameter FEATURE_RANGE = "ENABLED",
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parameter FEATURE_PIC = "ENABLED",
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parameter OPTION_PIC_TRIGGER = "LEVEL",
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parameter OPTION_PIC_NMI_WIDTH = 0,
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parameter FEATURE_DSX = "ENABLED",
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parameter FEATURE_OVERFLOW = "ENABLED",
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parameter FEATURE_CARRY_FLAG = "ENABLED",
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parameter FEATURE_FASTCONTEXTS = "NONE",
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parameter OPTION_RF_NUM_SHADOW_GPR = 0,
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parameter OPTION_RF_ADDR_WIDTH = 5,
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parameter OPTION_RF_WORDS = 32,
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0},
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parameter FEATURE_MULTIPLIER = "THREESTAGE",
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parameter FEATURE_DIVIDER = "SERIAL",
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parameter FEATURE_ADDC = "ENABLED",
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parameter FEATURE_SRA = "ENABLED",
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parameter FEATURE_ROR = "NONE",
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parameter FEATURE_EXT = "NONE",
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parameter FEATURE_CMOV = "ENABLED",
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parameter FEATURE_FFL1 = "ENABLED",
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parameter FEATURE_ATOMIC = "ENABLED",
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parameter FEATURE_CUST1 = "NONE",
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parameter FEATURE_CUST2 = "NONE",
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parameter FEATURE_CUST3 = "NONE",
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parameter FEATURE_CUST4 = "NONE",
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parameter FEATURE_CUST5 = "NONE",
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parameter FEATURE_CUST6 = "NONE",
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parameter FEATURE_CUST7 = "NONE",
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parameter FEATURE_CUST8 = "NONE",
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parameter OPTION_SHIFTER = "BARREL",
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parameter FEATURE_STORE_BUFFER = "ENABLED",
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parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8,
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parameter FEATURE_MULTICORE = "NONE",
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parameter FEATURE_TRACEPORT_EXEC = "NONE",
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parameter BUS_IF_TYPE = "WISHBONE32",
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parameter IBUS_WB_TYPE = "B3_READ_BURSTING",
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parameter DBUS_WB_TYPE = "CLASSIC"
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)
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(
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input clk,
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input rst,
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// Wishbone interface
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output [31:0] iwbm_adr_o,
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output iwbm_stb_o,
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output iwbm_cyc_o,
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output [3:0] iwbm_sel_o,
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output iwbm_we_o,
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output [2:0] iwbm_cti_o,
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output [1:0] iwbm_bte_o,
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output [31:0] iwbm_dat_o,
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input iwbm_err_i,
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input iwbm_ack_i,
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input [31:0] iwbm_dat_i,
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input iwbm_rty_i,
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output [31:0] dwbm_adr_o,
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output dwbm_stb_o,
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output dwbm_cyc_o,
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output [3:0] dwbm_sel_o,
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output dwbm_we_o,
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output [2:0] dwbm_cti_o,
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output [1:0] dwbm_bte_o,
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output [31:0] dwbm_dat_o,
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input dwbm_err_i,
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input dwbm_ack_i,
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input [31:0] dwbm_dat_i,
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input dwbm_rty_i,
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// Avalon interface
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output [31:0] avm_d_address_o,
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output [3:0] avm_d_byteenable_o,
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output avm_d_read_o,
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input [31:0] avm_d_readdata_i,
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output [3:0] avm_d_burstcount_o,
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output avm_d_write_o,
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output [31:0] avm_d_writedata_o,
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input avm_d_waitrequest_i,
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input avm_d_readdatavalid_i,
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output [31:0] avm_i_address_o,
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output [3:0] avm_i_byteenable_o,
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output avm_i_read_o,
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input [31:0] avm_i_readdata_i,
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output [3:0] avm_i_burstcount_o,
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input avm_i_waitrequest_i,
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input avm_i_readdatavalid_i,
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input [31:0] irq_i,
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// Debug interface
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input [15:0] du_addr_i,
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input du_stb_i,
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input [OPTION_OPERAND_WIDTH-1:0] du_dat_i,
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input du_we_i,
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output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
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output du_ack_o,
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// Stall control from debug interface
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input du_stall_i,
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output du_stall_o,
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output traceport_exec_valid_o,
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output [31:0] traceport_exec_pc_o,
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output [`OR1K_INSN_WIDTH-1:0] traceport_exec_insn_o,
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output [OPTION_OPERAND_WIDTH-1:0] traceport_exec_wbdata_o,
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output [OPTION_RF_ADDR_WIDTH-1:0] traceport_exec_wbreg_o,
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output traceport_exec_wben_o,
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// The multicore core identifier
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input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i,
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// The number of cores
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input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i,
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input [31:0] snoop_adr_i,
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input snoop_en_i
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);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire avm_i_write_o; // From ibus_bridge of mor1kx_bus_if_avalon.v
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wire avm_i_writedata_o; // From ibus_bridge of mor1kx_bus_if_avalon.v
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wire [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire [3:0] dbus_bsel_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire dbus_burst_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire dbus_req_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire dbus_we_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire ibus_burst_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire ibus_req_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire [15:0] spr_bus_addr_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o;// From mor1kx_cpu of mor1kx_cpu.v
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wire spr_bus_stb_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire spr_bus_we_o; // From mor1kx_cpu of mor1kx_cpu.v
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wire [15:0] spr_sr_o; // From mor1kx_cpu of mor1kx_cpu.v
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// End of automatics
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wire ibus_ack_i;
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wire [OPTION_OPERAND_WIDTH-1:0] ibus_dat_i;
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wire ibus_err_i;
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wire dbus_ack_i;
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wire [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i;
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wire dbus_err_i;
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generate
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if (BUS_IF_TYPE=="WISHBONE32") begin : bus_gen
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/* mor1kx_bus_if_wb32 AUTO_TEMPLATE (
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.cpu_err_o (ibus_err_i),
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.cpu_ack_o (ibus_ack_i),
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.cpu_dat_o (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]),
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.wbm_adr_o (iwbm_adr_o),
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.wbm_stb_o (iwbm_stb_o),
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.wbm_cyc_o (iwbm_cyc_o),
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.wbm_sel_o (iwbm_sel_o),
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.wbm_we_o (iwbm_we_o),
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.wbm_cti_o (iwbm_cti_o),
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.wbm_bte_o (iwbm_bte_o),
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.wbm_dat_o (iwbm_dat_o),
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// Inputs
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.cpu_adr_i (ibus_adr_o),
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.cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}),
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.cpu_req_i (ibus_req_o),
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.cpu_we_i (1'b0),
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.cpu_bsel_i (4'b1111),
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.cpu_burst_i (ibus_burst_o),
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.wbm_err_i (iwbm_err_i),
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.wbm_ack_i (iwbm_ack_i),
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.wbm_dat_i (iwbm_dat_i),
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.wbm_rty_i (iwbm_rty_i),
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); */
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mor1kx_bus_if_wb32
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#(.BUS_IF_TYPE(IBUS_WB_TYPE),
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.BURST_LENGTH((FEATURE_INSTRUCTIONCACHE != "NONE") ?
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((OPTION_ICACHE_BLOCK_WIDTH == 4) ? 4 :
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((OPTION_ICACHE_BLOCK_WIDTH == 5) ? 8 : 1))
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: 1 ))
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ibus_bridge
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(/*AUTOINST*/
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// Outputs
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.cpu_err_o (ibus_err_i), // Templated
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.cpu_ack_o (ibus_ack_i), // Templated
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.cpu_dat_o (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]), // Templated
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.wbm_adr_o (iwbm_adr_o), // Templated
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.wbm_stb_o (iwbm_stb_o), // Templated
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.wbm_cyc_o (iwbm_cyc_o), // Templated
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.wbm_sel_o (iwbm_sel_o), // Templated
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.wbm_we_o (iwbm_we_o), // Templated
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.wbm_cti_o (iwbm_cti_o), // Templated
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.wbm_bte_o (iwbm_bte_o), // Templated
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.wbm_dat_o (iwbm_dat_o), // Templated
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// Inputs
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.clk (clk),
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.rst (rst),
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.cpu_adr_i (ibus_adr_o), // Templated
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.cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}), // Templated
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.cpu_req_i (ibus_req_o), // Templated
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.cpu_bsel_i (4'b1111), // Templated
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.cpu_we_i (1'b0), // Templated
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.cpu_burst_i (ibus_burst_o), // Templated
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.wbm_err_i (iwbm_err_i), // Templated
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.wbm_ack_i (iwbm_ack_i), // Templated
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.wbm_dat_i (iwbm_dat_i), // Templated
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.wbm_rty_i (iwbm_rty_i)); // Templated
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/* mor1kx_bus_if_wb32 AUTO_TEMPLATE (
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.cpu_err_o (dbus_err_i),
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.cpu_ack_o (dbus_ack_i),
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.cpu_dat_o (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]),
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.wbm_adr_o (dwbm_adr_o),
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.wbm_stb_o (dwbm_stb_o),
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.wbm_cyc_o (dwbm_cyc_o),
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.wbm_sel_o (dwbm_sel_o),
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.wbm_we_o (dwbm_we_o),
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.wbm_cti_o (dwbm_cti_o),
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.wbm_bte_o (dwbm_bte_o),
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.wbm_dat_o (dwbm_dat_o),
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// Inputs
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.cpu_adr_i (dbus_adr_o[31:0]),
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.cpu_dat_i (dbus_dat_o),
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.cpu_req_i (dbus_req_o),
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.cpu_we_i (dbus_we_o),
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.cpu_bsel_i (dbus_bsel_o),
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.cpu_burst_i (dbus_burst_o),
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.wbm_err_i (dwbm_err_i),
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.wbm_ack_i (dwbm_ack_i),
|
| 292 |
|
|
.wbm_dat_i (dwbm_dat_i),
|
| 293 |
|
|
.wbm_rty_i (dwbm_rty_i),
|
| 294 |
|
|
); */
|
| 295 |
|
|
|
| 296 |
|
|
mor1kx_bus_if_wb32
|
| 297 |
|
|
#(.BUS_IF_TYPE(DBUS_WB_TYPE),
|
| 298 |
|
|
.BURST_LENGTH((FEATURE_DATACACHE != "NONE") ?
|
| 299 |
|
|
((OPTION_DCACHE_BLOCK_WIDTH == 4) ? 4 :
|
| 300 |
|
|
((OPTION_DCACHE_BLOCK_WIDTH == 5) ? 8 : 1))
|
| 301 |
|
|
: 1 ))
|
| 302 |
|
|
dbus_bridge
|
| 303 |
|
|
(/*AUTOINST*/
|
| 304 |
|
|
// Outputs
|
| 305 |
|
|
.cpu_err_o (dbus_err_i), // Templated
|
| 306 |
|
|
.cpu_ack_o (dbus_ack_i), // Templated
|
| 307 |
|
|
.cpu_dat_o (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
| 308 |
|
|
.wbm_adr_o (dwbm_adr_o), // Templated
|
| 309 |
|
|
.wbm_stb_o (dwbm_stb_o), // Templated
|
| 310 |
|
|
.wbm_cyc_o (dwbm_cyc_o), // Templated
|
| 311 |
|
|
.wbm_sel_o (dwbm_sel_o), // Templated
|
| 312 |
|
|
.wbm_we_o (dwbm_we_o), // Templated
|
| 313 |
|
|
.wbm_cti_o (dwbm_cti_o), // Templated
|
| 314 |
|
|
.wbm_bte_o (dwbm_bte_o), // Templated
|
| 315 |
|
|
.wbm_dat_o (dwbm_dat_o), // Templated
|
| 316 |
|
|
// Inputs
|
| 317 |
|
|
.clk (clk),
|
| 318 |
|
|
.rst (rst),
|
| 319 |
|
|
.cpu_adr_i (dbus_adr_o[31:0]), // Templated
|
| 320 |
|
|
.cpu_dat_i (dbus_dat_o), // Templated
|
| 321 |
|
|
.cpu_req_i (dbus_req_o), // Templated
|
| 322 |
|
|
.cpu_bsel_i (dbus_bsel_o), // Templated
|
| 323 |
|
|
.cpu_we_i (dbus_we_o), // Templated
|
| 324 |
|
|
.cpu_burst_i (dbus_burst_o), // Templated
|
| 325 |
|
|
.wbm_err_i (dwbm_err_i), // Templated
|
| 326 |
|
|
.wbm_ack_i (dwbm_ack_i), // Templated
|
| 327 |
|
|
.wbm_dat_i (dwbm_dat_i), // Templated
|
| 328 |
|
|
.wbm_rty_i (dwbm_rty_i)); // Templated
|
| 329 |
|
|
|
| 330 |
|
|
end else if (BUS_IF_TYPE=="AVALON") begin // block: bus_gen
|
| 331 |
|
|
/* mor1kx_bus_if_avalon AUTO_TEMPLATE (
|
| 332 |
|
|
.cpu_err_o (ibus_err_i),
|
| 333 |
|
|
.cpu_ack_o (ibus_ack_i),
|
| 334 |
|
|
.cpu_dat_o (ibus_dat_i),
|
| 335 |
|
|
.avm_address_o (avm_i_address_o),
|
| 336 |
|
|
.avm_byteenable_o (avm_i_byteenable_o),
|
| 337 |
|
|
.avm_read_o (avm_i_read_o),
|
| 338 |
|
|
.avm_burstcount_o (avm_i_burstcount_o),
|
| 339 |
|
|
.avm_write_o (avm_i_write_o),
|
| 340 |
|
|
.avm_writedata_o (avm_i_writedata_o),
|
| 341 |
|
|
// Inputs
|
| 342 |
|
|
.cpu_adr_i (ibus_adr_o),
|
| 343 |
|
|
.cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}),
|
| 344 |
|
|
.cpu_req_i (ibus_req_o),
|
| 345 |
|
|
.cpu_we_i (1'b0),
|
| 346 |
|
|
.cpu_bsel_i (4'b1111),
|
| 347 |
|
|
.cpu_burst_i (ibus_burst_o),
|
| 348 |
|
|
.avm_readdata_i (avm_i_readdata_i),
|
| 349 |
|
|
.avm_waitrequest_i (avm_i_waitrequest_i),
|
| 350 |
|
|
.avm_readdatavalid_i (avm_i_readdatavalid_i),
|
| 351 |
|
|
); */
|
| 352 |
|
|
|
| 353 |
|
|
mor1kx_bus_if_avalon
|
| 354 |
|
|
#(.OPTION_AVALON_BURST_LENGTH((1<<OPTION_ICACHE_BLOCK_WIDTH)/4))
|
| 355 |
|
|
ibus_bridge
|
| 356 |
|
|
(/*AUTOINST*/
|
| 357 |
|
|
// Outputs
|
| 358 |
|
|
.cpu_err_o (ibus_err_i), // Templated
|
| 359 |
|
|
.cpu_ack_o (ibus_ack_i), // Templated
|
| 360 |
|
|
.cpu_dat_o (ibus_dat_i), // Templated
|
| 361 |
|
|
.avm_address_o (avm_i_address_o), // Templated
|
| 362 |
|
|
.avm_byteenable_o (avm_i_byteenable_o), // Templated
|
| 363 |
|
|
.avm_read_o (avm_i_read_o), // Templated
|
| 364 |
|
|
.avm_burstcount_o (avm_i_burstcount_o), // Templated
|
| 365 |
|
|
.avm_write_o (avm_i_write_o), // Templated
|
| 366 |
|
|
.avm_writedata_o (avm_i_writedata_o), // Templated
|
| 367 |
|
|
// Inputs
|
| 368 |
|
|
.clk (clk),
|
| 369 |
|
|
.rst (rst),
|
| 370 |
|
|
.cpu_adr_i (ibus_adr_o), // Templated
|
| 371 |
|
|
.cpu_dat_i ({OPTION_OPERAND_WIDTH{1'b0}}), // Templated
|
| 372 |
|
|
.cpu_req_i (ibus_req_o), // Templated
|
| 373 |
|
|
.cpu_bsel_i (4'b1111), // Templated
|
| 374 |
|
|
.cpu_we_i (1'b0), // Templated
|
| 375 |
|
|
.cpu_burst_i (ibus_burst_o), // Templated
|
| 376 |
|
|
.avm_readdata_i (avm_i_readdata_i), // Templated
|
| 377 |
|
|
.avm_waitrequest_i (avm_i_waitrequest_i), // Templated
|
| 378 |
|
|
.avm_readdatavalid_i (avm_i_readdatavalid_i)); // Templated
|
| 379 |
|
|
|
| 380 |
|
|
/* mor1kx_bus_if_avalon AUTO_TEMPLATE (
|
| 381 |
|
|
.cpu_err_o (dbus_err_i),
|
| 382 |
|
|
.cpu_ack_o (dbus_ack_i),
|
| 383 |
|
|
.cpu_dat_o (dbus_dat_i),
|
| 384 |
|
|
.avm_address_o (avm_d_address_o),
|
| 385 |
|
|
.avm_byteenable_o (avm_d_byteenable_o),
|
| 386 |
|
|
.avm_read_o (avm_d_read_o),
|
| 387 |
|
|
.avm_burstcount_o (avm_d_burstcount_o),
|
| 388 |
|
|
.avm_write_o (avm_d_write_o),
|
| 389 |
|
|
.avm_writedata_o (avm_d_writedata_o),
|
| 390 |
|
|
// Inputs
|
| 391 |
|
|
.cpu_adr_i (dbus_adr_o),
|
| 392 |
|
|
.cpu_dat_i (dbus_dat_o),
|
| 393 |
|
|
.cpu_req_i (dbus_req_o),
|
| 394 |
|
|
.cpu_we_i (dbus_we_o),
|
| 395 |
|
|
.cpu_bsel_i (dbus_bsel_o),
|
| 396 |
|
|
.cpu_burst_i (dbus_burst_o),
|
| 397 |
|
|
.avm_readdata_i (avm_d_readdata_i),
|
| 398 |
|
|
.avm_waitrequest_i (avm_d_waitrequest_i),
|
| 399 |
|
|
.avm_readdatavalid_i (avm_d_readdatavalid_i),
|
| 400 |
|
|
); */
|
| 401 |
|
|
|
| 402 |
|
|
mor1kx_bus_if_avalon
|
| 403 |
|
|
#(.OPTION_AVALON_BURST_LENGTH((1<<OPTION_DCACHE_BLOCK_WIDTH)/4))
|
| 404 |
|
|
dbus_bridge
|
| 405 |
|
|
(/*AUTOINST*/
|
| 406 |
|
|
// Outputs
|
| 407 |
|
|
.cpu_err_o (dbus_err_i), // Templated
|
| 408 |
|
|
.cpu_ack_o (dbus_ack_i), // Templated
|
| 409 |
|
|
.cpu_dat_o (dbus_dat_i), // Templated
|
| 410 |
|
|
.avm_address_o (avm_d_address_o), // Templated
|
| 411 |
|
|
.avm_byteenable_o (avm_d_byteenable_o), // Templated
|
| 412 |
|
|
.avm_read_o (avm_d_read_o), // Templated
|
| 413 |
|
|
.avm_burstcount_o (avm_d_burstcount_o), // Templated
|
| 414 |
|
|
.avm_write_o (avm_d_write_o), // Templated
|
| 415 |
|
|
.avm_writedata_o (avm_d_writedata_o), // Templated
|
| 416 |
|
|
// Inputs
|
| 417 |
|
|
.clk (clk),
|
| 418 |
|
|
.rst (rst),
|
| 419 |
|
|
.cpu_adr_i (dbus_adr_o), // Templated
|
| 420 |
|
|
.cpu_dat_i (dbus_dat_o), // Templated
|
| 421 |
|
|
.cpu_req_i (dbus_req_o), // Templated
|
| 422 |
|
|
.cpu_bsel_i (dbus_bsel_o), // Templated
|
| 423 |
|
|
.cpu_we_i (dbus_we_o), // Templated
|
| 424 |
|
|
.cpu_burst_i (dbus_burst_o), // Templated
|
| 425 |
|
|
.avm_readdata_i (avm_d_readdata_i), // Templated
|
| 426 |
|
|
.avm_waitrequest_i (avm_d_waitrequest_i), // Templated
|
| 427 |
|
|
.avm_readdatavalid_i (avm_d_readdatavalid_i)); // Templated
|
| 428 |
|
|
|
| 429 |
|
|
end else begin
|
| 430 |
|
|
initial begin
|
| 431 |
|
|
$display("Error: BUS_IF_TYPE not correct");
|
| 432 |
|
|
$finish();
|
| 433 |
|
|
end
|
| 434 |
|
|
end // else: !if(BUS_IF_TYPE=="WISHBONE32")
|
| 435 |
|
|
endgenerate
|
| 436 |
|
|
|
| 437 |
|
|
/* mor1kx_cpu AUTO_TEMPLATE
|
| 438 |
|
|
(
|
| 439 |
|
|
.spr_bus_dat_dmmu_i (),
|
| 440 |
|
|
.spr_bus_ack_dmmu_i (),
|
| 441 |
|
|
.spr_bus_dat_immu_i (),
|
| 442 |
|
|
.spr_bus_ack_immu_i (),
|
| 443 |
|
|
.spr_bus_dat_mac_i (),
|
| 444 |
|
|
.spr_bus_ack_mac_i (),
|
| 445 |
|
|
.spr_bus_dat_pmu_i (),
|
| 446 |
|
|
.spr_bus_ack_pmu_i (),
|
| 447 |
|
|
.spr_bus_dat_pcu_i (),
|
| 448 |
|
|
.spr_bus_ack_pcu_i (),
|
| 449 |
|
|
.spr_bus_dat_fpu_i (),
|
| 450 |
|
|
.spr_bus_ack_fpu_i (),
|
| 451 |
|
|
); */
|
| 452 |
|
|
mor1kx_cpu
|
| 453 |
|
|
#(
|
| 454 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
| 455 |
|
|
.OPTION_CPU(OPTION_CPU0),
|
| 456 |
|
|
.FEATURE_DATACACHE(FEATURE_DATACACHE),
|
| 457 |
|
|
.OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH),
|
| 458 |
|
|
.OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH),
|
| 459 |
|
|
.OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS),
|
| 460 |
|
|
.OPTION_DCACHE_LIMIT_WIDTH(OPTION_DCACHE_LIMIT_WIDTH),
|
| 461 |
|
|
.OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP),
|
| 462 |
|
|
.FEATURE_DMMU(FEATURE_DMMU),
|
| 463 |
|
|
.FEATURE_DMMU_HW_TLB_RELOAD(FEATURE_DMMU_HW_TLB_RELOAD),
|
| 464 |
|
|
.OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH),
|
| 465 |
|
|
.OPTION_DMMU_WAYS(OPTION_DMMU_WAYS),
|
| 466 |
|
|
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
|
| 467 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH),
|
| 468 |
|
|
.OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH),
|
| 469 |
|
|
.OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS),
|
| 470 |
|
|
.OPTION_ICACHE_LIMIT_WIDTH(OPTION_ICACHE_LIMIT_WIDTH),
|
| 471 |
|
|
.FEATURE_IMMU(FEATURE_IMMU),
|
| 472 |
|
|
.FEATURE_IMMU_HW_TLB_RELOAD(FEATURE_IMMU_HW_TLB_RELOAD),
|
| 473 |
|
|
.OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH),
|
| 474 |
|
|
.OPTION_IMMU_WAYS(OPTION_IMMU_WAYS),
|
| 475 |
|
|
.FEATURE_PIC(FEATURE_PIC),
|
| 476 |
|
|
.FEATURE_TIMER(FEATURE_TIMER),
|
| 477 |
|
|
.FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT),
|
| 478 |
|
|
.FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS),
|
| 479 |
|
|
.FEATURE_MAC(FEATURE_MAC),
|
| 480 |
|
|
.FEATURE_SYSCALL(FEATURE_SYSCALL),
|
| 481 |
|
|
.FEATURE_TRAP(FEATURE_TRAP),
|
| 482 |
|
|
.FEATURE_RANGE(FEATURE_RANGE),
|
| 483 |
|
|
.OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER),
|
| 484 |
|
|
.OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH),
|
| 485 |
|
|
.FEATURE_DSX(FEATURE_DSX),
|
| 486 |
|
|
.FEATURE_OVERFLOW(FEATURE_OVERFLOW),
|
| 487 |
|
|
.FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG),
|
| 488 |
|
|
.FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS),
|
| 489 |
|
|
.OPTION_RF_NUM_SHADOW_GPR(OPTION_RF_NUM_SHADOW_GPR),
|
| 490 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
| 491 |
|
|
.OPTION_RF_WORDS(OPTION_RF_WORDS),
|
| 492 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
| 493 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER),
|
| 494 |
|
|
.FEATURE_DIVIDER(FEATURE_DIVIDER),
|
| 495 |
|
|
.FEATURE_ADDC(FEATURE_ADDC),
|
| 496 |
|
|
.FEATURE_SRA(FEATURE_SRA),
|
| 497 |
|
|
.FEATURE_ROR(FEATURE_ROR),
|
| 498 |
|
|
.FEATURE_EXT(FEATURE_EXT),
|
| 499 |
|
|
.FEATURE_CMOV(FEATURE_CMOV),
|
| 500 |
|
|
.FEATURE_FFL1(FEATURE_FFL1),
|
| 501 |
|
|
.FEATURE_ATOMIC(FEATURE_ATOMIC),
|
| 502 |
|
|
.FEATURE_CUST1(FEATURE_CUST1),
|
| 503 |
|
|
.FEATURE_CUST2(FEATURE_CUST2),
|
| 504 |
|
|
.FEATURE_CUST3(FEATURE_CUST3),
|
| 505 |
|
|
.FEATURE_CUST4(FEATURE_CUST4),
|
| 506 |
|
|
.FEATURE_CUST5(FEATURE_CUST5),
|
| 507 |
|
|
.FEATURE_CUST6(FEATURE_CUST6),
|
| 508 |
|
|
.FEATURE_CUST7(FEATURE_CUST7),
|
| 509 |
|
|
.FEATURE_CUST8(FEATURE_CUST8),
|
| 510 |
|
|
.OPTION_SHIFTER(OPTION_SHIFTER),
|
| 511 |
|
|
.FEATURE_STORE_BUFFER(FEATURE_STORE_BUFFER),
|
| 512 |
|
|
.OPTION_STORE_BUFFER_DEPTH_WIDTH(OPTION_STORE_BUFFER_DEPTH_WIDTH),
|
| 513 |
|
|
.FEATURE_MULTICORE(FEATURE_MULTICORE),
|
| 514 |
|
|
.FEATURE_TRACEPORT_EXEC(FEATURE_TRACEPORT_EXEC)
|
| 515 |
|
|
)
|
| 516 |
|
|
mor1kx_cpu
|
| 517 |
|
|
(/*AUTOINST*/
|
| 518 |
|
|
// Outputs
|
| 519 |
|
|
.ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
| 520 |
|
|
.ibus_req_o (ibus_req_o),
|
| 521 |
|
|
.ibus_burst_o (ibus_burst_o),
|
| 522 |
|
|
.dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
| 523 |
|
|
.dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
| 524 |
|
|
.dbus_req_o (dbus_req_o),
|
| 525 |
|
|
.dbus_bsel_o (dbus_bsel_o[3:0]),
|
| 526 |
|
|
.dbus_we_o (dbus_we_o),
|
| 527 |
|
|
.dbus_burst_o (dbus_burst_o),
|
| 528 |
|
|
.du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
| 529 |
|
|
.du_ack_o (du_ack_o),
|
| 530 |
|
|
.du_stall_o (du_stall_o),
|
| 531 |
|
|
.traceport_exec_valid_o (traceport_exec_valid_o),
|
| 532 |
|
|
.traceport_exec_pc_o (traceport_exec_pc_o[31:0]),
|
| 533 |
|
|
.traceport_exec_insn_o (traceport_exec_insn_o[`OR1K_INSN_WIDTH-1:0]),
|
| 534 |
|
|
.traceport_exec_wbdata_o (traceport_exec_wbdata_o[OPTION_OPERAND_WIDTH-1:0]),
|
| 535 |
|
|
.traceport_exec_wbreg_o (traceport_exec_wbreg_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
| 536 |
|
|
.traceport_exec_wben_o (traceport_exec_wben_o),
|
| 537 |
|
|
.spr_bus_addr_o (spr_bus_addr_o[15:0]),
|
| 538 |
|
|
.spr_bus_we_o (spr_bus_we_o),
|
| 539 |
|
|
.spr_bus_stb_o (spr_bus_stb_o),
|
| 540 |
|
|
.spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
| 541 |
|
|
.spr_sr_o (spr_sr_o[15:0]),
|
| 542 |
|
|
// Inputs
|
| 543 |
|
|
.clk (clk),
|
| 544 |
|
|
.rst (rst),
|
| 545 |
|
|
.ibus_err_i (ibus_err_i),
|
| 546 |
|
|
.ibus_ack_i (ibus_ack_i),
|
| 547 |
|
|
.ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]),
|
| 548 |
|
|
.dbus_err_i (dbus_err_i),
|
| 549 |
|
|
.dbus_ack_i (dbus_ack_i),
|
| 550 |
|
|
.dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]),
|
| 551 |
|
|
.irq_i (irq_i[31:0]),
|
| 552 |
|
|
.du_addr_i (du_addr_i[15:0]),
|
| 553 |
|
|
.du_stb_i (du_stb_i),
|
| 554 |
|
|
.du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]),
|
| 555 |
|
|
.du_we_i (du_we_i),
|
| 556 |
|
|
.du_stall_i (du_stall_i),
|
| 557 |
|
|
.spr_bus_dat_dmmu_i (), // Templated
|
| 558 |
|
|
.spr_bus_ack_dmmu_i (), // Templated
|
| 559 |
|
|
.spr_bus_dat_immu_i (), // Templated
|
| 560 |
|
|
.spr_bus_ack_immu_i (), // Templated
|
| 561 |
|
|
.spr_bus_dat_mac_i (), // Templated
|
| 562 |
|
|
.spr_bus_ack_mac_i (), // Templated
|
| 563 |
|
|
.spr_bus_dat_pmu_i (), // Templated
|
| 564 |
|
|
.spr_bus_ack_pmu_i (), // Templated
|
| 565 |
|
|
.spr_bus_dat_pcu_i (), // Templated
|
| 566 |
|
|
.spr_bus_ack_pcu_i (), // Templated
|
| 567 |
|
|
.spr_bus_dat_fpu_i (), // Templated
|
| 568 |
|
|
.spr_bus_ack_fpu_i (), // Templated
|
| 569 |
|
|
.multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]),
|
| 570 |
|
|
.multicore_numcores_i (multicore_numcores_i[OPTION_OPERAND_WIDTH-1:0]),
|
| 571 |
|
|
.snoop_adr_i (snoop_adr_i[31:0]),
|
| 572 |
|
|
.snoop_en_i (snoop_en_i));
|
| 573 |
|
|
|
| 574 |
|
|
endmodule // mor1kx
|
