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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_bus_if_avalon.v] - Blame information for rev 38

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/* ****************************************************************************
  This Source Code Form is subject to the terms of the
  Open Hardware Description License, v. 1.0. If a copy
  of the OHDL was not distributed with this file, You
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
  Description: mor1kx processor avalon bus bridge
 
  Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
***************************************************************************** */
 
`include "mor1kx-defines.v"
 
module mor1kx_bus_if_avalon
#(
  parameter OPTION_AVALON_BURST_LENGTH = 4
  )
  (
   input         clk,
   input         rst,
 
   output        cpu_err_o,
   output        cpu_ack_o,
   output [31:0] cpu_dat_o,
   input [31:0]  cpu_adr_i,
   input [31:0]  cpu_dat_i,
   input         cpu_req_i,
   input [3:0]    cpu_bsel_i,
   input         cpu_we_i,
   input         cpu_burst_i,
 
   output [31:0] avm_address_o,
   output [3:0]  avm_byteenable_o,
   output        avm_read_o,
   input [31:0]  avm_readdata_i,
   output [3:0]  avm_burstcount_o,
   output        avm_write_o,
   output [31:0] avm_writedata_o,
   input         avm_waitrequest_i,
   input         avm_readdatavalid_i
   );
 
   localparam IDLE      = 4'b0001;
   localparam READ      = 4'b0010;
   localparam BURST     = 4'b0100;
   localparam WRITE     = 4'b1000;
 
   reg [3:0]      state;
 
   always @(posedge clk) begin
      case (state)
        IDLE: begin
           if (cpu_req_i & !avm_waitrequest_i) begin
              if (cpu_we_i)
                state <= WRITE;
              else if (cpu_burst_i) begin
                state <= BURST;
              end else
                state <= READ;
           end
        end
 
        READ: begin
           if (avm_readdatavalid_i)
             state <= IDLE;
        end
 
        BURST: begin
           /* cpu_burst_i deasserts when the last burst access starts */
           if (!cpu_burst_i & avm_readdatavalid_i)
             state <= IDLE;
        end
 
        WRITE: begin
             state <= IDLE;
        end
      endcase
   end
 
   assign avm_address_o = cpu_adr_i;
   assign avm_read_o = cpu_req_i & !cpu_we_i & (state == IDLE);
   assign avm_byteenable_o = cpu_bsel_i;
   assign avm_write_o = cpu_req_i & cpu_we_i & (state == IDLE);
   assign avm_burstcount_o = cpu_burst_i & (state != BURST) ?
                             OPTION_AVALON_BURST_LENGTH : 4'd1;
   assign avm_writedata_o = cpu_dat_i;
 
   assign cpu_err_o = 0;
   assign cpu_ack_o = avm_readdatavalid_i | state == WRITE;
   assign cpu_dat_o = avm_readdata_i;
 
 
endmodule

Line No.	Rev	Author	Line
1	38	alirezamon	`/* ****************************************************************************`
2			`This Source Code Form is subject to the terms of the`
3			`Open Hardware Description License, v. 1.0. If a copy`
4			`of the OHDL was not distributed with this file, You`
5			`can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt`
6
7			`Description: mor1kx processor avalon bus bridge`
8
9			`Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>`
10
11			`***************************************************************************** */`
12
13			`include "mor1kx-defines.v"
14
15			`module mor1kx_bus_if_avalon`
16			`#(`
17			`parameter OPTION_AVALON_BURST_LENGTH = 4`
18			`)`
19			`(`
20			`input clk,`
21			`input rst,`
22
23			`output cpu_err_o,`
24			`output cpu_ack_o,`
25			`output [31:0] cpu_dat_o,`
26			`input [31:0] cpu_adr_i,`
27			`input [31:0] cpu_dat_i,`
28			`input cpu_req_i,`
29			`input [3:0] cpu_bsel_i,`
30			`input cpu_we_i,`
31			`input cpu_burst_i,`
32
33			`output [31:0] avm_address_o,`
34			`output [3:0] avm_byteenable_o,`
35			`output avm_read_o,`
36			`input [31:0] avm_readdata_i,`
37			`output [3:0] avm_burstcount_o,`
38			`output avm_write_o,`
39			`output [31:0] avm_writedata_o,`
40			`input avm_waitrequest_i,`
41			`input avm_readdatavalid_i`
42			`);`
43
44			`localparam IDLE = 4'b0001;`
45			`localparam READ = 4'b0010;`
46			`localparam BURST = 4'b0100;`
47			`localparam WRITE = 4'b1000;`
48
49			`reg [3:0] state;`
50
51			`always @(posedge clk) begin`
52			`case (state)`
53			`IDLE: begin`
54			`if (cpu_req_i & !avm_waitrequest_i) begin`
55			`if (cpu_we_i)`
56			`state <= WRITE;`
57			`else if (cpu_burst_i) begin`
58			`state <= BURST;`
59			`end else`
60			`state <= READ;`
61			`end`
62			`end`
63
64			`READ: begin`
65			`if (avm_readdatavalid_i)`
66			`state <= IDLE;`
67			`end`
68
69			`BURST: begin`
70			`/* cpu_burst_i deasserts when the last burst access starts */`
71			`if (!cpu_burst_i & avm_readdatavalid_i)`
72			`state <= IDLE;`
73			`end`
74
75			`WRITE: begin`
76			`state <= IDLE;`
77			`end`
78			`endcase`
79			`end`
80
81			`assign avm_address_o = cpu_adr_i;`
82			`assign avm_read_o = cpu_req_i & !cpu_we_i & (state == IDLE);`
83			`assign avm_byteenable_o = cpu_bsel_i;`
84			`assign avm_write_o = cpu_req_i & cpu_we_i & (state == IDLE);`
85			`assign avm_burstcount_o = cpu_burst_i & (state != BURST) ?`
86			`OPTION_AVALON_BURST_LENGTH : 4'd1;`
87			`assign avm_writedata_o = cpu_dat_i;`
88
89			`assign cpu_err_o = 0;`
90			`assign cpu_ack_o = avm_readdatavalid_i \| state == WRITE;`
91			`assign cpu_dat_o = avm_readdata_i;`
92
93
94			`endmodule`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_bus_if_avalon.v] - Blame information for rev 38